sys/powerpc/fpu/fpu_emu.c

   1 /*      $NetBSD: fpu_emu.c,v 1.14 2005/12/11 12:18:42 christos Exp $ */
   2
   3 /*
   4  * Copyright 2001 Wasabi Systems, Inc.
   5  * All rights reserved.
   6  *
   7  * Written by Eduardo Horvath and Simon Burge for Wasabi Systems, Inc.
   8  *
   9  * Redistribution and use in source and binary forms, with or without
  10  * modification, are permitted provided that the following conditions
  11  * are met:
  12  * 1. Redistributions of source code must retain the above copyright
  13  *    notice, this list of conditions and the following disclaimer.
  14  * 2. Redistributions in binary form must reproduce the above copyright
  15  *    notice, this list of conditions and the following disclaimer in the
  16  *    documentation and/or other materials provided with the distribution.
  17  * 3. All advertising materials mentioning features or use of this software
  18  *    must display the following acknowledgement:
  19  *      This product includes software developed for the NetBSD Project by
  20  *      Wasabi Systems, Inc.
  21  * 4. The name of Wasabi Systems, Inc. may not be used to endorse
  22  *    or promote products derived from this software without specific prior
  23  *    written permission.
  24  *
  25  * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
  26  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
  27  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  28  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL WASABI SYSTEMS, INC
  29  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  30  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  31  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  32  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  33  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  34  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  35  * POSSIBILITY OF SUCH DAMAGE.
  36  */
  37
  38 /*
  39  * Copyright (c) 1992, 1993
  40  *      The Regents of the University of California.  All rights reserved.
  41  *
  42  * This software was developed by the Computer Systems Engineering group
  43  * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
  44  * contributed to Berkeley.
  45  *
  46  * All advertising materials mentioning features or use of this software
  47  * must display the following acknowledgement:
  48  *      This product includes software developed by the University of
  49  *      California, Lawrence Berkeley Laboratory.
  50  *
  51  * Redistribution and use in source and binary forms, with or without
  52  * modification, are permitted provided that the following conditions
  53  * are met:
  54  * 1. Redistributions of source code must retain the above copyright
  55  *    notice, this list of conditions and the following disclaimer.
  56  * 2. Redistributions in binary form must reproduce the above copyright
  57  *    notice, this list of conditions and the following disclaimer in the
  58  *    documentation and/or other materials provided with the distribution.
  59  * 3. Neither the name of the University nor the names of its contributors
  60  *    may be used to endorse or promote products derived from this software
  61  *    without specific prior written permission.
  62  *
  63  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
  64  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  65  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  66  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
  67  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  68  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  69  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  70  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  71  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  72  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  73  * SUCH DAMAGE.
  74  *
  75  *      @(#)fpu.c       8.1 (Berkeley) 6/11/93
  76  */
  77
  78 #include <sys/cdefs.h>
  79 __FBSDID("$FreeBSD$");
  80
  81 #include "opt_ddb.h"
  82
  83 #include <sys/param.h>
  84 #include <sys/systm.h>
  85 #include <sys/kdb.h>
  86 #include <sys/kernel.h>
  87 #include <sys/proc.h>
  88 #include <sys/sysctl.h>
  89 #include <sys/signal.h>
  90 #include <sys/syslog.h>
  91 #include <sys/signalvar.h>
  92
  93 #include <machine/fpu.h>
  94 #include <machine/reg.h>
  95
  96 #include <powerpc/fpu/fpu_emu.h>
  97 #include <powerpc/fpu/fpu_extern.h>
  98 #include <powerpc/fpu/fpu_instr.h>
  99
 100 static SYSCTL_NODE(_hw, OID_AUTO, fpu_emu, CTLFLAG_RW, 0, "FPU emulator");
 101
 102 #define FPU_EMU_EVCNT_DECL(name)                                        \
 103 static u_int fpu_emu_evcnt_##name;                                      \
 104 SYSCTL_INT(_hw_fpu_emu, OID_AUTO, evcnt_##name, CTLFLAG_RD,             \
 105     &fpu_emu_evcnt_##name, 0, "")
 106
 107 #define FPU_EMU_EVCNT_INCR(name)        fpu_emu_evcnt_##name++
 108
 109 FPU_EMU_EVCNT_DECL(stfiwx);
 110 FPU_EMU_EVCNT_DECL(fpstore);
 111 FPU_EMU_EVCNT_DECL(fpload);
 112 FPU_EMU_EVCNT_DECL(fcmpu);
 113 FPU_EMU_EVCNT_DECL(frsp);
 114 FPU_EMU_EVCNT_DECL(fctiw);
 115 FPU_EMU_EVCNT_DECL(fcmpo);
 116 FPU_EMU_EVCNT_DECL(mtfsb1);
 117 FPU_EMU_EVCNT_DECL(fnegabs);
 118 FPU_EMU_EVCNT_DECL(mcrfs);
 119 FPU_EMU_EVCNT_DECL(mtfsb0);
 120 FPU_EMU_EVCNT_DECL(fmr);
 121 FPU_EMU_EVCNT_DECL(mtfsfi);
 122 FPU_EMU_EVCNT_DECL(fnabs);
 123 FPU_EMU_EVCNT_DECL(fabs);
 124 FPU_EMU_EVCNT_DECL(mffs);
 125 FPU_EMU_EVCNT_DECL(mtfsf);
 126 FPU_EMU_EVCNT_DECL(fctid);
 127 FPU_EMU_EVCNT_DECL(fcfid);
 128 FPU_EMU_EVCNT_DECL(fdiv);
 129 FPU_EMU_EVCNT_DECL(fsub);
 130 FPU_EMU_EVCNT_DECL(fadd);
 131 FPU_EMU_EVCNT_DECL(fsqrt);
 132 FPU_EMU_EVCNT_DECL(fsel);
 133 FPU_EMU_EVCNT_DECL(fpres);
 134 FPU_EMU_EVCNT_DECL(fmul);
 135 FPU_EMU_EVCNT_DECL(frsqrte);
 136 FPU_EMU_EVCNT_DECL(fmulsub);
 137 FPU_EMU_EVCNT_DECL(fmuladd);
 138 FPU_EMU_EVCNT_DECL(fnmsub);
 139 FPU_EMU_EVCNT_DECL(fnmadd);
 140
 141 /* FPSR exception masks */
 142 #define FPSR_EX_MSK     (FPSCR_VX|FPSCR_OX|FPSCR_UX|FPSCR_ZX|           \
 143                         FPSCR_XX|FPSCR_VXSNAN|FPSCR_VXISI|FPSCR_VXIDI|  \
 144                         FPSCR_VXZDZ|FPSCR_VXIMZ|FPSCR_VXVC|FPSCR_VXSOFT|\
 145                         FPSCR_VXSQRT|FPSCR_VXCVI)
 146 #define FPSR_EX         (FPSCR_VE|FPSCR_OE|FPSCR_UE|FPSCR_ZE|FPSCR_XE)
 147 #define FPSR_EXOP       (FPSR_EX_MSK&(~FPSR_EX))
 148
 149 int fpe_debug = 0;
 150
 151 #ifdef DEBUG
 152 vm_offset_t opc_disasm(vm_offset_t, int);
 153
 154 /*
 155  * Dump a `fpn' structure.
 156  */
 157 void
 158 fpu_dumpfpn(struct fpn *fp)
 159 {
 160         static const char *class[] = {
 161                 "SNAN", "QNAN", "ZERO", "NUM", "INF"
 162         };
 163
 164         printf("%s %c.%x %x %x %xE%d", class[fp->fp_class + 2],
 165                 fp->fp_sign ? '-' : ' ',
 166                 fp->fp_mant[0], fp->fp_mant[1],
 167                 fp->fp_mant[2], fp->fp_mant[3],
 168                 fp->fp_exp);
 169 }
 170 #endif
 171
 172 /*
 173  * fpu_execute returns the following error numbers (0 = no error):
 174  */
 175 #define FPE             1       /* take a floating point exception */
 176 #define NOTFPU          2       /* not an FPU instruction */
 177 #define FAULT           3
 178
 179
 180 /*
 181  * Emulate a floating-point instruction.
 182  * Return zero for success, else signal number.
 183  * (Typically: zero, SIGFPE, SIGILL, SIGSEGV)
 184  */
 185 int
 186 fpu_emulate(struct trapframe *frame, struct fpu *fpf)
 187 {
 188         union instr insn;
 189         struct fpemu fe;
 190         static int lastill = 0;
 191         int sig;
 192
 193         /* initialize insn.is_datasize to tell it is *not* initialized */
 194         fe.fe_fpstate = fpf;
 195         fe.fe_cx = 0;
 196
 197         /* always set this (to avoid a warning) */
 198
 199         if (copyin((void *) (frame->srr0), &insn.i_int, sizeof (insn.i_int))) {
 200 #ifdef DEBUG
 201                 printf("fpu_emulate: fault reading opcode\n");
 202 #endif
 203                 return SIGSEGV;
 204         }
 205
 206         DPRINTF(FPE_EX, ("fpu_emulate: emulating insn %x at %p\n",
 207             insn.i_int, (void *)frame->srr0));
 208
 209
 210         if ((insn.i_any.i_opcd == OPC_TWI) ||
 211             ((insn.i_any.i_opcd == OPC_integer_31) &&
 212             (insn.i_x.i_xo == OPC31_TW))) {
 213                 /* Check for the two trap insns. */
 214                 DPRINTF(FPE_EX, ("fpu_emulate: SIGTRAP\n"));
 215                 return (SIGTRAP);
 216         }
 217         sig = 0;
 218         switch (fpu_execute(frame, &fe, &insn)) {
 219         case 0:
 220                 DPRINTF(FPE_EX, ("fpu_emulate: success\n"));
 221                 frame->srr0 += 4;
 222                 break;
 223
 224         case FPE:
 225                 DPRINTF(FPE_EX, ("fpu_emulate: SIGFPE\n"));
 226                 sig = SIGFPE;
 227                 break;
 228
 229         case FAULT:
 230                 DPRINTF(FPE_EX, ("fpu_emulate: SIGSEGV\n"));
 231                 sig = SIGSEGV;
 232                 break;
 233
 234         case NOTFPU:
 235         default:
 236                 DPRINTF(FPE_EX, ("fpu_emulate: SIGILL\n"));
 237 #ifdef DEBUG
 238                 if (fpe_debug & FPE_EX) {
 239                         printf("fpu_emulate:  illegal insn %x at %p:",
 240                         insn.i_int, (void *) (frame->srr0));
 241                         opc_disasm(frame->srr0, insn.i_int);
 242                 }
 243 #endif
 244                 /*
 245                 * XXXX retry an illegal insn once due to cache issues.
 246                 */
 247                 if (lastill == frame->srr0) {
 248                         sig = SIGILL;
 249 #ifdef DEBUG
 250                         if (fpe_debug & FPE_EX)
 251                                 kdb_enter(KDB_WHY_UNSET, "illegal instruction");
 252 #endif
 253                 }
 254                 lastill = frame->srr0;
 255                 break;
 256         }
 257
 258         return (sig);
 259 }
 260
 261 /*
 262  * Execute an FPU instruction (one that runs entirely in the FPU; not
 263  * FBfcc or STF, for instance).  On return, fe->fe_fs->fs_fsr will be
 264  * modified to reflect the setting the hardware would have left.
 265  *
 266  * Note that we do not catch all illegal opcodes, so you can, for instance,
 267  * multiply two integers this way.
 268  */
 269 int
 270 fpu_execute(struct trapframe *tf, struct fpemu *fe, union instr *insn)
 271 {
 272         struct fpn *fp;
 273         union instr instr = *insn;
 274         int *a;
 275         vm_offset_t addr;
 276         int ra, rb, rc, rt, type, mask, fsr, cx, bf, setcr;
 277         unsigned int cond;
 278         struct fpu *fs;
 279
 280         /* Setup work. */
 281         fp = NULL;
 282         fs = fe->fe_fpstate;
 283         fe->fe_fpscr = ((int *)&fs->fpscr)[1];
 284
 285         /*
 286          * On PowerPC all floating point values are stored in registers
 287          * as doubles, even when used for single precision operations.
 288          */
 289         type = FTYPE_DBL;
 290         cond = instr.i_any.i_rc;
 291         setcr = 0;
 292         bf = 0; /* XXX gcc */
 293
 294 #if defined(DDB) && defined(DEBUG)
 295         if (fpe_debug & FPE_EX) {
 296                 vm_offset_t loc = tf->srr0;
 297
 298                 printf("Trying to emulate: %p ", (void *)loc);
 299                 opc_disasm(loc, instr.i_int);
 300         }
 301 #endif
 302
 303         /*
 304          * `Decode' and execute instruction.
 305          */
 306
 307         if ((instr.i_any.i_opcd >= OPC_LFS && instr.i_any.i_opcd <= OPC_STFDU) ||
 308             instr.i_any.i_opcd == OPC_integer_31) {
 309                 /*
 310                  * Handle load/store insns:
 311                  *
 312                  * Convert to/from single if needed, calculate addr,
 313                  * and update index reg if needed.
 314                  */
 315                 double buf;
 316                 size_t size = sizeof(float);
 317                 int store, update;
 318
 319                 cond = 0; /* ld/st never set condition codes */
 320
 321
 322                 if (instr.i_any.i_opcd == OPC_integer_31) {
 323                         if (instr.i_x.i_xo == OPC31_STFIWX) {
 324                                 FPU_EMU_EVCNT_INCR(stfiwx);
 325
 326                                 /* Store as integer */
 327                                 ra = instr.i_x.i_ra;
 328                                 rb = instr.i_x.i_rb;
 329                                 DPRINTF(FPE_INSN,
 330                                         ("reg %d has %jx reg %d has %jx\n",
 331                                         ra, (uintmax_t)tf->fixreg[ra], rb,
 332                                         (uintmax_t)tf->fixreg[rb]));
 333
 334                                 addr = tf->fixreg[rb];
 335                                 if (ra != 0)
 336                                         addr += tf->fixreg[ra];
 337                                 rt = instr.i_x.i_rt;
 338                                 a = (int *)&fs->fpr[rt].fpr;
 339                                 DPRINTF(FPE_INSN,
 340                                         ("fpu_execute: Store INT %x at %p\n",
 341                                                 a[1], (void *)addr));
 342                                 if (copyout(&a[1], (void *)addr, sizeof(int)))
 343                                         return (FAULT);
 344                                 return (0);
 345                         }
 346
 347                         if ((instr.i_x.i_xo & OPC31_FPMASK) != OPC31_FPOP)
 348                                 /* Not an indexed FP load/store op */
 349                                 return (NOTFPU);
 350
 351                         store = (instr.i_x.i_xo & 0x80);
 352                         if (instr.i_x.i_xo & 0x40)
 353                                 size = sizeof(double);
 354                         else
 355                                 type = FTYPE_SNG;
 356                         update = (instr.i_x.i_xo & 0x20);
 357
 358                         /* calculate EA of load/store */
 359                         ra = instr.i_x.i_ra;
 360                         rb = instr.i_x.i_rb;
 361                         DPRINTF(FPE_INSN, ("reg %d has %jx reg %d has %jx\n",
 362                                 ra, (uintmax_t)tf->fixreg[ra], rb,
 363                                 (uintmax_t)tf->fixreg[rb]));
 364                         addr = tf->fixreg[rb];
 365                         if (ra != 0)
 366                                 addr += tf->fixreg[ra];
 367                         rt = instr.i_x.i_rt;
 368                 } else {
 369                         store = instr.i_d.i_opcd & 0x4;
 370                         if (instr.i_d.i_opcd & 0x2)
 371                                 size = sizeof(double);
 372                         else
 373                                 type = FTYPE_SNG;
 374                         update = instr.i_d.i_opcd & 0x1;
 375
 376                         /* calculate EA of load/store */
 377                         ra = instr.i_d.i_ra;
 378                         addr = instr.i_d.i_d;
 379                         DPRINTF(FPE_INSN, ("reg %d has %jx displ %jx\n",
 380                                 ra, (uintmax_t)tf->fixreg[ra],
 381                                 (uintmax_t)addr));
 382                         if (ra != 0)
 383                                 addr += tf->fixreg[ra];
 384                         rt = instr.i_d.i_rt;
 385                 }
 386
 387                 if (update && ra == 0)
 388                         return (NOTFPU);
 389
 390                 if (store) {
 391                         /* Store */
 392                         FPU_EMU_EVCNT_INCR(fpstore);
 393                         if (type != FTYPE_DBL) {
 394                                 DPRINTF(FPE_INSN,
 395                                         ("fpu_execute: Store SNG at %p\n",
 396                                                 (void *)addr));
 397                                 fpu_explode(fe, fp = &fe->fe_f1, FTYPE_DBL, rt);
 398                                 fpu_implode(fe, fp, type, (void *)&buf);
 399                                 if (copyout(&buf, (void *)addr, size))
 400                                         return (FAULT);
 401                         } else {
 402                                 DPRINTF(FPE_INSN,
 403                                         ("fpu_execute: Store DBL at %p\n",
 404                                                 (void *)addr));
 405                                 if (copyout(&fs->fpr[rt].fpr, (void *)addr,
 406                                     size))
 407                                         return (FAULT);
 408                         }
 409                 } else {
 410                         /* Load */
 411                         FPU_EMU_EVCNT_INCR(fpload);
 412                         DPRINTF(FPE_INSN, ("fpu_execute: Load from %p\n",
 413                                 (void *)addr));
 414                         if (copyin((const void *)addr, &fs->fpr[rt].fpr,
 415                             size))
 416                                 return (FAULT);
 417                         if (type != FTYPE_DBL) {
 418                                 fpu_explode(fe, fp = &fe->fe_f1, type, rt);
 419                                 fpu_implode(fe, fp, FTYPE_DBL,
 420                                         (u_int *)&fs->fpr[rt].fpr);
 421                         }
 422                 }
 423                 if (update)
 424                         tf->fixreg[ra] = addr;
 425                 /* Complete. */
 426                 return (0);
 427 #ifdef notyet
 428         } else if (instr.i_any.i_opcd == OPC_load_st_62) {
 429                 /* These are 64-bit extensions */
 430                 return (NOTFPU);
 431 #endif
 432         } else if (instr.i_any.i_opcd == OPC_sp_fp_59 ||
 433                 instr.i_any.i_opcd == OPC_dp_fp_63) {
 434
 435
 436                 if (instr.i_any.i_opcd == OPC_dp_fp_63 &&
 437                     !(instr.i_a.i_xo & OPC63M_MASK)) {
 438                         /* Format X */
 439                         rt = instr.i_x.i_rt;
 440                         ra = instr.i_x.i_ra;
 441                         rb = instr.i_x.i_rb;
 442
 443
 444                         /* One of the special opcodes.... */
 445                         switch (instr.i_x.i_xo) {
 446                         case    OPC63_FCMPU:
 447                                 FPU_EMU_EVCNT_INCR(fcmpu);
 448                                 DPRINTF(FPE_INSN, ("fpu_execute: FCMPU\n"));
 449                                 rt >>= 2;
 450                                 fpu_explode(fe, &fe->fe_f1, type, ra);
 451                                 fpu_explode(fe, &fe->fe_f2, type, rb);
 452                                 fpu_compare(fe, 0);
 453                                 /* Make sure we do the condition regs. */
 454                                 cond = 0;
 455                                 /* N.B.: i_rs is already left shifted by two. */
 456                                 bf = instr.i_x.i_rs & 0xfc;
 457                                 setcr = 1;
 458                                 break;
 459
 460                         case    OPC63_FRSP:
 461                                 /*
 462                                  * Convert to single:
 463                                  *
 464                                  * PowerPC uses this to round a double
 465                                  * precision value to single precision,
 466                                  * but values in registers are always
 467                                  * stored in double precision format.
 468                                  */
 469                                 FPU_EMU_EVCNT_INCR(frsp);
 470                                 DPRINTF(FPE_INSN, ("fpu_execute: FRSP\n"));
 471                                 fpu_explode(fe, fp = &fe->fe_f1, FTYPE_DBL, rb);
 472                                 fpu_implode(fe, fp, FTYPE_SNG,
 473                                         (u_int *)&fs->fpr[rt].fpr);
 474                                 fpu_explode(fe, fp = &fe->fe_f1, FTYPE_SNG, rt);
 475                                 type = FTYPE_DBL;
 476                                 break;
 477                         case    OPC63_FCTIW:
 478                         case    OPC63_FCTIWZ:
 479                                 FPU_EMU_EVCNT_INCR(fctiw);
 480                                 DPRINTF(FPE_INSN, ("fpu_execute: FCTIW\n"));
 481                                 fpu_explode(fe, fp = &fe->fe_f1, type, rb);
 482                                 type = FTYPE_INT;
 483                                 break;
 484                         case    OPC63_FCMPO:
 485                                 FPU_EMU_EVCNT_INCR(fcmpo);
 486                                 DPRINTF(FPE_INSN, ("fpu_execute: FCMPO\n"));
 487                                 rt >>= 2;
 488                                 fpu_explode(fe, &fe->fe_f1, type, ra);
 489                                 fpu_explode(fe, &fe->fe_f2, type, rb);
 490                                 fpu_compare(fe, 1);
 491                                 /* Make sure we do the condition regs. */
 492                                 cond = 0;
 493                                 /* N.B.: i_rs is already left shifted by two. */
 494                                 bf = instr.i_x.i_rs & 0xfc;
 495                                 setcr = 1;
 496                                 break;
 497                         case    OPC63_MTFSB1:
 498                                 FPU_EMU_EVCNT_INCR(mtfsb1);
 499                                 DPRINTF(FPE_INSN, ("fpu_execute: MTFSB1\n"));
 500                                 fe->fe_fpscr |=
 501                                         (~(FPSCR_VX|FPSR_EX) & (1<<(31-rt)));
 502                                 break;
 503                         case    OPC63_FNEG:
 504                                 FPU_EMU_EVCNT_INCR(fnegabs);
 505                                 DPRINTF(FPE_INSN, ("fpu_execute: FNEGABS\n"));
 506                                 memcpy(&fs->fpr[rt].fpr, &fs->fpr[rb].fpr,
 507                                         sizeof(double));
 508                                 a = (int *)&fs->fpr[rt].fpr;
 509                                 *a ^= (1U << 31);
 510                                 break;
 511                         case    OPC63_MCRFS:
 512                                 FPU_EMU_EVCNT_INCR(mcrfs);
 513                                 DPRINTF(FPE_INSN, ("fpu_execute: MCRFS\n"));
 514                                 cond = 0;
 515                                 rt &= 0x1c;
 516                                 ra &= 0x1c;
 517                                 /* Extract the bits we want */
 518                                 mask = (fe->fe_fpscr >> (28 - ra)) & 0xf;
 519                                 /* Clear the bits we copied. */
 520                                 fe->fe_cx =
 521                                         (FPSR_EX_MSK | (0xf << (28 - ra)));
 522                                 fe->fe_fpscr &= fe->fe_cx;
 523                                 /* Now shove them in the right part of cr */
 524                                 tf->cr &= ~(0xf << (28 - rt));
 525                                 tf->cr |= (mask << (28 - rt));
 526                                 break;
 527                         case    OPC63_MTFSB0:
 528                                 FPU_EMU_EVCNT_INCR(mtfsb0);
 529                                 DPRINTF(FPE_INSN, ("fpu_execute: MTFSB0\n"));
 530                                 fe->fe_fpscr &=
 531                                         ((FPSCR_VX|FPSR_EX) & ~(1<<(31-rt)));
 532                                 break;
 533                         case    OPC63_FMR:
 534                                 FPU_EMU_EVCNT_INCR(fmr);
 535                                 DPRINTF(FPE_INSN, ("fpu_execute: FMR\n"));
 536                                 memcpy(&fs->fpr[rt].fpr, &fs->fpr[rb].fpr,
 537                                         sizeof(double));
 538                                 break;
 539                         case    OPC63_MTFSFI:
 540                                 FPU_EMU_EVCNT_INCR(mtfsfi);
 541                                 DPRINTF(FPE_INSN, ("fpu_execute: MTFSFI\n"));
 542                                 rb >>= 1;
 543                                 rt &= 0x1c; /* Already left-shifted 4 */
 544                                 fe->fe_cx = rb << (28 - rt);
 545                                 mask = 0xf<<(28 - rt);
 546                                 fe->fe_fpscr = (fe->fe_fpscr & ~mask) |
 547                                         fe->fe_cx;
 548 /* XXX weird stuff about OX, FX, FEX, and VX should be handled */
 549                                 break;
 550                         case    OPC63_FNABS:
 551                                 FPU_EMU_EVCNT_INCR(fnabs);
 552                                 DPRINTF(FPE_INSN, ("fpu_execute: FABS\n"));
 553                                 memcpy(&fs->fpr[rt].fpr, &fs->fpr[rb].fpr,
 554                                         sizeof(double));
 555                                 a = (int *)&fs->fpr[rt].fpr;
 556                                 *a |= (1U << 31);
 557                                 break;
 558                         case    OPC63_FABS:
 559                                 FPU_EMU_EVCNT_INCR(fabs);
 560                                 DPRINTF(FPE_INSN, ("fpu_execute: FABS\n"));
 561                                 memcpy(&fs->fpr[rt].fpr, &fs->fpr[rb].fpr,
 562                                         sizeof(double));
 563                                 a = (int *)&fs->fpr[rt].fpr;
 564                                 *a &= ~(1U << 31);
 565                                 break;
 566                         case    OPC63_MFFS:
 567                                 FPU_EMU_EVCNT_INCR(mffs);
 568                                 DPRINTF(FPE_INSN, ("fpu_execute: MFFS\n"));
 569                                 memcpy(&fs->fpr[rt].fpr, &fs->fpscr,
 570                                         sizeof(fs->fpscr));
 571                                 break;
 572                         case    OPC63_MTFSF:
 573                                 FPU_EMU_EVCNT_INCR(mtfsf);
 574                                 DPRINTF(FPE_INSN, ("fpu_execute: MTFSF\n"));
 575                                 if ((rt = instr.i_xfl.i_flm) == -1)
 576                                         mask = -1;
 577                                 else {
 578                                         mask = 0;
 579                                         /* Convert 1 bit -> 4 bits */
 580                                         for (ra = 0; ra < 8; ra ++)
 581                                                 if (rt & (1<<ra))
 582                                                         mask |= (0xf<<(4*ra));
 583                                 }
 584                                 a = (int *)&fs->fpr[rt].fpr;
 585                                 fe->fe_cx = mask & a[1];
 586                                 fe->fe_fpscr = (fe->fe_fpscr&~mask) |
 587                                         (fe->fe_cx);
 588 /* XXX weird stuff about OX, FX, FEX, and VX should be handled */
 589                                 break;
 590                         case    OPC63_FCTID:
 591                         case    OPC63_FCTIDZ:
 592                                 FPU_EMU_EVCNT_INCR(fctid);
 593                                 DPRINTF(FPE_INSN, ("fpu_execute: FCTID\n"));
 594                                 fpu_explode(fe, fp = &fe->fe_f1, type, rb);
 595                                 type = FTYPE_LNG;
 596                                 break;
 597                         case    OPC63_FCFID:
 598                                 FPU_EMU_EVCNT_INCR(fcfid);
 599                                 DPRINTF(FPE_INSN, ("fpu_execute: FCFID\n"));
 600                                 type = FTYPE_LNG;
 601                                 fpu_explode(fe, fp = &fe->fe_f1, type, rb);
 602                                 type = FTYPE_DBL;
 603                                 break;
 604                         default:
 605                                 return (NOTFPU);
 606                                 break;
 607                         }
 608                 } else {
 609                         /* Format A */
 610                         rt = instr.i_a.i_frt;
 611                         ra = instr.i_a.i_fra;
 612                         rb = instr.i_a.i_frb;
 613                         rc = instr.i_a.i_frc;
 614
 615                         /*
 616                          * All arithmetic operations work on registers, which
 617                          * are stored as doubles.
 618                          */
 619                         type = FTYPE_DBL;
 620                         switch ((unsigned int)instr.i_a.i_xo) {
 621                         case    OPC59_FDIVS:
 622                                 FPU_EMU_EVCNT_INCR(fdiv);
 623                                 DPRINTF(FPE_INSN, ("fpu_execute: FDIV\n"));
 624                                 fpu_explode(fe, &fe->fe_f1, type, ra);
 625                                 fpu_explode(fe, &fe->fe_f2, type, rb);
 626                                 fp = fpu_div(fe);
 627                                 break;
 628                         case    OPC59_FSUBS:
 629                                 FPU_EMU_EVCNT_INCR(fsub);
 630                                 DPRINTF(FPE_INSN, ("fpu_execute: FSUB\n"));
 631                                 fpu_explode(fe, &fe->fe_f1, type, ra);
 632                                 fpu_explode(fe, &fe->fe_f2, type, rb);
 633                                 fp = fpu_sub(fe);
 634                                 break;
 635                         case    OPC59_FADDS:
 636                                 FPU_EMU_EVCNT_INCR(fadd);
 637                                 DPRINTF(FPE_INSN, ("fpu_execute: FADD\n"));
 638                                 fpu_explode(fe, &fe->fe_f1, type, ra);
 639                                 fpu_explode(fe, &fe->fe_f2, type, rb);
 640                                 fp = fpu_add(fe);
 641                                 break;
 642                         case    OPC59_FSQRTS:
 643                                 FPU_EMU_EVCNT_INCR(fsqrt);
 644                                 DPRINTF(FPE_INSN, ("fpu_execute: FSQRT\n"));
 645                                 fpu_explode(fe, &fe->fe_f1, type, rb);
 646                                 fp = fpu_sqrt(fe);
 647                                 break;
 648                         case    OPC63M_FSEL:
 649                                 FPU_EMU_EVCNT_INCR(fsel);
 650                                 DPRINTF(FPE_INSN, ("fpu_execute: FSEL\n"));
 651                                 a = (int *)&fe->fe_fpstate->fpr[ra].fpr;
 652                                 if ((*a & 0x80000000) && (*a & 0x7fffffff))
 653                                         /* fra < 0 */
 654                                         rc = rb;
 655                                 DPRINTF(FPE_INSN, ("f%d => f%d\n", rc, rt));
 656                                 memcpy(&fs->fpr[rt].fpr, &fs->fpr[rc].fpr,
 657                                         sizeof(double));
 658                                 break;
 659                         case    OPC59_FRES:
 660                                 FPU_EMU_EVCNT_INCR(fpres);
 661                                 DPRINTF(FPE_INSN, ("fpu_execute: FPRES\n"));
 662                                 fpu_explode(fe, &fe->fe_f1, type, rb);
 663                                 fp = fpu_sqrt(fe);
 664                                 /* now we've gotta overwrite the dest reg */
 665                                 *((int *)&fe->fe_fpstate->fpr[rt].fpr) = 1;
 666                                 fpu_explode(fe, &fe->fe_f1, FTYPE_INT, rt);
 667                                 fpu_div(fe);
 668                                 break;
 669                         case    OPC59_FMULS:
 670                                 FPU_EMU_EVCNT_INCR(fmul);
 671                                 DPRINTF(FPE_INSN, ("fpu_execute: FMUL\n"));
 672                                 fpu_explode(fe, &fe->fe_f1, type, ra);
 673                                 fpu_explode(fe, &fe->fe_f2, type, rc);
 674                                 fp = fpu_mul(fe);
 675                                 break;
 676                         case    OPC63M_FRSQRTE:
 677                                 /* Reciprocal sqrt() estimate */
 678                                 FPU_EMU_EVCNT_INCR(frsqrte);
 679                                 DPRINTF(FPE_INSN, ("fpu_execute: FRSQRTE\n"));
 680                                 fpu_explode(fe, &fe->fe_f1, type, rb);
 681                                 fp = fpu_sqrt(fe);
 682                                 fe->fe_f2 = *fp;
 683                                 /* now we've gotta overwrite the dest reg */
 684                                 *((int *)&fe->fe_fpstate->fpr[rt].fpr) = 1;
 685                                 fpu_explode(fe, &fe->fe_f1, FTYPE_INT, rt);
 686                                 fpu_div(fe);
 687                                 break;
 688                         case    OPC59_FMSUBS:
 689                                 FPU_EMU_EVCNT_INCR(fmulsub);
 690                                 DPRINTF(FPE_INSN, ("fpu_execute: FMULSUB\n"));
 691                                 fpu_explode(fe, &fe->fe_f1, type, ra);
 692                                 fpu_explode(fe, &fe->fe_f2, type, rc);
 693                                 fp = fpu_mul(fe);
 694                                 fe->fe_f1 = *fp;
 695                                 fpu_explode(fe, &fe->fe_f2, type, rb);
 696                                 fp = fpu_sub(fe);
 697                                 break;
 698                         case    OPC59_FMADDS:
 699                                 FPU_EMU_EVCNT_INCR(fmuladd);
 700                                 DPRINTF(FPE_INSN, ("fpu_execute: FMULADD\n"));
 701                                 fpu_explode(fe, &fe->fe_f1, type, ra);
 702                                 fpu_explode(fe, &fe->fe_f2, type, rc);
 703                                 fp = fpu_mul(fe);
 704                                 fe->fe_f1 = *fp;
 705                                 fpu_explode(fe, &fe->fe_f2, type, rb);
 706                                 fp = fpu_add(fe);
 707                                 break;
 708                         case    OPC59_FNMSUBS:
 709                                 FPU_EMU_EVCNT_INCR(fnmsub);
 710                                 DPRINTF(FPE_INSN, ("fpu_execute: FNMSUB\n"));
 711                                 fpu_explode(fe, &fe->fe_f1, type, ra);
 712                                 fpu_explode(fe, &fe->fe_f2, type, rc);
 713                                 fp = fpu_mul(fe);
 714                                 fe->fe_f1 = *fp;
 715                                 fpu_explode(fe, &fe->fe_f2, type, rb);
 716                                 fp = fpu_sub(fe);
 717                                 /* Negate */
 718                                 fp->fp_sign ^= 1;
 719                                 break;
 720                         case    OPC59_FNMADDS:
 721                                 FPU_EMU_EVCNT_INCR(fnmadd);
 722                                 DPRINTF(FPE_INSN, ("fpu_execute: FNMADD\n"));
 723                                 fpu_explode(fe, &fe->fe_f1, type, ra);
 724                                 fpu_explode(fe, &fe->fe_f2, type, rc);
 725                                 fp = fpu_mul(fe);
 726                                 fe->fe_f1 = *fp;
 727                                 fpu_explode(fe, &fe->fe_f2, type, rb);
 728                                 fp = fpu_add(fe);
 729                                 /* Negate */
 730                                 fp->fp_sign ^= 1;
 731                                 break;
 732                         default:
 733                                 return (NOTFPU);
 734                                 break;
 735                         }
 736
 737                         /* If the instruction was single precision, round */
 738                         if (!(instr.i_any.i_opcd & 0x4)) {
 739                                 fpu_implode(fe, fp, FTYPE_SNG,
 740                                         (u_int *)&fs->fpr[rt].fpr);
 741                                 fpu_explode(fe, fp = &fe->fe_f1, FTYPE_SNG, rt);
 742                         }
 743                 }
 744         } else {
 745                 return (NOTFPU);
 746         }
 747
 748         /*
 749          * ALU operation is complete.  Collapse the result and then check
 750          * for exceptions.  If we got any, and they are enabled, do not
 751          * alter the destination register, just stop with an exception.
 752          * Otherwise set new current exceptions and accrue.
 753          */
 754         if (fp)
 755                 fpu_implode(fe, fp, type, (u_int *)&fs->fpr[rt].fpr);
 756         cx = fe->fe_cx;
 757         fsr = fe->fe_fpscr;
 758         if (cx != 0) {
 759                 fsr &= ~FPSCR_FX;
 760                 if ((cx^fsr)&FPSR_EX_MSK)
 761                         fsr |= FPSCR_FX;
 762                 mask = fsr & FPSR_EX;
 763                 mask <<= (25-3);
 764                 if (cx & mask)
 765                         fsr |= FPSCR_FEX;
 766                 if (cx & FPSCR_FPRF) {
 767                         /* Need to replace CC */
 768                         fsr &= ~FPSCR_FPRF;
 769                 }
 770                 if (cx & (FPSR_EXOP))
 771                         fsr |= FPSCR_VX;
 772                 fsr |= cx;
 773                 DPRINTF(FPE_INSN, ("fpu_execute: cx %x, fsr %x\n", cx, fsr));
 774         }
 775
 776         if (cond) {
 777                 cond = fsr & 0xf0000000;
 778                 /* Isolate condition codes */
 779                 cond >>= 28;
 780                 /* Move fpu condition codes to cr[1] */
 781                 tf->cr &= (0x0f000000);
 782                 tf->cr |= (cond<<24);
 783                 DPRINTF(FPE_INSN, ("fpu_execute: cr[1] <= %x\n", cond));
 784         }
 785
 786         if (setcr) {
 787                 cond = fsr & FPSCR_FPCC;
 788                 /* Isolate condition codes */
 789                 cond <<= 16;
 790                 /* Move fpu condition codes to cr[1] */
 791                 tf->cr &= ~(0xf0000000>>bf);
 792                 tf->cr |= (cond>>bf);
 793                 DPRINTF(FPE_INSN, ("fpu_execute: cr[%d] (cr=%jx) <= %x\n",
 794                         bf/4, (uintmax_t)tf->cr, cond));
 795         }
 796
 797         ((int *)&fs->fpscr)[1] = fsr;
 798         if (fsr & FPSCR_FEX)
 799                 return(FPE);
 800         return (0);     /* success */
 801 }