1 /* $NetBSD: fpu_emu.h,v 1.3 2005/12/11 12:18:42 christos Exp $ */
5 * Copyright (c) 1992, 1993
6 * The Regents of the University of California. All rights reserved.
8 * This software was developed by the Computer Systems Engineering group
9 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
10 * contributed to Berkeley.
12 * All advertising materials mentioning features or use of this software
13 * must display the following acknowledgement:
14 * This product includes software developed by the University of
15 * California, Lawrence Berkeley Laboratory.
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions
20 * 1. Redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer.
22 * 2. Redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution.
25 * 3. Neither the name of the University nor the names of its contributors
26 * may be used to endorse or promote products derived from this software
27 * without specific prior written permission.
29 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
30 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
31 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
32 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
33 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
34 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
35 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
36 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
37 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
38 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
41 * @(#)fpu_emu.h 8.1 (Berkeley) 6/11/93
45 * Floating point emulator (tailored for SPARC, but structurally
46 * machine-independent).
48 * Floating point numbers are carried around internally in an `expanded'
49 * or `unpacked' form consisting of:
52 * - mantissa (`1.' + 112-bit fraction + guard + round)
54 * Any implied `1' bit is inserted, giving a 113-bit mantissa that is
55 * always nonzero. Additional low-order `guard' and `round' bits are
56 * scrunched in, making the entire mantissa 115 bits long. This is divided
57 * into four 32-bit words, with `spare' bits left over in the upper part
58 * of the top word (the high bits of fp_mant[0]). An internal `exploded'
59 * number is thus kept within the half-open interval [1.0,2.0) (but see
60 * the `number classes' below). This holds even for denormalized numbers:
61 * when we explode an external denorm, we normalize it, introducing low-order
62 * zero bits, so that the rest of the code always sees normalized values.
64 * Note that a number of our algorithms use the `spare' bits at the top.
65 * The most demanding algorithm---the one for sqrt---depends on two such
66 * bits, so that it can represent values up to (but not including) 8.0,
67 * and then it needs a carry on top of that, so that we need three `spares'.
69 * The sticky-word is 32 bits so that we can use `OR' operators to goosh
70 * whole words from the mantissa into it.
72 * All operations are done in this internal extended precision. According
73 * to Hennesey & Patterson, Appendix A, rounding can be repeated---that is,
74 * it is OK to do a+b in extended precision and then round the result to
75 * single precision---provided single, double, and extended precisions are
76 * `far enough apart' (they always are), but we will try to avoid any such
77 * extra work where possible.
80 int fp_class; /* see below */
81 int fp_sign; /* 0 => positive, 1 => negative */
82 int fp_exp; /* exponent (unbiased) */
83 int fp_sticky; /* nonzero bits lost at right end */
84 u_int fp_mant[4]; /* 115-bit mantissa */
87 #define FP_NMANT 115 /* total bits in mantissa (incl g,r) */
88 #define FP_NG 2 /* number of low-order guard bits */
89 #define FP_LG ((FP_NMANT - 1) & 31) /* log2(1.0) for fp_mant[0] */
90 #define FP_LG2 ((FP_NMANT - 1) & 63) /* log2(1.0) for fp_mant[0] and fp_mant[1] */
91 #define FP_QUIETBIT (1 << (FP_LG - 1)) /* Quiet bit in NaNs (0.5) */
92 #define FP_1 (1 << FP_LG) /* 1.0 in fp_mant[0] */
93 #define FP_2 (1 << (FP_LG + 1)) /* 2.0 in fp_mant[0] */
96 * Number classes. Since zero, Inf, and NaN cannot be represented using
97 * the above layout, we distinguish these from other numbers via a class.
98 * In addition, to make computation easier and to follow Appendix N of
99 * the SPARC Version 8 standard, we give each kind of NaN a separate class.
101 #define FPC_SNAN -2 /* signalling NaN (sign irrelevant) */
102 #define FPC_QNAN -1 /* quiet NaN (sign irrelevant) */
103 #define FPC_ZERO 0 /* zero (sign matters) */
104 #define FPC_NUM 1 /* number (sign matters) */
105 #define FPC_INF 2 /* infinity (sign matters) */
107 #define ISSNAN(fp) ((fp)->fp_class == FPC_SNAN)
108 #define ISQNAN(fp) ((fp)->fp_class == FPC_QNAN)
109 #define ISNAN(fp) ((fp)->fp_class < 0)
110 #define ISZERO(fp) ((fp)->fp_class == 0)
111 #define ISINF(fp) ((fp)->fp_class == FPC_INF)
114 * ORDER(x,y) `sorts' a pair of `fpn *'s so that the right operand (y) points
115 * to the `more significant' operand for our purposes. Appendix N says that
116 * the result of a computation involving two numbers are:
118 * If both are SNaN: operand 2, converted to Quiet
119 * If only one is SNaN: the SNaN operand, converted to Quiet
120 * If both are QNaN: operand 2
121 * If only one is QNaN: the QNaN operand
123 * In addition, in operations with an Inf operand, the result is usually
124 * Inf. The class numbers are carefully arranged so that if
125 * (unsigned)class(op1) > (unsigned)class(op2)
126 * then op1 is the one we want; otherwise op2 is the one we want.
128 #define ORDER(x, y) { \
129 if ((u_int)(x)->fp_class > (u_int)(y)->fp_class) \
132 #define SWAP(x, y) { \
134 swap = (x), (x) = (y), (y) = swap; \
141 struct fpreg *fe_fpstate; /* registers, etc */
142 int fe_fpscr; /* fpscr copy (modified during op) */
143 int fe_cx; /* keep track of exceptions */
144 struct fpn fe_f1; /* operand 1 */
145 struct fpn fe_f2; /* operand 2, if required */
146 struct fpn fe_f3; /* available storage for result */
150 * Arithmetic functions.
151 * Each of these may modify its inputs (f1,f2) and/or the temporary.
152 * Each returns a pointer to the result and/or sets exceptions.
154 struct fpn *fpu_add(struct fpemu *);
155 #define fpu_sub(fe) ((fe)->fe_f2.fp_sign ^= 1, fpu_add(fe))
156 struct fpn *fpu_mul(struct fpemu *);
157 struct fpn *fpu_div(struct fpemu *);
158 struct fpn *fpu_sqrt(struct fpemu *);
164 /* Perform a compare instruction (with or without unordered exception). */
165 void fpu_compare(struct fpemu *, int);
167 /* Build a new Quiet NaN (sign=0, frac=all 1's). */
168 struct fpn *fpu_newnan(struct fpemu *);
170 void fpu_norm(struct fpn *);
173 * Shift a number right some number of bits, taking care of round/sticky.
174 * Note that the result is probably not a well-formed number (it will lack
175 * the normal 1-bit mant[0]&FP_1).
177 int fpu_shr(struct fpn *, int);
179 void fpu_explode(struct fpemu *, struct fpn *, int, int);
180 void fpu_implode(struct fpemu *, struct fpn *, int, u_int *);
187 extern int fpe_debug;
188 void fpu_dumpfpn(struct fpn *);
189 #define DPRINTF(x, y) if (fpe_debug & (x)) printf y
190 #define DUMPFPN(x, f) if (fpe_debug & (x)) fpu_dumpfpn((f))
192 #define DPRINTF(x, y)
193 #define DUMPFPN(x, f)