1 /* $NetBSD: fpu_emu.h,v 1.3 2005/12/11 12:18:42 christos Exp $ */
5 * SPDX-License-Identifier: BSD-3-Clause
7 * Copyright (c) 1992, 1993
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10 * This software was developed by the Computer Systems Engineering group
11 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
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43 * @(#)fpu_emu.h 8.1 (Berkeley) 6/11/93
47 * Floating point emulator (tailored for SPARC, but structurally
48 * machine-independent).
50 * Floating point numbers are carried around internally in an `expanded'
51 * or `unpacked' form consisting of:
54 * - mantissa (`1.' + 112-bit fraction + guard + round)
56 * Any implied `1' bit is inserted, giving a 113-bit mantissa that is
57 * always nonzero. Additional low-order `guard' and `round' bits are
58 * scrunched in, making the entire mantissa 115 bits long. This is divided
59 * into four 32-bit words, with `spare' bits left over in the upper part
60 * of the top word (the high bits of fp_mant[0]). An internal `exploded'
61 * number is thus kept within the half-open interval [1.0,2.0) (but see
62 * the `number classes' below). This holds even for denormalized numbers:
63 * when we explode an external denorm, we normalize it, introducing low-order
64 * zero bits, so that the rest of the code always sees normalized values.
66 * Note that a number of our algorithms use the `spare' bits at the top.
67 * The most demanding algorithm---the one for sqrt---depends on two such
68 * bits, so that it can represent values up to (but not including) 8.0,
69 * and then it needs a carry on top of that, so that we need three `spares'.
71 * The sticky-word is 32 bits so that we can use `OR' operators to goosh
72 * whole words from the mantissa into it.
74 * All operations are done in this internal extended precision. According
75 * to Hennesey & Patterson, Appendix A, rounding can be repeated---that is,
76 * it is OK to do a+b in extended precision and then round the result to
77 * single precision---provided single, double, and extended precisions are
78 * `far enough apart' (they always are), but we will try to avoid any such
79 * extra work where possible.
82 int fp_class; /* see below */
83 int fp_sign; /* 0 => positive, 1 => negative */
84 int fp_exp; /* exponent (unbiased) */
85 int fp_sticky; /* nonzero bits lost at right end */
86 u_int fp_mant[4]; /* 115-bit mantissa */
89 #define FP_NMANT 115 /* total bits in mantissa (incl g,r) */
90 #define FP_NG 2 /* number of low-order guard bits */
91 #define FP_LG ((FP_NMANT - 1) & 31) /* log2(1.0) for fp_mant[0] */
92 #define FP_LG2 ((FP_NMANT - 1) & 63) /* log2(1.0) for fp_mant[0] and fp_mant[1] */
93 #define FP_QUIETBIT (1 << (FP_LG - 1)) /* Quiet bit in NaNs (0.5) */
94 #define FP_1 (1 << FP_LG) /* 1.0 in fp_mant[0] */
95 #define FP_2 (1 << (FP_LG + 1)) /* 2.0 in fp_mant[0] */
98 * Number classes. Since zero, Inf, and NaN cannot be represented using
99 * the above layout, we distinguish these from other numbers via a class.
100 * In addition, to make computation easier and to follow Appendix N of
101 * the SPARC Version 8 standard, we give each kind of NaN a separate class.
103 #define FPC_SNAN -2 /* signalling NaN (sign irrelevant) */
104 #define FPC_QNAN -1 /* quiet NaN (sign irrelevant) */
105 #define FPC_ZERO 0 /* zero (sign matters) */
106 #define FPC_NUM 1 /* number (sign matters) */
107 #define FPC_INF 2 /* infinity (sign matters) */
109 #define ISSNAN(fp) ((fp)->fp_class == FPC_SNAN)
110 #define ISQNAN(fp) ((fp)->fp_class == FPC_QNAN)
111 #define ISNAN(fp) ((fp)->fp_class < 0)
112 #define ISZERO(fp) ((fp)->fp_class == 0)
113 #define ISINF(fp) ((fp)->fp_class == FPC_INF)
116 * ORDER(x,y) `sorts' a pair of `fpn *'s so that the right operand (y) points
117 * to the `more significant' operand for our purposes. Appendix N says that
118 * the result of a computation involving two numbers are:
120 * If both are SNaN: operand 2, converted to Quiet
121 * If only one is SNaN: the SNaN operand, converted to Quiet
122 * If both are QNaN: operand 2
123 * If only one is QNaN: the QNaN operand
125 * In addition, in operations with an Inf operand, the result is usually
126 * Inf. The class numbers are carefully arranged so that if
127 * (unsigned)class(op1) > (unsigned)class(op2)
128 * then op1 is the one we want; otherwise op2 is the one we want.
130 #define ORDER(x, y) { \
131 if ((u_int)(x)->fp_class > (u_int)(y)->fp_class) \
134 #define SWAP(x, y) { \
136 swap = (x), (x) = (y), (y) = swap; \
143 struct fpu *fe_fpstate; /* registers, etc */
144 int fe_fpscr; /* fpscr copy (modified during op) */
145 int fe_cx; /* keep track of exceptions */
146 struct fpn fe_f1; /* operand 1 */
147 struct fpn fe_f2; /* operand 2, if required */
148 struct fpn fe_f3; /* available storage for result */
152 * Arithmetic functions.
153 * Each of these may modify its inputs (f1,f2) and/or the temporary.
154 * Each returns a pointer to the result and/or sets exceptions.
156 struct fpn *fpu_add(struct fpemu *);
157 #define fpu_sub(fe) ((fe)->fe_f2.fp_sign ^= 1, fpu_add(fe))
158 struct fpn *fpu_mul(struct fpemu *);
159 struct fpn *fpu_div(struct fpemu *);
160 struct fpn *fpu_sqrt(struct fpemu *);
166 /* Perform a compare instruction (with or without unordered exception). */
167 void fpu_compare(struct fpemu *, int);
169 /* Build a new Quiet NaN (sign=0, frac=all 1's). */
170 struct fpn *fpu_newnan(struct fpemu *);
172 void fpu_norm(struct fpn *);
175 * Shift a number right some number of bits, taking care of round/sticky.
176 * Note that the result is probably not a well-formed number (it will lack
177 * the normal 1-bit mant[0]&FP_1).
179 int fpu_shr(struct fpn *, int);
181 void fpu_explode(struct fpemu *, struct fpn *, int, int);
182 void fpu_implode(struct fpemu *, struct fpn *, int, u_int *);
189 extern int fpe_debug;
190 void fpu_dumpfpn(struct fpn *);
191 #define DPRINTF(x, y) if (fpe_debug & (x)) printf y
192 #define DUMPFPN(x, f) if (fpe_debug & (x)) fpu_dumpfpn((f))
194 #define DPRINTF(x, y)
195 #define DUMPFPN(x, f)