1 /* $NetBSD: fpu_explode.c,v 1.6 2005/12/11 12:18:42 christos Exp $ */
4 * SPDX-License-Identifier: BSD-3-Clause
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10 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
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42 * @(#)fpu_explode.c 8.1 (Berkeley) 6/11/93
46 * FPU subroutines: `explode' the machine's `packed binary' format numbers
47 * into our internal format.
50 #include <sys/cdefs.h>
51 __FBSDID("$FreeBSD$");
53 #include <sys/types.h>
54 #include <sys/systm.h>
56 #include <machine/fpu.h>
57 #include <machine/ieee.h>
58 #include <machine/pcb.h>
60 #include <powerpc/fpu/fpu_arith.h>
61 #include <powerpc/fpu/fpu_emu.h>
62 #include <powerpc/fpu/fpu_extern.h>
63 #include <powerpc/fpu/fpu_instr.h>
66 * N.B.: in all of the following, we assume the FP format is
68 * ---------------------------
69 * | s | exponent | fraction |
70 * ---------------------------
72 * (which represents -1**s * 1.fraction * 2**exponent), so that the
73 * sign bit is way at the top (bit 31), the exponent is next, and
74 * then the remaining bits mark the fraction. A zero exponent means
75 * zero or denormalized (0.fraction rather than 1.fraction), and the
76 * maximum possible exponent, 2bias+1, signals inf (fraction==0) or NaN.
78 * Since the sign bit is always the topmost bit---this holds even for
79 * integers---we set that outside all the *tof functions. Each function
80 * returns the class code for the new number (but note that we use
81 * FPC_QNAN for all NaNs; fpu_explode will fix this if appropriate).
88 fpu_itof(struct fpn *fp, u_int i)
94 * The value FP_1 represents 2^FP_LG, so set the exponent
95 * there and let normalization fix it up. Convert negative
96 * numbers to sign-and-magnitude. Note that this relies on
97 * fpu_norm()'s handling of `supernormals'; see fpu_subr.c.
100 fp->fp_mant[0] = (int)i < 0 ? -i : i;
112 fpu_xtof(struct fpn *fp, u_int64_t i)
118 * The value FP_1 represents 2^FP_LG, so set the exponent
119 * there and let normalization fix it up. Convert negative
120 * numbers to sign-and-magnitude. Note that this relies on
121 * fpu_norm()'s handling of `supernormals'; see fpu_subr.c.
124 *((int64_t*)fp->fp_mant) = (int64_t)i < 0 ? -i : i;
131 #define mask(nbits) ((1L << (nbits)) - 1)
134 * All external floating formats convert to internal in the same manner,
135 * as defined here. Note that only normals get an implied 1.0 inserted.
137 #define FP_TOF(exp, expbias, allfrac, f0, f1, f2, f3) \
141 fp->fp_exp = 1 - expbias; \
142 fp->fp_mant[0] = f0; \
143 fp->fp_mant[1] = f1; \
144 fp->fp_mant[2] = f2; \
145 fp->fp_mant[3] = f3; \
149 if (exp == (2 * expbias + 1)) { \
152 fp->fp_mant[0] = f0; \
153 fp->fp_mant[1] = f1; \
154 fp->fp_mant[2] = f2; \
155 fp->fp_mant[3] = f3; \
158 fp->fp_exp = exp - expbias; \
159 fp->fp_mant[0] = FP_1 | f0; \
160 fp->fp_mant[1] = f1; \
161 fp->fp_mant[2] = f2; \
162 fp->fp_mant[3] = f3; \
166 * 32-bit single precision -> fpn.
167 * We assume a single occupies at most (64-FP_LG) bits in the internal
168 * format: i.e., needs at most fp_mant[0] and fp_mant[1].
171 fpu_stof(struct fpn *fp, u_int i)
175 #define SNG_SHIFT (SNG_FRACBITS - FP_LG)
177 exp = (i >> (32 - 1 - SNG_EXPBITS)) & mask(SNG_EXPBITS);
178 frac = i & mask(SNG_FRACBITS);
179 f0 = frac >> SNG_SHIFT;
180 f1 = frac << (32 - SNG_SHIFT);
181 FP_TOF(exp, SNG_EXP_BIAS, frac, f0, f1, 0, 0);
185 * 64-bit double -> fpn.
186 * We assume this uses at most (96-FP_LG) bits.
189 fpu_dtof(struct fpn *fp, u_int i, u_int j)
192 u_int frac, f0, f1, f2;
193 #define DBL_SHIFT (DBL_FRACBITS - 32 - FP_LG)
195 exp = (i >> (32 - 1 - DBL_EXPBITS)) & mask(DBL_EXPBITS);
196 frac = i & mask(DBL_FRACBITS - 32);
197 f0 = frac >> DBL_SHIFT;
198 f1 = (frac << (32 - DBL_SHIFT)) | (j >> DBL_SHIFT);
199 f2 = j << (32 - DBL_SHIFT);
201 FP_TOF(exp, DBL_EXP_BIAS, frac, f0, f1, f2, 0);
205 * Explode the contents of a register / regpair / regquad.
206 * If the input is a signalling NaN, an NV (invalid) exception
207 * will be set. (Note that nothing but NV can occur until ALU
208 * operations are performed.)
211 fpu_explode(struct fpemu *fe, struct fpn *fp, int type, int reg)
214 u_int64_t l, *xspace;
216 xspace = (u_int64_t *)&fe->fe_fpstate->fpr[reg].fpr;
218 space = (u_int *)&fe->fe_fpstate->fpr[reg].fpr;
220 fp->fp_sign = s >> 31;
228 s = fpu_itof(fp, space[1]);
236 s = fpu_dtof(fp, s, space[1]);
240 panic("fpu_explode");
241 panic("fpu_explode: invalid type %d", type);
244 if (s == FPC_QNAN && (fp->fp_mant[0] & FP_QUIETBIT) == 0) {
246 * Input is a signalling NaN. All operations that return
247 * an input NaN operand put it through a ``NaN conversion'',
248 * which basically just means ``turn on the quiet bit''.
249 * We do this here so that all NaNs internally look quiet
250 * (we can tell signalling ones by their class).
252 fp->fp_mant[0] |= FP_QUIETBIT;
253 fe->fe_cx = FPSCR_VXSNAN; /* assert invalid operand */
257 DPRINTF(FPE_REG, ("fpu_explode: %%%c%d => ", (type == FTYPE_LNG) ? 'x' :
258 ((type == FTYPE_INT) ? 'i' :
259 ((type == FTYPE_SNG) ? 's' :
260 ((type == FTYPE_DBL) ? 'd' : '?'))),
262 DUMPFPN(FPE_REG, fp);
263 DPRINTF(FPE_REG, ("\n"));