1 /* $NetBSD: fpu_implode.c,v 1.6 2005/12/11 12:18:42 christos Exp $ */
4 * SPDX-License-Identifier: BSD-3-Clause
6 * Copyright (c) 1992, 1993
7 * The Regents of the University of California. All rights reserved.
9 * This software was developed by the Computer Systems Engineering group
10 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
11 * contributed to Berkeley.
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15 * This product includes software developed by the University of
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44 * FPU subroutines: `implode' internal format numbers into the machine's
45 * `packed binary' format.
48 #include <sys/types.h>
49 #include <sys/systm.h>
51 #include <machine/fpu.h>
52 #include <machine/ieee.h>
53 #include <machine/ieeefp.h>
55 #include <powerpc/fpu/fpu_arith.h>
56 #include <powerpc/fpu/fpu_emu.h>
57 #include <powerpc/fpu/fpu_extern.h>
58 #include <powerpc/fpu/fpu_instr.h>
60 static int round(struct fpemu *, struct fpn *);
61 static int toinf(struct fpemu *, int);
64 * Round a number (algorithm from Motorola MC68882 manual, modified for
65 * our internal format). Set inexact exception if rounding is required.
66 * Return true iff we rounded up.
68 * After rounding, we discard the guard and round bits by shifting right
69 * 2 bits (a la fpu_shr(), but we do not bother with fp->fp_sticky).
70 * This saves effort later.
72 * Note that we may leave the value 2.0 in fp->fp_mant; it is the caller's
73 * responsibility to fix this if necessary.
76 round(struct fpemu *fe, struct fpn *fp)
90 m3 = (m3 >> FP_NG) | (m2 << (32 - FP_NG));
91 m2 = (m2 >> FP_NG) | (m1 << (32 - FP_NG));
92 m1 = (m1 >> FP_NG) | (m0 << (32 - FP_NG));
95 if ((gr | s) == 0) /* result is exact: no rounding needed */
98 fe->fe_cx |= FPSCR_XX|FPSCR_FI; /* inexact */
100 /* Go to rounddown to round down; break to round up. */
101 switch ((fe->fe_fpscr) & FPSCR_RN) {
105 * Round only if guard is set (gr & 2). If guard is set,
106 * but round & sticky both clear, then we want to round
107 * but have a tie, so round to even, i.e., add 1 iff odd.
111 if ((gr & 1) || fp->fp_sticky || (m3 & 1))
116 /* Round towards zero, i.e., down. */
120 /* Round towards -Inf: up if negative, down if positive. */
126 /* Round towards +Inf: up if positive, down otherwise. */
132 /* Bump low bit of mantissa, with carry. */
133 fe->fe_cx |= FPSCR_FR;
136 FPU_ADDCS(m2, m2, 0);
137 FPU_ADDCS(m1, m1, 0);
154 * For overflow: return true if overflow is to go to +/-Inf, according
155 * to the sign of the overflowing result. If false, overflow is to go
156 * to the largest magnitude value instead.
159 toinf(struct fpemu *fe, int sign)
163 /* look at rounding direction */
164 switch ((fe->fe_fpscr) & FPSCR_RN) {
166 case FP_RN: /* the nearest value is always Inf */
170 case FP_RZ: /* toward 0 => never towards Inf */
174 case FP_RP: /* toward +Inf iff positive */
178 case FP_RM: /* toward -Inf iff negative */
183 fe->fe_cx |= FPSCR_OX;
188 * fpn -> int (int value returned as return value).
190 * N.B.: this conversion always rounds towards zero (this is a peculiarity
191 * of the SPARC instruction set).
194 fpu_ftoi(struct fpemu *fe, struct fpn *fp)
200 switch (fp->fp_class) {
206 * If exp >= 2^32, overflow. Otherwise shift value right
207 * into last mantissa word (this will not exceed 0xffffffff),
208 * shifting any guard and round bits out into the sticky
209 * bit. Then ``round'' towards zero, i.e., just set an
210 * inexact exception if sticky is set (see round()).
211 * If the result is > 0x80000000, or is positive and equals
212 * 0x80000000, overflow; otherwise the last fraction word
215 if ((exp = fp->fp_exp) >= 32)
217 /* NB: the following includes exp < 0 cases */
218 if (fpu_shr(fp, FP_NMANT - 1 - exp) != 0)
219 fe->fe_cx |= FPSCR_UX;
221 if (i >= ((u_int)0x80000000 + sign))
223 return (sign ? -i : i);
225 default: /* Inf, qNaN, sNaN */
228 /* overflow: replace any inexact exception with invalid */
229 fe->fe_cx |= FPSCR_VXCVI;
230 return (0x7fffffff + sign);
234 * fpn -> extended int (high bits of int value returned as return value).
236 * N.B.: this conversion always rounds towards zero (this is a peculiarity
237 * of the SPARC instruction set).
240 fpu_ftox(struct fpemu *fe, struct fpn *fp, u_int *res)
246 switch (fp->fp_class) {
253 * If exp >= 2^64, overflow. Otherwise shift value right
254 * into last mantissa word (this will not exceed 0xffffffffffffffff),
255 * shifting any guard and round bits out into the sticky
256 * bit. Then ``round'' towards zero, i.e., just set an
257 * inexact exception if sticky is set (see round()).
258 * If the result is > 0x8000000000000000, or is positive and equals
259 * 0x8000000000000000, overflow; otherwise the last fraction word
262 if ((exp = fp->fp_exp) >= 64)
264 /* NB: the following includes exp < 0 cases */
265 if (fpu_shr(fp, FP_NMANT - 1 - exp) != 0)
266 fe->fe_cx |= FPSCR_UX;
267 i = ((u_int64_t)fp->fp_mant[2]<<32)|fp->fp_mant[3];
268 if (i >= ((u_int64_t)0x8000000000000000LL + sign))
270 return (sign ? -i : i);
272 default: /* Inf, qNaN, sNaN */
275 /* overflow: replace any inexact exception with invalid */
276 fe->fe_cx |= FPSCR_VXCVI;
277 return (0x7fffffffffffffffLL + sign);
281 * fpn -> single (32 bit single returned as return value).
282 * We assume <= 29 bits in a single-precision fraction (1.f part).
285 fpu_ftos(struct fpemu *fe, struct fpn *fp)
287 u_int sign = fp->fp_sign << 31;
290 #define SNG_EXP(e) ((e) << SNG_FRACBITS) /* makes e an exponent */
291 #define SNG_MASK (SNG_EXP(1) - 1) /* mask for fraction */
293 /* Take care of non-numbers first. */
296 * Preserve upper bits of NaN, per SPARC V8 appendix N.
297 * Note that fp->fp_mant[0] has the quiet bit set,
298 * even if it is classified as a signalling NaN.
300 (void) fpu_shr(fp, FP_NMANT - 1 - SNG_FRACBITS);
301 exp = SNG_EXP_INFNAN;
305 return (sign | SNG_EXP(SNG_EXP_INFNAN));
310 * Normals (including subnormals). Drop all the fraction bits
311 * (including the explicit ``implied'' 1 bit) down into the
312 * single-precision range. If the number is subnormal, move
313 * the ``implied'' 1 into the explicit range as well, and shift
314 * right to introduce leading zeroes. Rounding then acts
315 * differently for normals and subnormals: the largest subnormal
316 * may round to the smallest normal (1.0 x 2^minexp), or may
317 * remain subnormal. In the latter case, signal an underflow
318 * if the result was inexact or if underflow traps are enabled.
320 * Rounding a normal, on the other hand, always produces another
321 * normal (although either way the result might be too big for
322 * single precision, and cause an overflow). If rounding a
323 * normal produces 2.0 in the fraction, we need not adjust that
324 * fraction at all, since both 1.0 and 2.0 are zero under the
327 * Note that the guard and round bits vanish from the number after
330 if ((exp = fp->fp_exp + SNG_EXP_BIAS) <= 0) { /* subnormal */
331 /* -NG for g,r; -SNG_FRACBITS-exp for fraction */
332 (void) fpu_shr(fp, FP_NMANT - FP_NG - SNG_FRACBITS - exp);
333 if (round(fe, fp) && fp->fp_mant[3] == SNG_EXP(1))
334 return (sign | SNG_EXP(1) | 0);
335 if ((fe->fe_cx & FPSCR_FI) ||
336 (fe->fe_fpscr & FPSCR_UX))
337 fe->fe_cx |= FPSCR_UX;
338 return (sign | SNG_EXP(0) | fp->fp_mant[3]);
340 /* -FP_NG for g,r; -1 for implied 1; -SNG_FRACBITS for fraction */
341 (void) fpu_shr(fp, FP_NMANT - FP_NG - 1 - SNG_FRACBITS);
343 if ((fp->fp_mant[3] & SNG_EXP(1 << FP_NG)) == 0)
346 if (round(fe, fp) && fp->fp_mant[3] == SNG_EXP(2))
348 if (exp >= SNG_EXP_INFNAN) {
349 /* overflow to inf or to max single */
351 return (sign | SNG_EXP(SNG_EXP_INFNAN));
352 return (sign | SNG_EXP(SNG_EXP_INFNAN - 1) | SNG_MASK);
356 return (sign | SNG_EXP(exp) | (fp->fp_mant[3] & SNG_MASK));
360 * fpn -> double (32 bit high-order result returned; 32-bit low order result
361 * left in res[1]). Assumes <= 61 bits in double precision fraction.
363 * This code mimics fpu_ftos; see it for comments.
366 fpu_ftod(struct fpemu *fe, struct fpn *fp, u_int *res)
368 u_int sign = fp->fp_sign << 31;
371 #define DBL_EXP(e) ((e) << (DBL_FRACBITS & 31))
372 #define DBL_MASK (DBL_EXP(1) - 1)
375 (void) fpu_shr(fp, FP_NMANT - 1 - DBL_FRACBITS);
376 exp = DBL_EXP_INFNAN;
380 sign |= DBL_EXP(DBL_EXP_INFNAN);
388 if ((exp = fp->fp_exp + DBL_EXP_BIAS) <= 0) {
389 (void) fpu_shr(fp, FP_NMANT - FP_NG - DBL_FRACBITS - exp);
390 if (round(fe, fp) && fp->fp_mant[2] == DBL_EXP(1)) {
392 return (sign | DBL_EXP(1) | 0);
394 if ((fe->fe_cx & FPSCR_FI) ||
395 (fe->fe_fpscr & FPSCR_UX))
396 fe->fe_cx |= FPSCR_UX;
400 (void) fpu_shr(fp, FP_NMANT - FP_NG - 1 - DBL_FRACBITS);
401 if (round(fe, fp) && fp->fp_mant[2] == DBL_EXP(2))
403 if (exp >= DBL_EXP_INFNAN) {
404 fe->fe_cx |= FPSCR_OX | FPSCR_UX;
405 if (toinf(fe, sign)) {
407 return (sign | DBL_EXP(DBL_EXP_INFNAN) | 0);
410 return (sign | DBL_EXP(DBL_EXP_INFNAN) | DBL_MASK);
413 res[1] = fp->fp_mant[3];
414 return (sign | DBL_EXP(exp) | (fp->fp_mant[2] & DBL_MASK));
418 * Implode an fpn, writing the result into the given space.
421 fpu_implode(struct fpemu *fe, struct fpn *fp, int type, u_int *space)
426 space[0] = fpu_ftox(fe, fp, space);
427 DPRINTF(FPE_REG, ("fpu_implode: long %x %x\n",
428 space[0], space[1]));
433 space[1] = fpu_ftoi(fe, fp);
434 DPRINTF(FPE_REG, ("fpu_implode: int %x\n",
439 space[0] = fpu_ftos(fe, fp);
440 DPRINTF(FPE_REG, ("fpu_implode: single %x\n",
445 space[0] = fpu_ftod(fe, fp, space);
446 DPRINTF(FPE_REG, ("fpu_implode: double %x %x\n",
447 space[0], space[1]));
451 panic("fpu_implode: invalid type %d", type);