1 /* $NetBSD: fpu_implode.c,v 1.6 2005/12/11 12:18:42 christos Exp $ */
4 * Copyright (c) 1992, 1993
5 * The Regents of the University of California. All rights reserved.
7 * This software was developed by the Computer Systems Engineering group
8 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
9 * contributed to Berkeley.
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13 * This product includes software developed by the University of
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40 * @(#)fpu_implode.c 8.1 (Berkeley) 6/11/93
44 * FPU subroutines: `implode' internal format numbers into the machine's
45 * `packed binary' format.
48 #include <sys/cdefs.h>
49 __FBSDID("$FreeBSD$");
51 #include <sys/types.h>
52 #include <sys/systm.h>
54 #include <machine/fpu.h>
55 #include <machine/ieee.h>
56 #include <machine/ieeefp.h>
57 #include <machine/reg.h>
59 #include <powerpc/fpu/fpu_arith.h>
60 #include <powerpc/fpu/fpu_emu.h>
61 #include <powerpc/fpu/fpu_extern.h>
62 #include <powerpc/fpu/fpu_instr.h>
64 static int round(struct fpemu *, struct fpn *);
65 static int toinf(struct fpemu *, int);
68 * Round a number (algorithm from Motorola MC68882 manual, modified for
69 * our internal format). Set inexact exception if rounding is required.
70 * Return true iff we rounded up.
72 * After rounding, we discard the guard and round bits by shifting right
73 * 2 bits (a la fpu_shr(), but we do not bother with fp->fp_sticky).
74 * This saves effort later.
76 * Note that we may leave the value 2.0 in fp->fp_mant; it is the caller's
77 * responsibility to fix this if necessary.
80 round(struct fpemu *fe, struct fpn *fp)
94 m3 = (m3 >> FP_NG) | (m2 << (32 - FP_NG));
95 m2 = (m2 >> FP_NG) | (m1 << (32 - FP_NG));
96 m1 = (m1 >> FP_NG) | (m0 << (32 - FP_NG));
99 if ((gr | s) == 0) /* result is exact: no rounding needed */
102 fe->fe_cx |= FPSCR_XX|FPSCR_FI; /* inexact */
104 /* Go to rounddown to round down; break to round up. */
105 switch ((fe->fe_fpscr) & FPSCR_RN) {
110 * Round only if guard is set (gr & 2). If guard is set,
111 * but round & sticky both clear, then we want to round
112 * but have a tie, so round to even, i.e., add 1 iff odd.
116 if ((gr & 1) || fp->fp_sticky || (m3 & 1))
121 /* Round towards zero, i.e., down. */
125 /* Round towards -Inf: up if negative, down if positive. */
131 /* Round towards +Inf: up if positive, down otherwise. */
137 /* Bump low bit of mantissa, with carry. */
138 fe->fe_cx |= FPSCR_FR;
141 FPU_ADDCS(m2, m2, 0);
142 FPU_ADDCS(m1, m1, 0);
159 * For overflow: return true if overflow is to go to +/-Inf, according
160 * to the sign of the overflowing result. If false, overflow is to go
161 * to the largest magnitude value instead.
164 toinf(struct fpemu *fe, int sign)
168 /* look at rounding direction */
169 switch ((fe->fe_fpscr) & FPSCR_RN) {
172 case FP_RN: /* the nearest value is always Inf */
176 case FP_RZ: /* toward 0 => never towards Inf */
180 case FP_RP: /* toward +Inf iff positive */
184 case FP_RM: /* toward -Inf iff negative */
189 fe->fe_cx |= FPSCR_OX;
194 * fpn -> int (int value returned as return value).
196 * N.B.: this conversion always rounds towards zero (this is a peculiarity
197 * of the SPARC instruction set).
200 fpu_ftoi(struct fpemu *fe, struct fpn *fp)
206 switch (fp->fp_class) {
213 * If exp >= 2^32, overflow. Otherwise shift value right
214 * into last mantissa word (this will not exceed 0xffffffff),
215 * shifting any guard and round bits out into the sticky
216 * bit. Then ``round'' towards zero, i.e., just set an
217 * inexact exception if sticky is set (see round()).
218 * If the result is > 0x80000000, or is positive and equals
219 * 0x80000000, overflow; otherwise the last fraction word
222 if ((exp = fp->fp_exp) >= 32)
224 /* NB: the following includes exp < 0 cases */
225 if (fpu_shr(fp, FP_NMANT - 1 - exp) != 0)
226 fe->fe_cx |= FPSCR_UX;
228 if (i >= ((u_int)0x80000000 + sign))
230 return (sign ? -i : i);
232 default: /* Inf, qNaN, sNaN */
235 /* overflow: replace any inexact exception with invalid */
236 fe->fe_cx |= FPSCR_VXCVI;
237 return (0x7fffffff + sign);
241 * fpn -> extended int (high bits of int value returned as return value).
243 * N.B.: this conversion always rounds towards zero (this is a peculiarity
244 * of the SPARC instruction set).
247 fpu_ftox(struct fpemu *fe, struct fpn *fp, u_int *res)
253 switch (fp->fp_class) {
261 * If exp >= 2^64, overflow. Otherwise shift value right
262 * into last mantissa word (this will not exceed 0xffffffffffffffff),
263 * shifting any guard and round bits out into the sticky
264 * bit. Then ``round'' towards zero, i.e., just set an
265 * inexact exception if sticky is set (see round()).
266 * If the result is > 0x8000000000000000, or is positive and equals
267 * 0x8000000000000000, overflow; otherwise the last fraction word
270 if ((exp = fp->fp_exp) >= 64)
272 /* NB: the following includes exp < 0 cases */
273 if (fpu_shr(fp, FP_NMANT - 1 - exp) != 0)
274 fe->fe_cx |= FPSCR_UX;
275 i = ((u_int64_t)fp->fp_mant[2]<<32)|fp->fp_mant[3];
276 if (i >= ((u_int64_t)0x8000000000000000LL + sign))
278 return (sign ? -i : i);
280 default: /* Inf, qNaN, sNaN */
283 /* overflow: replace any inexact exception with invalid */
284 fe->fe_cx |= FPSCR_VXCVI;
285 return (0x7fffffffffffffffLL + sign);
289 * fpn -> single (32 bit single returned as return value).
290 * We assume <= 29 bits in a single-precision fraction (1.f part).
293 fpu_ftos(struct fpemu *fe, struct fpn *fp)
295 u_int sign = fp->fp_sign << 31;
298 #define SNG_EXP(e) ((e) << SNG_FRACBITS) /* makes e an exponent */
299 #define SNG_MASK (SNG_EXP(1) - 1) /* mask for fraction */
301 /* Take care of non-numbers first. */
304 * Preserve upper bits of NaN, per SPARC V8 appendix N.
305 * Note that fp->fp_mant[0] has the quiet bit set,
306 * even if it is classified as a signalling NaN.
308 (void) fpu_shr(fp, FP_NMANT - 1 - SNG_FRACBITS);
309 exp = SNG_EXP_INFNAN;
313 return (sign | SNG_EXP(SNG_EXP_INFNAN));
318 * Normals (including subnormals). Drop all the fraction bits
319 * (including the explicit ``implied'' 1 bit) down into the
320 * single-precision range. If the number is subnormal, move
321 * the ``implied'' 1 into the explicit range as well, and shift
322 * right to introduce leading zeroes. Rounding then acts
323 * differently for normals and subnormals: the largest subnormal
324 * may round to the smallest normal (1.0 x 2^minexp), or may
325 * remain subnormal. In the latter case, signal an underflow
326 * if the result was inexact or if underflow traps are enabled.
328 * Rounding a normal, on the other hand, always produces another
329 * normal (although either way the result might be too big for
330 * single precision, and cause an overflow). If rounding a
331 * normal produces 2.0 in the fraction, we need not adjust that
332 * fraction at all, since both 1.0 and 2.0 are zero under the
335 * Note that the guard and round bits vanish from the number after
338 if ((exp = fp->fp_exp + SNG_EXP_BIAS) <= 0) { /* subnormal */
339 /* -NG for g,r; -SNG_FRACBITS-exp for fraction */
340 (void) fpu_shr(fp, FP_NMANT - FP_NG - SNG_FRACBITS - exp);
341 if (round(fe, fp) && fp->fp_mant[3] == SNG_EXP(1))
342 return (sign | SNG_EXP(1) | 0);
343 if ((fe->fe_cx & FPSCR_FI) ||
344 (fe->fe_fpscr & FPSCR_UX))
345 fe->fe_cx |= FPSCR_UX;
346 return (sign | SNG_EXP(0) | fp->fp_mant[3]);
348 /* -FP_NG for g,r; -1 for implied 1; -SNG_FRACBITS for fraction */
349 (void) fpu_shr(fp, FP_NMANT - FP_NG - 1 - SNG_FRACBITS);
351 if ((fp->fp_mant[3] & SNG_EXP(1 << FP_NG)) == 0)
354 if (round(fe, fp) && fp->fp_mant[3] == SNG_EXP(2))
356 if (exp >= SNG_EXP_INFNAN) {
357 /* overflow to inf or to max single */
359 return (sign | SNG_EXP(SNG_EXP_INFNAN));
360 return (sign | SNG_EXP(SNG_EXP_INFNAN - 1) | SNG_MASK);
364 return (sign | SNG_EXP(exp) | (fp->fp_mant[3] & SNG_MASK));
368 * fpn -> double (32 bit high-order result returned; 32-bit low order result
369 * left in res[1]). Assumes <= 61 bits in double precision fraction.
371 * This code mimics fpu_ftos; see it for comments.
374 fpu_ftod(struct fpemu *fe, struct fpn *fp, u_int *res)
376 u_int sign = fp->fp_sign << 31;
379 #define DBL_EXP(e) ((e) << (DBL_FRACBITS & 31))
380 #define DBL_MASK (DBL_EXP(1) - 1)
383 (void) fpu_shr(fp, FP_NMANT - 1 - DBL_FRACBITS);
384 exp = DBL_EXP_INFNAN;
388 sign |= DBL_EXP(DBL_EXP_INFNAN);
396 if ((exp = fp->fp_exp + DBL_EXP_BIAS) <= 0) {
397 (void) fpu_shr(fp, FP_NMANT - FP_NG - DBL_FRACBITS - exp);
398 if (round(fe, fp) && fp->fp_mant[2] == DBL_EXP(1)) {
400 return (sign | DBL_EXP(1) | 0);
402 if ((fe->fe_cx & FPSCR_FI) ||
403 (fe->fe_fpscr & FPSCR_UX))
404 fe->fe_cx |= FPSCR_UX;
408 (void) fpu_shr(fp, FP_NMANT - FP_NG - 1 - DBL_FRACBITS);
409 if (round(fe, fp) && fp->fp_mant[2] == DBL_EXP(2))
411 if (exp >= DBL_EXP_INFNAN) {
412 fe->fe_cx |= FPSCR_OX | FPSCR_UX;
413 if (toinf(fe, sign)) {
415 return (sign | DBL_EXP(DBL_EXP_INFNAN) | 0);
418 return (sign | DBL_EXP(DBL_EXP_INFNAN) | DBL_MASK);
421 res[1] = fp->fp_mant[3];
422 return (sign | DBL_EXP(exp) | (fp->fp_mant[2] & DBL_MASK));
426 * Implode an fpn, writing the result into the given space.
429 fpu_implode(struct fpemu *fe, struct fpn *fp, int type, u_int *space)
435 space[0] = fpu_ftox(fe, fp, space);
436 DPRINTF(FPE_REG, ("fpu_implode: long %x %x\n",
437 space[0], space[1]));
442 space[1] = fpu_ftoi(fe, fp);
443 DPRINTF(FPE_REG, ("fpu_implode: int %x\n",
448 space[0] = fpu_ftos(fe, fp);
449 DPRINTF(FPE_REG, ("fpu_implode: single %x\n",
454 space[0] = fpu_ftod(fe, fp, space);
455 DPRINTF(FPE_REG, ("fpu_implode: double %x %x\n",
456 space[0], space[1]));
460 panic("fpu_implode: invalid type %d", type);