1 /* $NetBSD: fpu_implode.c,v 1.6 2005/12/11 12:18:42 christos Exp $ */
4 * SPDX-License-Identifier: BSD-3-Clause
6 * Copyright (c) 1992, 1993
7 * The Regents of the University of California. All rights reserved.
9 * This software was developed by the Computer Systems Engineering group
10 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
11 * contributed to Berkeley.
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15 * This product includes software developed by the University of
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42 * @(#)fpu_implode.c 8.1 (Berkeley) 6/11/93
46 * FPU subroutines: `implode' internal format numbers into the machine's
47 * `packed binary' format.
50 #include <sys/cdefs.h>
51 __FBSDID("$FreeBSD$");
53 #include <sys/types.h>
54 #include <sys/systm.h>
56 #include <machine/fpu.h>
57 #include <machine/ieee.h>
58 #include <machine/ieeefp.h>
59 #include <machine/reg.h>
61 #include <powerpc/fpu/fpu_arith.h>
62 #include <powerpc/fpu/fpu_emu.h>
63 #include <powerpc/fpu/fpu_extern.h>
64 #include <powerpc/fpu/fpu_instr.h>
66 static int round(struct fpemu *, struct fpn *);
67 static int toinf(struct fpemu *, int);
70 * Round a number (algorithm from Motorola MC68882 manual, modified for
71 * our internal format). Set inexact exception if rounding is required.
72 * Return true iff we rounded up.
74 * After rounding, we discard the guard and round bits by shifting right
75 * 2 bits (a la fpu_shr(), but we do not bother with fp->fp_sticky).
76 * This saves effort later.
78 * Note that we may leave the value 2.0 in fp->fp_mant; it is the caller's
79 * responsibility to fix this if necessary.
82 round(struct fpemu *fe, struct fpn *fp)
96 m3 = (m3 >> FP_NG) | (m2 << (32 - FP_NG));
97 m2 = (m2 >> FP_NG) | (m1 << (32 - FP_NG));
98 m1 = (m1 >> FP_NG) | (m0 << (32 - FP_NG));
101 if ((gr | s) == 0) /* result is exact: no rounding needed */
104 fe->fe_cx |= FPSCR_XX|FPSCR_FI; /* inexact */
106 /* Go to rounddown to round down; break to round up. */
107 switch ((fe->fe_fpscr) & FPSCR_RN) {
112 * Round only if guard is set (gr & 2). If guard is set,
113 * but round & sticky both clear, then we want to round
114 * but have a tie, so round to even, i.e., add 1 iff odd.
118 if ((gr & 1) || fp->fp_sticky || (m3 & 1))
123 /* Round towards zero, i.e., down. */
127 /* Round towards -Inf: up if negative, down if positive. */
133 /* Round towards +Inf: up if positive, down otherwise. */
139 /* Bump low bit of mantissa, with carry. */
140 fe->fe_cx |= FPSCR_FR;
143 FPU_ADDCS(m2, m2, 0);
144 FPU_ADDCS(m1, m1, 0);
161 * For overflow: return true if overflow is to go to +/-Inf, according
162 * to the sign of the overflowing result. If false, overflow is to go
163 * to the largest magnitude value instead.
166 toinf(struct fpemu *fe, int sign)
170 /* look at rounding direction */
171 switch ((fe->fe_fpscr) & FPSCR_RN) {
174 case FP_RN: /* the nearest value is always Inf */
178 case FP_RZ: /* toward 0 => never towards Inf */
182 case FP_RP: /* toward +Inf iff positive */
186 case FP_RM: /* toward -Inf iff negative */
191 fe->fe_cx |= FPSCR_OX;
196 * fpn -> int (int value returned as return value).
198 * N.B.: this conversion always rounds towards zero (this is a peculiarity
199 * of the SPARC instruction set).
202 fpu_ftoi(struct fpemu *fe, struct fpn *fp)
208 switch (fp->fp_class) {
215 * If exp >= 2^32, overflow. Otherwise shift value right
216 * into last mantissa word (this will not exceed 0xffffffff),
217 * shifting any guard and round bits out into the sticky
218 * bit. Then ``round'' towards zero, i.e., just set an
219 * inexact exception if sticky is set (see round()).
220 * If the result is > 0x80000000, or is positive and equals
221 * 0x80000000, overflow; otherwise the last fraction word
224 if ((exp = fp->fp_exp) >= 32)
226 /* NB: the following includes exp < 0 cases */
227 if (fpu_shr(fp, FP_NMANT - 1 - exp) != 0)
228 fe->fe_cx |= FPSCR_UX;
230 if (i >= ((u_int)0x80000000 + sign))
232 return (sign ? -i : i);
234 default: /* Inf, qNaN, sNaN */
237 /* overflow: replace any inexact exception with invalid */
238 fe->fe_cx |= FPSCR_VXCVI;
239 return (0x7fffffff + sign);
243 * fpn -> extended int (high bits of int value returned as return value).
245 * N.B.: this conversion always rounds towards zero (this is a peculiarity
246 * of the SPARC instruction set).
249 fpu_ftox(struct fpemu *fe, struct fpn *fp, u_int *res)
255 switch (fp->fp_class) {
263 * If exp >= 2^64, overflow. Otherwise shift value right
264 * into last mantissa word (this will not exceed 0xffffffffffffffff),
265 * shifting any guard and round bits out into the sticky
266 * bit. Then ``round'' towards zero, i.e., just set an
267 * inexact exception if sticky is set (see round()).
268 * If the result is > 0x8000000000000000, or is positive and equals
269 * 0x8000000000000000, overflow; otherwise the last fraction word
272 if ((exp = fp->fp_exp) >= 64)
274 /* NB: the following includes exp < 0 cases */
275 if (fpu_shr(fp, FP_NMANT - 1 - exp) != 0)
276 fe->fe_cx |= FPSCR_UX;
277 i = ((u_int64_t)fp->fp_mant[2]<<32)|fp->fp_mant[3];
278 if (i >= ((u_int64_t)0x8000000000000000LL + sign))
280 return (sign ? -i : i);
282 default: /* Inf, qNaN, sNaN */
285 /* overflow: replace any inexact exception with invalid */
286 fe->fe_cx |= FPSCR_VXCVI;
287 return (0x7fffffffffffffffLL + sign);
291 * fpn -> single (32 bit single returned as return value).
292 * We assume <= 29 bits in a single-precision fraction (1.f part).
295 fpu_ftos(struct fpemu *fe, struct fpn *fp)
297 u_int sign = fp->fp_sign << 31;
300 #define SNG_EXP(e) ((e) << SNG_FRACBITS) /* makes e an exponent */
301 #define SNG_MASK (SNG_EXP(1) - 1) /* mask for fraction */
303 /* Take care of non-numbers first. */
306 * Preserve upper bits of NaN, per SPARC V8 appendix N.
307 * Note that fp->fp_mant[0] has the quiet bit set,
308 * even if it is classified as a signalling NaN.
310 (void) fpu_shr(fp, FP_NMANT - 1 - SNG_FRACBITS);
311 exp = SNG_EXP_INFNAN;
315 return (sign | SNG_EXP(SNG_EXP_INFNAN));
320 * Normals (including subnormals). Drop all the fraction bits
321 * (including the explicit ``implied'' 1 bit) down into the
322 * single-precision range. If the number is subnormal, move
323 * the ``implied'' 1 into the explicit range as well, and shift
324 * right to introduce leading zeroes. Rounding then acts
325 * differently for normals and subnormals: the largest subnormal
326 * may round to the smallest normal (1.0 x 2^minexp), or may
327 * remain subnormal. In the latter case, signal an underflow
328 * if the result was inexact or if underflow traps are enabled.
330 * Rounding a normal, on the other hand, always produces another
331 * normal (although either way the result might be too big for
332 * single precision, and cause an overflow). If rounding a
333 * normal produces 2.0 in the fraction, we need not adjust that
334 * fraction at all, since both 1.0 and 2.0 are zero under the
337 * Note that the guard and round bits vanish from the number after
340 if ((exp = fp->fp_exp + SNG_EXP_BIAS) <= 0) { /* subnormal */
341 /* -NG for g,r; -SNG_FRACBITS-exp for fraction */
342 (void) fpu_shr(fp, FP_NMANT - FP_NG - SNG_FRACBITS - exp);
343 if (round(fe, fp) && fp->fp_mant[3] == SNG_EXP(1))
344 return (sign | SNG_EXP(1) | 0);
345 if ((fe->fe_cx & FPSCR_FI) ||
346 (fe->fe_fpscr & FPSCR_UX))
347 fe->fe_cx |= FPSCR_UX;
348 return (sign | SNG_EXP(0) | fp->fp_mant[3]);
350 /* -FP_NG for g,r; -1 for implied 1; -SNG_FRACBITS for fraction */
351 (void) fpu_shr(fp, FP_NMANT - FP_NG - 1 - SNG_FRACBITS);
353 if ((fp->fp_mant[3] & SNG_EXP(1 << FP_NG)) == 0)
356 if (round(fe, fp) && fp->fp_mant[3] == SNG_EXP(2))
358 if (exp >= SNG_EXP_INFNAN) {
359 /* overflow to inf or to max single */
361 return (sign | SNG_EXP(SNG_EXP_INFNAN));
362 return (sign | SNG_EXP(SNG_EXP_INFNAN - 1) | SNG_MASK);
366 return (sign | SNG_EXP(exp) | (fp->fp_mant[3] & SNG_MASK));
370 * fpn -> double (32 bit high-order result returned; 32-bit low order result
371 * left in res[1]). Assumes <= 61 bits in double precision fraction.
373 * This code mimics fpu_ftos; see it for comments.
376 fpu_ftod(struct fpemu *fe, struct fpn *fp, u_int *res)
378 u_int sign = fp->fp_sign << 31;
381 #define DBL_EXP(e) ((e) << (DBL_FRACBITS & 31))
382 #define DBL_MASK (DBL_EXP(1) - 1)
385 (void) fpu_shr(fp, FP_NMANT - 1 - DBL_FRACBITS);
386 exp = DBL_EXP_INFNAN;
390 sign |= DBL_EXP(DBL_EXP_INFNAN);
398 if ((exp = fp->fp_exp + DBL_EXP_BIAS) <= 0) {
399 (void) fpu_shr(fp, FP_NMANT - FP_NG - DBL_FRACBITS - exp);
400 if (round(fe, fp) && fp->fp_mant[2] == DBL_EXP(1)) {
402 return (sign | DBL_EXP(1) | 0);
404 if ((fe->fe_cx & FPSCR_FI) ||
405 (fe->fe_fpscr & FPSCR_UX))
406 fe->fe_cx |= FPSCR_UX;
410 (void) fpu_shr(fp, FP_NMANT - FP_NG - 1 - DBL_FRACBITS);
411 if (round(fe, fp) && fp->fp_mant[2] == DBL_EXP(2))
413 if (exp >= DBL_EXP_INFNAN) {
414 fe->fe_cx |= FPSCR_OX | FPSCR_UX;
415 if (toinf(fe, sign)) {
417 return (sign | DBL_EXP(DBL_EXP_INFNAN) | 0);
420 return (sign | DBL_EXP(DBL_EXP_INFNAN) | DBL_MASK);
423 res[1] = fp->fp_mant[3];
424 return (sign | DBL_EXP(exp) | (fp->fp_mant[2] & DBL_MASK));
428 * Implode an fpn, writing the result into the given space.
431 fpu_implode(struct fpemu *fe, struct fpn *fp, int type, u_int *space)
437 space[0] = fpu_ftox(fe, fp, space);
438 DPRINTF(FPE_REG, ("fpu_implode: long %x %x\n",
439 space[0], space[1]));
444 space[1] = fpu_ftoi(fe, fp);
445 DPRINTF(FPE_REG, ("fpu_implode: int %x\n",
450 space[0] = fpu_ftos(fe, fp);
451 DPRINTF(FPE_REG, ("fpu_implode: single %x\n",
456 space[0] = fpu_ftod(fe, fp, space);
457 DPRINTF(FPE_REG, ("fpu_implode: double %x %x\n",
458 space[0], space[1]));
462 panic("fpu_implode: invalid type %d", type);