1 /* $NetBSD: fpu_implode.c,v 1.6 2005/12/11 12:18:42 christos Exp $ */
4 * SPDX-License-Identifier: BSD-3-Clause
6 * Copyright (c) 1992, 1993
7 * The Regents of the University of California. All rights reserved.
9 * This software was developed by the Computer Systems Engineering group
10 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
11 * contributed to Berkeley.
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15 * This product includes software developed by the University of
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42 * @(#)fpu_implode.c 8.1 (Berkeley) 6/11/93
46 * FPU subroutines: `implode' internal format numbers into the machine's
47 * `packed binary' format.
50 #include <sys/cdefs.h>
51 __FBSDID("$FreeBSD$");
53 #include <sys/types.h>
54 #include <sys/systm.h>
56 #include <machine/fpu.h>
57 #include <machine/ieee.h>
58 #include <machine/ieeefp.h>
60 #include <powerpc/fpu/fpu_arith.h>
61 #include <powerpc/fpu/fpu_emu.h>
62 #include <powerpc/fpu/fpu_extern.h>
63 #include <powerpc/fpu/fpu_instr.h>
65 static int round(struct fpemu *, struct fpn *);
66 static int toinf(struct fpemu *, int);
69 * Round a number (algorithm from Motorola MC68882 manual, modified for
70 * our internal format). Set inexact exception if rounding is required.
71 * Return true iff we rounded up.
73 * After rounding, we discard the guard and round bits by shifting right
74 * 2 bits (a la fpu_shr(), but we do not bother with fp->fp_sticky).
75 * This saves effort later.
77 * Note that we may leave the value 2.0 in fp->fp_mant; it is the caller's
78 * responsibility to fix this if necessary.
81 round(struct fpemu *fe, struct fpn *fp)
95 m3 = (m3 >> FP_NG) | (m2 << (32 - FP_NG));
96 m2 = (m2 >> FP_NG) | (m1 << (32 - FP_NG));
97 m1 = (m1 >> FP_NG) | (m0 << (32 - FP_NG));
100 if ((gr | s) == 0) /* result is exact: no rounding needed */
103 fe->fe_cx |= FPSCR_XX|FPSCR_FI; /* inexact */
105 /* Go to rounddown to round down; break to round up. */
106 switch ((fe->fe_fpscr) & FPSCR_RN) {
110 * Round only if guard is set (gr & 2). If guard is set,
111 * but round & sticky both clear, then we want to round
112 * but have a tie, so round to even, i.e., add 1 iff odd.
116 if ((gr & 1) || fp->fp_sticky || (m3 & 1))
121 /* Round towards zero, i.e., down. */
125 /* Round towards -Inf: up if negative, down if positive. */
131 /* Round towards +Inf: up if positive, down otherwise. */
137 /* Bump low bit of mantissa, with carry. */
138 fe->fe_cx |= FPSCR_FR;
141 FPU_ADDCS(m2, m2, 0);
142 FPU_ADDCS(m1, m1, 0);
159 * For overflow: return true if overflow is to go to +/-Inf, according
160 * to the sign of the overflowing result. If false, overflow is to go
161 * to the largest magnitude value instead.
164 toinf(struct fpemu *fe, int sign)
168 /* look at rounding direction */
169 switch ((fe->fe_fpscr) & FPSCR_RN) {
171 case FP_RN: /* the nearest value is always Inf */
175 case FP_RZ: /* toward 0 => never towards Inf */
179 case FP_RP: /* toward +Inf iff positive */
183 case FP_RM: /* toward -Inf iff negative */
188 fe->fe_cx |= FPSCR_OX;
193 * fpn -> int (int value returned as return value).
195 * N.B.: this conversion always rounds towards zero (this is a peculiarity
196 * of the SPARC instruction set).
199 fpu_ftoi(struct fpemu *fe, struct fpn *fp)
205 switch (fp->fp_class) {
211 * If exp >= 2^32, overflow. Otherwise shift value right
212 * into last mantissa word (this will not exceed 0xffffffff),
213 * shifting any guard and round bits out into the sticky
214 * bit. Then ``round'' towards zero, i.e., just set an
215 * inexact exception if sticky is set (see round()).
216 * If the result is > 0x80000000, or is positive and equals
217 * 0x80000000, overflow; otherwise the last fraction word
220 if ((exp = fp->fp_exp) >= 32)
222 /* NB: the following includes exp < 0 cases */
223 if (fpu_shr(fp, FP_NMANT - 1 - exp) != 0)
224 fe->fe_cx |= FPSCR_UX;
226 if (i >= ((u_int)0x80000000 + sign))
228 return (sign ? -i : i);
230 default: /* Inf, qNaN, sNaN */
233 /* overflow: replace any inexact exception with invalid */
234 fe->fe_cx |= FPSCR_VXCVI;
235 return (0x7fffffff + sign);
239 * fpn -> extended int (high bits of int value returned as return value).
241 * N.B.: this conversion always rounds towards zero (this is a peculiarity
242 * of the SPARC instruction set).
245 fpu_ftox(struct fpemu *fe, struct fpn *fp, u_int *res)
251 switch (fp->fp_class) {
258 * If exp >= 2^64, overflow. Otherwise shift value right
259 * into last mantissa word (this will not exceed 0xffffffffffffffff),
260 * shifting any guard and round bits out into the sticky
261 * bit. Then ``round'' towards zero, i.e., just set an
262 * inexact exception if sticky is set (see round()).
263 * If the result is > 0x8000000000000000, or is positive and equals
264 * 0x8000000000000000, overflow; otherwise the last fraction word
267 if ((exp = fp->fp_exp) >= 64)
269 /* NB: the following includes exp < 0 cases */
270 if (fpu_shr(fp, FP_NMANT - 1 - exp) != 0)
271 fe->fe_cx |= FPSCR_UX;
272 i = ((u_int64_t)fp->fp_mant[2]<<32)|fp->fp_mant[3];
273 if (i >= ((u_int64_t)0x8000000000000000LL + sign))
275 return (sign ? -i : i);
277 default: /* Inf, qNaN, sNaN */
280 /* overflow: replace any inexact exception with invalid */
281 fe->fe_cx |= FPSCR_VXCVI;
282 return (0x7fffffffffffffffLL + sign);
286 * fpn -> single (32 bit single returned as return value).
287 * We assume <= 29 bits in a single-precision fraction (1.f part).
290 fpu_ftos(struct fpemu *fe, struct fpn *fp)
292 u_int sign = fp->fp_sign << 31;
295 #define SNG_EXP(e) ((e) << SNG_FRACBITS) /* makes e an exponent */
296 #define SNG_MASK (SNG_EXP(1) - 1) /* mask for fraction */
298 /* Take care of non-numbers first. */
301 * Preserve upper bits of NaN, per SPARC V8 appendix N.
302 * Note that fp->fp_mant[0] has the quiet bit set,
303 * even if it is classified as a signalling NaN.
305 (void) fpu_shr(fp, FP_NMANT - 1 - SNG_FRACBITS);
306 exp = SNG_EXP_INFNAN;
310 return (sign | SNG_EXP(SNG_EXP_INFNAN));
315 * Normals (including subnormals). Drop all the fraction bits
316 * (including the explicit ``implied'' 1 bit) down into the
317 * single-precision range. If the number is subnormal, move
318 * the ``implied'' 1 into the explicit range as well, and shift
319 * right to introduce leading zeroes. Rounding then acts
320 * differently for normals and subnormals: the largest subnormal
321 * may round to the smallest normal (1.0 x 2^minexp), or may
322 * remain subnormal. In the latter case, signal an underflow
323 * if the result was inexact or if underflow traps are enabled.
325 * Rounding a normal, on the other hand, always produces another
326 * normal (although either way the result might be too big for
327 * single precision, and cause an overflow). If rounding a
328 * normal produces 2.0 in the fraction, we need not adjust that
329 * fraction at all, since both 1.0 and 2.0 are zero under the
332 * Note that the guard and round bits vanish from the number after
335 if ((exp = fp->fp_exp + SNG_EXP_BIAS) <= 0) { /* subnormal */
336 /* -NG for g,r; -SNG_FRACBITS-exp for fraction */
337 (void) fpu_shr(fp, FP_NMANT - FP_NG - SNG_FRACBITS - exp);
338 if (round(fe, fp) && fp->fp_mant[3] == SNG_EXP(1))
339 return (sign | SNG_EXP(1) | 0);
340 if ((fe->fe_cx & FPSCR_FI) ||
341 (fe->fe_fpscr & FPSCR_UX))
342 fe->fe_cx |= FPSCR_UX;
343 return (sign | SNG_EXP(0) | fp->fp_mant[3]);
345 /* -FP_NG for g,r; -1 for implied 1; -SNG_FRACBITS for fraction */
346 (void) fpu_shr(fp, FP_NMANT - FP_NG - 1 - SNG_FRACBITS);
348 if ((fp->fp_mant[3] & SNG_EXP(1 << FP_NG)) == 0)
351 if (round(fe, fp) && fp->fp_mant[3] == SNG_EXP(2))
353 if (exp >= SNG_EXP_INFNAN) {
354 /* overflow to inf or to max single */
356 return (sign | SNG_EXP(SNG_EXP_INFNAN));
357 return (sign | SNG_EXP(SNG_EXP_INFNAN - 1) | SNG_MASK);
361 return (sign | SNG_EXP(exp) | (fp->fp_mant[3] & SNG_MASK));
365 * fpn -> double (32 bit high-order result returned; 32-bit low order result
366 * left in res[1]). Assumes <= 61 bits in double precision fraction.
368 * This code mimics fpu_ftos; see it for comments.
371 fpu_ftod(struct fpemu *fe, struct fpn *fp, u_int *res)
373 u_int sign = fp->fp_sign << 31;
376 #define DBL_EXP(e) ((e) << (DBL_FRACBITS & 31))
377 #define DBL_MASK (DBL_EXP(1) - 1)
380 (void) fpu_shr(fp, FP_NMANT - 1 - DBL_FRACBITS);
381 exp = DBL_EXP_INFNAN;
385 sign |= DBL_EXP(DBL_EXP_INFNAN);
393 if ((exp = fp->fp_exp + DBL_EXP_BIAS) <= 0) {
394 (void) fpu_shr(fp, FP_NMANT - FP_NG - DBL_FRACBITS - exp);
395 if (round(fe, fp) && fp->fp_mant[2] == DBL_EXP(1)) {
397 return (sign | DBL_EXP(1) | 0);
399 if ((fe->fe_cx & FPSCR_FI) ||
400 (fe->fe_fpscr & FPSCR_UX))
401 fe->fe_cx |= FPSCR_UX;
405 (void) fpu_shr(fp, FP_NMANT - FP_NG - 1 - DBL_FRACBITS);
406 if (round(fe, fp) && fp->fp_mant[2] == DBL_EXP(2))
408 if (exp >= DBL_EXP_INFNAN) {
409 fe->fe_cx |= FPSCR_OX | FPSCR_UX;
410 if (toinf(fe, sign)) {
412 return (sign | DBL_EXP(DBL_EXP_INFNAN) | 0);
415 return (sign | DBL_EXP(DBL_EXP_INFNAN) | DBL_MASK);
418 res[1] = fp->fp_mant[3];
419 return (sign | DBL_EXP(exp) | (fp->fp_mant[2] & DBL_MASK));
423 * Implode an fpn, writing the result into the given space.
426 fpu_implode(struct fpemu *fe, struct fpn *fp, int type, u_int *space)
431 space[0] = fpu_ftox(fe, fp, space);
432 DPRINTF(FPE_REG, ("fpu_implode: long %x %x\n",
433 space[0], space[1]));
438 space[1] = fpu_ftoi(fe, fp);
439 DPRINTF(FPE_REG, ("fpu_implode: int %x\n",
444 space[0] = fpu_ftos(fe, fp);
445 DPRINTF(FPE_REG, ("fpu_implode: single %x\n",
450 space[0] = fpu_ftod(fe, fp, space);
451 DPRINTF(FPE_REG, ("fpu_implode: double %x %x\n",
452 space[0], space[1]));
456 panic("fpu_implode: invalid type %d", type);