1 /* $NetBSD: fpu_subr.c,v 1.4 2005/12/11 12:18:42 christos Exp $ */
4 * SPDX-License-Identifier: BSD-3-Clause
6 * Copyright (c) 1992, 1993
7 * The Regents of the University of California. All rights reserved.
9 * This software was developed by the Computer Systems Engineering group
10 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
11 * contributed to Berkeley.
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14 * must display the following acknowledgement:
15 * This product includes software developed by the University of
16 * California, Lawrence Berkeley Laboratory.
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19 * modification, are permitted provided that the following conditions
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42 * @(#)fpu_subr.c 8.1 (Berkeley) 6/11/93
49 #include <sys/cdefs.h>
50 __FBSDID("$FreeBSD$");
52 #include <sys/types.h>
53 #include <sys/systm.h>
55 #include <machine/fpu.h>
57 #include <powerpc/fpu/fpu_arith.h>
58 #include <powerpc/fpu/fpu_emu.h>
61 * Shift the given number right rsh bits. Any bits that `fall off' will get
62 * shoved into the sticky field; we return the resulting sticky. Note that
63 * shifting NaNs is legal (this will never shift all bits out); a NaN's
64 * sticky field is ignored anyway.
67 fpu_shr(struct fpn *fp, int rsh)
69 u_int m0, m1, m2, m3, s;
73 if (rsh <= 0 || (fp->fp_class != FPC_NUM && !ISNAN(fp)))
74 panic("fpu_rightshift 1");
82 /* If shifting all the bits out, take a shortcut. */
83 if (rsh >= FP_NMANT) {
85 if ((m0 | m1 | m2 | m3) == 0)
86 panic("fpu_rightshift 2");
93 if ((m0 | m1 | m2 | m3) == 0)
94 fp->fp_class = FPC_ZERO;
101 /* Squish out full words. */
105 m3 = m0, m2 = 0, m1 = 0, m0 = 0;
106 } else if (rsh >= 32 * 2) {
108 m3 = m1, m2 = m0, m1 = 0, m0 = 0;
109 } else if (rsh >= 32) {
111 m3 = m2, m2 = m1, m1 = m0, m0 = 0;
114 /* Handle any remaining partial word. */
115 if ((rsh &= 31) != 0) {
118 m3 = (m3 >> rsh) | (m2 << lsh);
119 m2 = (m2 >> rsh) | (m1 << lsh);
120 m1 = (m1 >> rsh) | (m0 << lsh);
132 * Force a number to be normal, i.e., make its fraction have all zero
133 * bits before FP_1, then FP_1, then all 1 bits. This is used for denorms
134 * and (sometimes) for intermediate results.
136 * Internally, this may use a `supernormal' -- a number whose fp_mant
137 * is greater than or equal to 2.0 -- so as a side effect you can hand it
138 * a supernormal and it will fix it (provided fp->fp_mant[3] == 0).
141 fpu_norm(struct fpn *fp)
143 u_int m0, m1, m2, m3, top, sup, nrm;
152 /* Handle severe subnormals with 32-bit moves. */
155 m0 = m1, m1 = m2, m2 = m3, m3 = 0, exp -= 32;
157 m0 = m2, m1 = m3, m2 = 0, m3 = 0, exp -= 2 * 32;
159 m0 = m3, m1 = 0, m2 = 0, m3 = 0, exp -= 3 * 32;
161 fp->fp_class = FPC_ZERO;
166 /* Now fix any supernormal or remaining subnormal. */
171 * We have a supernormal number. We need to shift it right.
172 * We may assume m3==0.
174 for (rsh = 1, top = m0 >> 1; top >= sup; rsh++) /* XXX slow */
179 m2 = (m2 >> rsh) | (m1 << lsh);
180 m1 = (m1 >> rsh) | (m0 << lsh);
182 } else if (m0 < nrm) {
184 * We have a regular denorm (a subnormal number), and need
187 for (lsh = 1, top = m0 << 1; top < nrm; lsh++) /* XXX slow */
191 m0 = top | (m1 >> rsh);
192 m1 = (m1 << lsh) | (m2 >> rsh);
193 m2 = (m2 << lsh) | (m3 >> rsh);
205 * Concoct a `fresh' Quiet NaN per Appendix N.
206 * As a side effect, we set NV (invalid) for the current exceptions.
209 fpu_newnan(struct fpemu *fe)
213 fe->fe_cx |= FPSCR_VXSNAN;
215 fp->fp_class = FPC_QNAN;
217 fp->fp_mant[0] = FP_1 - 1;
218 fp->fp_mant[1] = fp->fp_mant[2] = fp->fp_mant[3] = ~0;
219 DUMPFPN(FPE_REG, fp);