2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 1998 Doug Rabson
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 #ifndef _MACHINE_CPUFUNC_H_
32 #define _MACHINE_CPUFUNC_H_
36 #include <sys/types.h>
38 #include <machine/psl.h>
39 #include <machine/spr.h>
44 void breakpoint(void);
54 /* CPU register mangling inlines */
57 mtmsr(register_t value)
60 __asm __volatile ("mtmsr %0; isync" :: "r"(value));
65 mtmsrd(register_t value)
68 __asm __volatile ("mtmsrd %0; isync" :: "r"(value));
72 static __inline register_t
77 __asm __volatile ("mfmsr %0" : "=r"(value));
84 mtsrin(vm_offset_t va, register_t value)
87 __asm __volatile ("mtsrin %0,%1; isync" :: "r"(value), "r"(va));
90 static __inline register_t
91 mfsrin(vm_offset_t va)
95 __asm __volatile ("mfsrin %0,%1" : "=r"(value) : "r"(va));
101 static __inline register_t
106 __asm __volatile ("mfspr %0,136" : "=r"(value));
112 mtdec(register_t value)
115 __asm __volatile ("mtdec %0" :: "r"(value));
118 static __inline register_t
123 __asm __volatile ("mfdec %0" : "=r"(value));
128 static __inline uint32_t
133 __asm __volatile ("mfpvr %0" : "=r"(value));
138 static __inline u_quad_t
143 __asm __volatile ("mftb %0" : "=r"(tb));
145 uint32_t *tbup = (uint32_t *)&tb;
146 uint32_t *tblp = tbup + 1;
149 *tbup = mfspr(TBR_TBU);
150 *tblp = mfspr(TBR_TBL);
151 } while (*tbup != mfspr(TBR_TBU));
162 mtspr(TBR_TBWU, (uint32_t)(time >> 32));
163 mtspr(TBR_TBWL, (uint32_t)(time & 0xffffffff));
166 static __inline register_t
171 __asm __volatile ("mffs 0; stfd 0,0(%0)"
174 return ((register_t)value);
178 mtfsf(uint64_t value)
181 __asm __volatile ("lfd 0,0(%0); mtfsf 0xff,0"
189 __asm __volatile ("eieio" : : : "memory");
196 __asm __volatile ("isync" : : : "memory");
203 __asm __volatile ("sync" : : : "memory");
207 cntlzd(uint64_t word)
211 __asm __volatile(".long 0x7c000074 | (%1 << 21) | (%0 << 16)" :
212 "=r"(result) : "r"(word));
218 cnttzd(uint64_t word)
222 __asm __volatile(".long 0x7c000474 | (%1 << 21) | (%0 << 16)" :
223 "=r"(result) : "r"(word));
231 __asm __volatile("ptesync");
234 static __inline register_t
240 mtmsr(msr & ~PSL_EE);
245 intr_restore(register_t msr)
251 static __inline struct pcpu *
256 __asm __volatile("mfsprg %0, 0" : "=r"(ret));
261 #define HAVE_INLINE_FLS
262 static __inline __pure2 int
265 return (mask ? 32 - __builtin_clz(mask) : 0);
268 #define HAVE_INLINE_FLSL
269 static __inline __pure2 int
272 return (mask ? (8 * sizeof(long) - __builtin_clzl(mask)) : 0);
275 /* "NOP" operations to signify priorities to the kernel. */
279 __asm __volatile("or 31,31,31");
285 __asm __volatile("or 1,1,1");
291 __asm __volatile("or 6,6,6");
295 nop_prio_medium(void)
297 __asm __volatile("or 2,2,2");
303 __asm __volatile("or 5,5,5");
309 __asm __volatile("or 3,3,3");
314 #endif /* !_MACHINE_CPUFUNC_H_ */