2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2008 Nathan Whitehorn
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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31 #ifndef _MACHINE_DBDMA_H_
32 #define _MACHINE_DBDMA_H_
34 #include <sys/param.h>
35 #include <machine/bus.h>
38 * Apple's DBDMA (Descriptor-based DMA) interface is a common DMA engine
39 * used by a variety of custom Apple ASICs. It is described in the CHRP
40 * specification and in the book Macintosh Technology in the Common
41 * Hardware Reference Platform, copyright 1995 Apple Computer.
44 /* DBDMA Command Values */
47 DBDMA_OUTPUT_MORE = 0,
48 DBDMA_OUTPUT_LAST = 1,
58 /* These codes are for the interrupt, branch, and wait flags */
67 /* Channel status bits */
68 #define DBDMA_STATUS_RUN (0x01 << 15)
69 #define DBDMA_STATUS_PAUSE (0x01 << 14)
70 #define DBDMA_STATUS_FLUSH (0x01 << 13)
71 #define DBDMA_STATUS_WAKE (0x01 << 12)
72 #define DBDMA_STATUS_DEAD (0x01 << 11)
73 #define DBDMA_STATUS_ACTIVE (0x01 << 10)
75 /* Set by hardware if a branch was taken */
76 #define DBDMA_STATUS_BRANCH 8
79 typedef struct dbdma_command dbdma_command_t;
81 typedef struct dbdma_channel dbdma_channel_t;
83 int dbdma_allocate_channel(struct resource *dbdma_regs, u_int offset,
84 bus_dma_tag_t parent_dma, int slots, dbdma_channel_t **chan);
86 int dbdma_resize_channel(dbdma_channel_t *chan, int newslots);
87 int dbdma_free_channel(dbdma_channel_t *chan);
89 void dbdma_run(dbdma_channel_t *chan);
90 void dbdma_stop(dbdma_channel_t *chan);
91 void dbdma_reset(dbdma_channel_t *chan);
92 void dbdma_set_current_cmd(dbdma_channel_t *chan, int slot);
94 void dbdma_pause(dbdma_channel_t *chan);
95 void dbdma_wake(dbdma_channel_t *chan);
98 * DBDMA uses a 16 bit channel control register to describe the current
99 * state of DMA on the channel. The high-order bits (8-15) contain information
100 * on the run state and are listed in the DBDMA_STATUS_* constants above. These
101 * are manipulated with the dbdma_run/stop/reset() routines above.
103 * The low order bits (0-7) are device dependent status bits. These can be set
104 * and read by both hardware and software. The mask is the set of bits to
105 * modify; if mask is 0x03 and value is 0, the lowest order 2 bits will be
109 uint16_t dbdma_get_chan_status(dbdma_channel_t *chan);
111 uint8_t dbdma_get_device_status(dbdma_channel_t *chan);
112 void dbdma_set_device_status(dbdma_channel_t *chan, uint8_t mask,
116 * Each DBDMA command word has the current channel status register and the
117 * number of residual bytes (requested - actually transferred) written to it
118 * at time of command completion.
121 uint16_t dbdma_get_cmd_status(dbdma_channel_t *chan, int slot);
122 uint16_t dbdma_get_residuals(dbdma_channel_t *chan, int slot);
124 void dbdma_clear_cmd_status(dbdma_channel_t *chan, int slot);
127 * The interrupt/branch/wait selector let you specify a set of values
128 * of the device dependent status bits that will cause intterupt/branch/wait
129 * conditions to be taken if the flags for these are set to one of the
130 * DBDMA_COND_* values.
132 * The condition is considered true if (status & mask) == value.
135 void dbdma_set_interrupt_selector(dbdma_channel_t *chan, uint8_t mask,
137 void dbdma_set_branch_selector(dbdma_channel_t *chan, uint8_t mask,
139 void dbdma_set_wait_selector(dbdma_channel_t *chan, uint8_t mask,
142 void dbdma_insert_command(dbdma_channel_t *chan, int slot, int command,
143 int stream, bus_addr_t data, size_t count, uint8_t interrupt,
144 uint8_t branch, uint8_t wait, uint32_t branch_slot);
146 void dbdma_insert_stop(dbdma_channel_t *chan, int slot);
147 void dbdma_insert_nop(dbdma_channel_t *chan, int slot);
148 void dbdma_insert_branch(dbdma_channel_t *chan, int slot, int to_slot);
150 void dbdma_sync_commands(dbdma_channel_t *chan, bus_dmasync_op_t op);
152 void dbdma_save_state(dbdma_channel_t *chan);
153 void dbdma_restore_state(dbdma_channel_t *chan);
155 #endif /* _MACHINE_DBDMA_H_ */