2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 1999 Luoqi Chen <luoqi@freebsd.org>
5 * Copyright (c) Peter Wemm <peter@netplex.com.au>
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32 #ifndef _MACHINE_PCPU_H_
33 #define _MACHINE_PCPU_H_
35 #include <machine/cpufunc.h>
36 #include <machine/slb.h>
37 #include <machine/tlb.h>
43 #define PCPU_MD_COMMON_FIELDS \
45 struct pmap *pc_curpmap; /* current pmap */ \
46 struct thread *pc_fputhread; /* current fpu user */ \
47 struct thread *pc_vecthread; /* current vec user */ \
48 struct thread *pc_htmthread; /* current htm user */ \
51 volatile int pc_awake; \
52 uint32_t pc_ipimask; \
53 uint32_t pc_flags; /* cpu feature flags */ \
54 register_t pc_tempsave[CPUSAVE_LEN]; \
55 register_t pc_disisave[CPUSAVE_LEN]; \
56 register_t pc_dbsave[CPUSAVE_LEN]; \
58 vm_offset_t pc_qmap_addr;
60 #define PCPU_MD_AIM32_FIELDS \
61 struct pvo_entry *qmap_pvo; \
62 struct mtx qmap_lock; \
65 #define PCPU_MD_AIM64_FIELDS \
67 struct slb **userslb; \
68 register_t slbsave[18]; \
69 uint8_t slbstack[1024]; \
70 struct pvo_entry *qmap_pvo; \
71 struct mtx qmap_lock; \
72 uint64_t opal_hmi_flags; \
76 #define PCPU_MD_AIM_FIELDS PCPU_MD_AIM64_FIELDS
78 #define PCPU_MD_AIM_FIELDS PCPU_MD_AIM32_FIELDS
81 /* CPU feature flags, can be used for cached flow control. */
82 #define PC_FLAG_NOSRS 0x80000000
84 #define BOOKE_CRITSAVE_LEN (CPUSAVE_LEN + 2)
85 #define BOOKE_TLB_MAXNEST 4
86 #define BOOKE_TLB_SAVELEN 16
87 #define BOOKE_TLBSAVE_LEN (BOOKE_TLB_SAVELEN * BOOKE_TLB_MAXNEST)
90 #define BOOKE_PCPU_PAD 901
92 #define BOOKE_PCPU_PAD 365
94 #define PCPU_MD_BOOKE_FIELDS \
95 register_t critsave[BOOKE_CRITSAVE_LEN]; \
96 register_t mchksave[CPUSAVE_LEN]; \
97 register_t tlbsave[BOOKE_TLBSAVE_LEN]; \
98 register_t tlb_level; \
99 uintptr_t *tlb_lock; \
101 char __pad[BOOKE_PCPU_PAD];
103 /* Definitions for register offsets within the exception tmp save areas */
104 #define CPUSAVE_R27 0 /* where r27 gets saved */
105 #define CPUSAVE_R28 1 /* where r28 gets saved */
106 #define CPUSAVE_R29 2 /* where r29 gets saved */
107 #define CPUSAVE_R30 3 /* where r30 gets saved */
108 #define CPUSAVE_R31 4 /* where r31 gets saved */
109 #define CPUSAVE_AIM_DAR 5 /* where SPR_DAR gets saved */
110 #define CPUSAVE_AIM_DSISR 6 /* where SPR_DSISR gets saved */
111 #define CPUSAVE_BOOKE_DEAR 5 /* where SPR_DEAR gets saved */
112 #define CPUSAVE_BOOKE_ESR 6 /* where SPR_ESR gets saved */
113 #define CPUSAVE_SRR0 7 /* where SRR0 gets saved */
114 #define CPUSAVE_SRR1 8 /* where SRR1 gets saved */
115 #define BOOKE_CRITSAVE_SRR0 9 /* where real SRR0 gets saved (critical) */
116 #define BOOKE_CRITSAVE_SRR1 10 /* where real SRR0 gets saved (critical) */
118 /* Book-E TLBSAVE is more elaborate */
119 #define TLBSAVE_BOOKE_LR 0
120 #define TLBSAVE_BOOKE_CR 1
121 #define TLBSAVE_BOOKE_SRR0 2
122 #define TLBSAVE_BOOKE_SRR1 3
123 #define TLBSAVE_BOOKE_R20 4
124 #define TLBSAVE_BOOKE_R21 5
125 #define TLBSAVE_BOOKE_R22 6
126 #define TLBSAVE_BOOKE_R23 7
127 #define TLBSAVE_BOOKE_R24 8
128 #define TLBSAVE_BOOKE_R25 9
129 #define TLBSAVE_BOOKE_R26 10
130 #define TLBSAVE_BOOKE_R27 11
131 #define TLBSAVE_BOOKE_R28 12
132 #define TLBSAVE_BOOKE_R29 13
133 #define TLBSAVE_BOOKE_R30 14
134 #define TLBSAVE_BOOKE_R31 15
136 #define PCPU_MD_FIELDS \
137 PCPU_MD_COMMON_FIELDS \
143 PCPU_MD_BOOKE_FIELDS \
149 #define pcpup (get_pcpu())
151 static __inline __pure2 struct thread *
156 __asm __volatile("mr %0,13" : "=r"(td));
158 __asm __volatile("mr %0,2" : "=r"(td));
162 #define curthread (__curthread())
164 #define PCPU_GET(member) (pcpup->pc_ ## member)
167 * XXX The implementation of this operation should be made atomic
168 * with respect to preemption.
170 #define PCPU_ADD(member, value) (pcpup->pc_ ## member += (value))
171 #define PCPU_INC(member) PCPU_ADD(member, 1)
172 #define PCPU_PTR(member) (&pcpup->pc_ ## member)
173 #define PCPU_SET(member,value) (pcpup->pc_ ## member = (value))
177 #endif /* !_MACHINE_PCPU_H_ */