2 * Copyright (C) 1995, 1996 Wolfgang Solfrank.
3 * Copyright (C) 1995, 1996 TooLs GmbH.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. All advertising materials mentioning features or use of this software
15 * must display the following acknowledgement:
16 * This product includes software developed by TooLs GmbH.
17 * 4. The name of TooLs GmbH may not be used to endorse or promote products
18 * derived from this software without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR
21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
23 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
24 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
25 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
26 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
27 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
28 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
29 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 * $NetBSD: psl.h,v 1.5 2000/11/19 19:52:37 matt Exp $
35 #ifndef _MACHINE_PSL_H_
36 #define _MACHINE_PSL_H_
39 * Machine State Register (MSR) - All cores
41 #define PSL_VEC 0x02000000UL /* AltiVec/SPE vector unit available */
42 #define PSL_VSX 0x00800000UL /* Vector-Scalar unit available */
43 #define PSL_EE 0x00008000UL /* external interrupt enable */
44 #define PSL_PR 0x00004000UL /* privilege mode (1 == user) */
45 #define PSL_FP 0x00002000UL /* floating point enable */
46 #define PSL_ME 0x00001000UL /* machine check enable */
47 #define PSL_FE0 0x00000800UL /* floating point interrupt mode 0 */
48 #define PSL_FE1 0x00000100UL /* floating point interrupt mode 1 */
49 #define PSL_PMM 0x00000004UL /* performance monitor mark */
50 #define PSL_RI 0x00000002UL /* recoverable interrupt */
52 /* Machine State Register - Book-E cores */
54 #define PSL_CM 0x80000000UL /* Computation Mode (64-bit) */
57 #define PSL_GS 0x10000000UL /* Guest state */
58 #define PSL_UCLE 0x04000000UL /* User mode cache lock enable */
59 #define PSL_WE 0x00040000UL /* Wait state enable */
60 #define PSL_CE 0x00020000UL /* Critical interrupt enable */
61 #define PSL_UBLE 0x00000400UL /* BTB lock enable - e500 only */
62 #define PSL_DWE 0x00000400UL /* Debug Wait Enable - 440 only*/
63 #define PSL_DE 0x00000200UL /* Debug interrupt enable */
64 #define PSL_IS 0x00000020UL /* Instruction address space */
65 #define PSL_DS 0x00000010UL /* Data address space */
67 /* Machine State Register (MSR) - AIM cores */
69 #define PSL_SF 0x8000000000000000UL /* 64-bit addressing */
70 #define PSL_HV 0x1000000000000000UL /* hyper-privileged mode */
73 #define PSL_POW 0x00040000UL /* power management */
74 #define PSL_ILE 0x00010000UL /* interrupt endian mode (1 == le) */
75 #define PSL_SE 0x00000400UL /* single-step trace enable */
76 #define PSL_BE 0x00000200UL /* branch trace enable */
77 #define PSL_IP 0x00000040UL /* interrupt prefix - 601 only */
78 #define PSL_IR 0x00000020UL /* instruction address relocation */
79 #define PSL_DR 0x00000010UL /* data address relocation */
80 #define PSL_LE 0x00000001UL /* endian mode (1 == le) */
83 * Floating-point exception modes:
85 #define PSL_FE_DIS 0 /* none */
86 #define PSL_FE_NONREC PSL_FE1 /* imprecise non-recoverable */
87 #define PSL_FE_REC PSL_FE0 /* imprecise recoverable */
88 #define PSL_FE_PREC (PSL_FE0 | PSL_FE1) /* precise */
89 #define PSL_FE_DFLT PSL_FE_DIS /* default == none */
91 #if defined(BOOKE_E500)
92 /* Initial kernel MSR, use IS=1 ad DS=1. */
93 #define PSL_KERNSET_INIT (PSL_IS | PSL_DS)
95 #define PSL_KERNSET (PSL_CM | PSL_CE | PSL_ME | PSL_EE)
97 #define PSL_KERNSET (PSL_CE | PSL_ME | PSL_EE)
99 #define PSL_SRR1_MASK 0x00000000UL /* No mask on Book-E */
100 #elif defined(BOOKE_PPC4XX)
101 #define PSL_KERNSET (PSL_CE | PSL_ME | PSL_EE | PSL_FP)
102 #define PSL_SRR1_MASK 0x00000000UL /* No mask on Book-E */
105 #define PSL_KERNSET (PSL_SF | PSL_EE | PSL_ME | PSL_IR | PSL_DR | PSL_RI)
107 #define PSL_KERNSET (PSL_EE | PSL_ME | PSL_IR | PSL_DR | PSL_RI)
109 #define PSL_SRR1_MASK 0x783f0000UL /* Bits 1-4, 10-15 (ppc32), 33-36, 42-47 (ppc64) */
112 #define PSL_USERSET (PSL_KERNSET | PSL_PR)
113 #define PSL_USERSTATIC (~(PSL_VEC | PSL_FP | PSL_FE0 | PSL_FE1) & ~PSL_SRR1_MASK)
115 #endif /* _MACHINE_PSL_H_ */