2 * SPDX-License-Identifier: BSD-4-Clause
4 * Copyright (C) 1995, 1996 Wolfgang Solfrank.
5 * Copyright (C) 1995, 1996 TooLs GmbH.
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. All advertising materials mentioning features or use of this software
17 * must display the following acknowledgement:
18 * This product includes software developed by TooLs GmbH.
19 * 4. The name of TooLs GmbH may not be used to endorse or promote products
20 * derived from this software without specific prior written permission.
22 * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR
23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
25 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
27 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
28 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
29 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
30 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
31 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 * $NetBSD: psl.h,v 1.5 2000/11/19 19:52:37 matt Exp $
37 #ifndef _MACHINE_PSL_H_
38 #define _MACHINE_PSL_H_
41 * Machine State Register (MSR) - All cores
43 #define PSL_VEC 0x02000000UL /* AltiVec/SPE vector unit available */
44 #define PSL_VSX 0x00800000UL /* Vector-Scalar unit available */
45 #define PSL_EE 0x00008000UL /* external interrupt enable */
46 #define PSL_PR 0x00004000UL /* privilege mode (1 == user) */
47 #define PSL_FP 0x00002000UL /* floating point enable */
48 #define PSL_ME 0x00001000UL /* machine check enable */
49 #define PSL_FE0 0x00000800UL /* floating point interrupt mode 0 */
50 #define PSL_FE1 0x00000100UL /* floating point interrupt mode 1 */
51 #define PSL_PMM 0x00000004UL /* performance monitor mark */
52 #define PSL_RI 0x00000002UL /* recoverable interrupt */
54 /* Machine State Register - Book-E cores */
56 #define PSL_CM 0x80000000UL /* Computation Mode (64-bit) */
59 #define PSL_GS 0x10000000UL /* Guest state */
60 #define PSL_UCLE 0x04000000UL /* User mode cache lock enable */
61 #define PSL_WE 0x00040000UL /* Wait state enable */
62 #define PSL_CE 0x00020000UL /* Critical interrupt enable */
63 #define PSL_UBLE 0x00000400UL /* BTB lock enable - e500 only */
64 #define PSL_DWE 0x00000400UL /* Debug Wait Enable - 440 only*/
65 #define PSL_DE 0x00000200UL /* Debug interrupt enable */
66 #define PSL_IS 0x00000020UL /* Instruction address space */
67 #define PSL_DS 0x00000010UL /* Data address space */
69 /* Machine State Register (MSR) - AIM cores */
71 #define PSL_SF 0x8000000000000000UL /* 64-bit addressing */
72 #define PSL_HV 0x1000000000000000UL /* hyper-privileged mode */
75 #define PSL_POW 0x00040000UL /* power management */
76 #define PSL_ILE 0x00010000UL /* interrupt endian mode (1 == le) */
77 #define PSL_SE 0x00000400UL /* single-step trace enable */
78 #define PSL_BE 0x00000200UL /* branch trace enable */
79 #define PSL_IP 0x00000040UL /* interrupt prefix - 601 only */
80 #define PSL_IR 0x00000020UL /* instruction address relocation */
81 #define PSL_DR 0x00000010UL /* data address relocation */
82 #define PSL_LE 0x00000001UL /* endian mode (1 == le) */
85 * Floating-point exception modes:
87 #define PSL_FE_DIS 0 /* none */
88 #define PSL_FE_NONREC PSL_FE1 /* imprecise non-recoverable */
89 #define PSL_FE_REC PSL_FE0 /* imprecise recoverable */
90 #define PSL_FE_PREC (PSL_FE0 | PSL_FE1) /* precise */
91 #define PSL_FE_DFLT PSL_FE_PREC /* default == precise */
94 extern register_t psl_kernset; /* Default MSR values for kernel */
95 extern register_t psl_userset; /* Default MSR values for userland */
97 extern register_t psl_userset32; /* Default user MSR values for 32-bit */
99 extern register_t psl_userstatic; /* Bits of SRR1 userland may not set */
102 #endif /* _MACHINE_PSL_H_ */