2 * SPDX-License-Identifier: BSD-3-Clause
4 * Copyright (C) 2006-2012 Semihalf.
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8 * modification, are permitted provided that the following conditions
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32 #ifndef _MACHINE_TLB_H_
33 #define _MACHINE_TLB_H_
35 #if defined(BOOKE_E500)
37 /* PowerPC E500 MAS registers */
38 #define MAS0_TLBSEL(x) ((x << 28) & 0x10000000)
39 #define MAS0_ESEL(x) ((x << 16) & 0x003F0000)
41 #define MAS0_TLBSEL1 0x10000000
42 #define MAS0_TLBSEL0 0x00000000
43 #define MAS0_ESEL_TLB1MASK 0x000F0000
44 #define MAS0_ESEL_TLB0MASK 0x00030000
45 #define MAS0_ESEL_SHIFT 16
46 #define MAS0_NV_MASK 0x00000003
47 #define MAS0_NV_SHIFT 0
49 #define MAS1_VALID 0x80000000
50 #define MAS1_IPROT 0x40000000
51 #define MAS1_TID_MASK 0x00FF0000
52 #define MAS1_TID_SHIFT 16
53 #define MAS1_TS_MASK 0x00001000
54 #define MAS1_TS_SHIFT 12
55 #define MAS1_TSIZE_MASK 0x00000F00
56 #define MAS1_TSIZE_SHIFT 8
59 #define TLB_SIZE_16K 2
60 #define TLB_SIZE_64K 3
61 #define TLB_SIZE_256K 4
64 #define TLB_SIZE_16M 7
65 #define TLB_SIZE_64M 8
66 #define TLB_SIZE_256M 9
67 #define TLB_SIZE_1G 10
68 #define TLB_SIZE_4G 11
71 #define MAS2_EPN_MASK 0xFFFFFFFFFFFFF000UL
73 #define MAS2_EPN_MASK 0xFFFFF000
75 #define MAS2_EPN_SHIFT 12
76 #define MAS2_X0 0x00000040
77 #define MAS2_X1 0x00000020
78 #define MAS2_W 0x00000010
79 #define MAS2_I 0x00000008
80 #define MAS2_M 0x00000004
81 #define MAS2_G 0x00000002
82 #define MAS2_E 0x00000001
83 #define MAS2_WIMGE_MASK 0x0000007F
85 #define MAS3_RPN 0xFFFFF000
86 #define MAS3_RPN_SHIFT 12
87 #define MAS3_U0 0x00000200
88 #define MAS3_U1 0x00000100
89 #define MAS3_U2 0x00000080
90 #define MAS3_U3 0x00000040
91 #define MAS3_UX 0x00000020
92 #define MAS3_SX 0x00000010
93 #define MAS3_UW 0x00000008
94 #define MAS3_SW 0x00000004
95 #define MAS3_UR 0x00000002
96 #define MAS3_SR 0x00000001
98 #define MAS4_TLBSELD1 0x10000000
99 #define MAS4_TLBSELD0 0x00000000
100 #define MAS4_TIDSELD_MASK 0x00030000
101 #define MAS4_TIDSELD_SHIFT 16
102 #define MAS4_TSIZED_MASK 0x00000F00
103 #define MAS4_TSIZED_SHIFT 8
104 #define MAS4_X0D 0x00000040
105 #define MAS4_X1D 0x00000020
106 #define MAS4_WD 0x00000010
107 #define MAS4_ID 0x00000008
108 #define MAS4_MD 0x00000004
109 #define MAS4_GD 0x00000002
110 #define MAS4_ED 0x00000001
112 #define MAS6_SPID0_MASK 0x00FF0000
113 #define MAS6_SPID0_SHIFT 16
114 #define MAS6_SAS 0x00000001
116 #define MAS7_RPN 0x0000000F
118 #define MAS1_GETTID(mas1) (((mas1) & MAS1_TID_MASK) >> MAS1_TID_SHIFT)
120 #define MAS2_TLB0_ENTRY_IDX_MASK 0x0007f000
121 #define MAS2_TLB0_ENTRY_IDX_SHIFT 12
124 * Maximum number of TLB1 entries used for a permanent mapping of kernel
125 * region (kernel image plus statically allocated data).
127 #define KERNEL_REGION_MAX_TLB_ENTRIES 4
130 * Use MAS2_X0 to mark entries which will be copied
131 * to AP CPUs during SMP bootstrap. As result entries
132 * marked with _TLB_ENTRY_SHARED will be shared by all CPUs.
134 #define _TLB_ENTRY_SHARED (MAS2_X0) /* XXX under SMP? */
135 #define _TLB_ENTRY_IO (MAS2_I | MAS2_G)
136 #define _TLB_ENTRY_MEM (MAS2_M)
138 #define TLB1_MAX_ENTRIES 64
141 typedef struct tlb_entry {
155 void tlb1_inval_entry(unsigned int);
156 void tlb1_init(void);
159 #endif /* BOOKE_E500 */
161 #define TID_KERNEL 0 /* TLB TID to use for kernel (shared) translations */
162 #define TID_KRESERVED 1 /* Number of TIDs reserved for kernel */
163 #define TID_URESERVED 0 /* Number of TIDs reserved for user */
164 #define TID_MIN (TID_KRESERVED + TID_URESERVED)
168 #define TLB_UNLOCKED 0
172 typedef int tlbtid_t;
176 void tlb_lock(uintptr_t *);
177 void tlb_unlock(uintptr_t *);
178 void tlb1_ap_prep(void);
179 int tlb1_set_entry(vm_offset_t, vm_paddr_t, vm_size_t, uint32_t);
183 #endif /* _MACHINE_TLB_H_ */