2 * Copyright (C) 2006-2012 Semihalf.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
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14 * derived from this software without specific prior written permission.
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30 #ifndef _MACHINE_TLB_H_
31 #define _MACHINE_TLB_H_
33 #if defined(BOOKE_E500)
35 /* PowerPC E500 MAS registers */
36 #define MAS0_TLBSEL(x) ((x << 28) & 0x10000000)
37 #define MAS0_ESEL(x) ((x << 16) & 0x003F0000)
39 #define MAS0_TLBSEL1 0x10000000
40 #define MAS0_TLBSEL0 0x00000000
41 #define MAS0_ESEL_TLB1MASK 0x000F0000
42 #define MAS0_ESEL_TLB0MASK 0x00030000
43 #define MAS0_ESEL_SHIFT 16
44 #define MAS0_NV_MASK 0x00000003
45 #define MAS0_NV_SHIFT 0
47 #define MAS1_VALID 0x80000000
48 #define MAS1_IPROT 0x40000000
49 #define MAS1_TID_MASK 0x00FF0000
50 #define MAS1_TID_SHIFT 16
51 #define MAS1_TS_MASK 0x00001000
52 #define MAS1_TS_SHIFT 12
53 #define MAS1_TSIZE_MASK 0x00000F00
54 #define MAS1_TSIZE_SHIFT 8
57 #define TLB_SIZE_16K 2
58 #define TLB_SIZE_64K 3
59 #define TLB_SIZE_256K 4
62 #define TLB_SIZE_16M 7
63 #define TLB_SIZE_64M 8
64 #define TLB_SIZE_256M 9
65 #define TLB_SIZE_1G 10
66 #define TLB_SIZE_4G 11
69 #define MAS2_EPN_MASK 0xFFFFFFFFFFFFF000UL
71 #define MAS2_EPN_MASK 0xFFFFF000
73 #define MAS2_EPN_SHIFT 12
74 #define MAS2_X0 0x00000040
75 #define MAS2_X1 0x00000020
76 #define MAS2_W 0x00000010
77 #define MAS2_I 0x00000008
78 #define MAS2_M 0x00000004
79 #define MAS2_G 0x00000002
80 #define MAS2_E 0x00000001
81 #define MAS2_WIMGE_MASK 0x0000007F
83 #define MAS3_RPN 0xFFFFF000
84 #define MAS3_RPN_SHIFT 12
85 #define MAS3_U0 0x00000200
86 #define MAS3_U1 0x00000100
87 #define MAS3_U2 0x00000080
88 #define MAS3_U3 0x00000040
89 #define MAS3_UX 0x00000020
90 #define MAS3_SX 0x00000010
91 #define MAS3_UW 0x00000008
92 #define MAS3_SW 0x00000004
93 #define MAS3_UR 0x00000002
94 #define MAS3_SR 0x00000001
96 #define MAS4_TLBSELD1 0x10000000
97 #define MAS4_TLBSELD0 0x00000000
98 #define MAS4_TIDSELD_MASK 0x00030000
99 #define MAS4_TIDSELD_SHIFT 16
100 #define MAS4_TSIZED_MASK 0x00000F00
101 #define MAS4_TSIZED_SHIFT 8
102 #define MAS4_X0D 0x00000040
103 #define MAS4_X1D 0x00000020
104 #define MAS4_WD 0x00000010
105 #define MAS4_ID 0x00000008
106 #define MAS4_MD 0x00000004
107 #define MAS4_GD 0x00000002
108 #define MAS4_ED 0x00000001
110 #define MAS6_SPID0_MASK 0x00FF0000
111 #define MAS6_SPID0_SHIFT 16
112 #define MAS6_SAS 0x00000001
114 #define MAS7_RPN 0x0000000F
116 #define MAS1_GETTID(mas1) (((mas1) & MAS1_TID_MASK) >> MAS1_TID_SHIFT)
118 #define MAS2_TLB0_ENTRY_IDX_MASK 0x0007f000
119 #define MAS2_TLB0_ENTRY_IDX_SHIFT 12
122 * Maximum number of TLB1 entries used for a permanent mapping of kernel
123 * region (kernel image plus statically allocated data).
125 #define KERNEL_REGION_MAX_TLB_ENTRIES 4
128 * Use MAS2_X0 to mark entries which will be copied
129 * to AP CPUs during SMP bootstrap. As result entries
130 * marked with _TLB_ENTRY_SHARED will be shared by all CPUs.
132 #define _TLB_ENTRY_SHARED (MAS2_X0) /* XXX under SMP? */
133 #define _TLB_ENTRY_IO (MAS2_I | MAS2_G)
134 #define _TLB_ENTRY_MEM (MAS2_M)
136 #define TLB1_MAX_ENTRIES 64
139 typedef struct tlb_entry {
153 void tlb0_print_tlbentries(void);
155 void tlb1_inval_entry(unsigned int);
156 void tlb1_init(void);
157 void tlb1_print_entries(void);
158 void tlb1_print_tlbentries(void);
161 #elif defined(BOOKE_PPC4XX)
168 /* Page identification fields */
169 #define TLB_EPN_MASK (0xFFFFFC00 >> 0)
170 #define TLB_VALID (0x80000000 >> 22)
171 #define TLB_TS (0x80000000 >> 23)
172 #define TLB_SIZE_1K (0x00000000 >> 24)
173 #define TLB_SIZE_MASK (0xF0000000 >> 24)
175 /* Translation fields */
176 #define TLB_RPN_MASK (0xFFFFFC00 >> 0)
177 #define TLB_ERPN_MASK (0xF0000000 >> 28)
179 /* Storage attribute and access control fields */
180 #define TLB_WL1 (0x80000000 >> 11)
181 #define TLB_IL1I (0x80000000 >> 12)
182 #define TLB_IL1D (0x80000000 >> 13)
183 #define TLB_IL2I (0x80000000 >> 14)
184 #define TLB_IL2D (0x80000000 >> 15)
185 #define TLB_U0 (0x80000000 >> 16)
186 #define TLB_U1 (0x80000000 >> 17)
187 #define TLB_U2 (0x80000000 >> 18)
188 #define TLB_U3 (0x80000000 >> 19)
189 #define TLB_W (0x80000000 >> 20)
190 #define TLB_I (0x80000000 >> 21)
191 #define TLB_M (0x80000000 >> 22)
192 #define TLB_G (0x80000000 >> 23)
193 #define TLB_E (0x80000000 >> 24)
194 #define TLB_UX (0x80000000 >> 26)
195 #define TLB_UW (0x80000000 >> 27)
196 #define TLB_UR (0x80000000 >> 28)
197 #define TLB_SX (0x80000000 >> 29)
198 #define TLB_SW (0x80000000 >> 30)
199 #define TLB_SR (0x80000000 >> 31)
202 #define TLB_SIZE_4K (0x10000000 >> 24)
203 #define TLB_SIZE_16K (0x20000000 >> 24)
204 #define TLB_SIZE_64K (0x30000000 >> 24)
205 #define TLB_SIZE_256K (0x40000000 >> 24)
206 #define TLB_SIZE_1M (0x50000000 >> 24)
207 #define TLB_SIZE_16M (0x70000000 >> 24)
208 #define TLB_SIZE_256M (0x90000000 >> 24)
209 #define TLB_SIZE_1G (0xA0000000 >> 24)
211 #endif /* BOOKE_E500 */
213 #define TID_KERNEL 0 /* TLB TID to use for kernel (shared) translations */
214 #define TID_KRESERVED 1 /* Number of TIDs reserved for kernel */
215 #define TID_URESERVED 0 /* Number of TIDs reserved for user */
216 #define TID_MIN (TID_KRESERVED + TID_URESERVED)
220 #define TLB_UNLOCKED 0
224 typedef int tlbtid_t;
228 void tlb_lock(uintptr_t *);
229 void tlb_unlock(uintptr_t *);
230 void tlb1_ap_prep(void);
231 int tlb1_set_entry(vm_offset_t, vm_paddr_t, vm_size_t, uint32_t);
235 #endif /* _MACHINE_TLB_H_ */