2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2009 Marcel Moolenaar
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
20 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
21 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
22 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
23 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 #include <sys/cdefs.h>
29 __FBSDID("$FreeBSD$");
31 #include <sys/param.h>
32 #include <sys/systm.h>
34 #include <sys/cpuset.h>
35 #include <sys/kernel.h>
36 #include <sys/module.h>
39 #include <machine/bus.h>
40 #include <machine/intr_machdep.h>
41 #include <machine/pio.h>
43 #include <powerpc/mpc85xx/mpc85xx.h>
45 #include <dev/ic/i8259.h>
47 #include <isa/isareg.h>
48 #include <isa/isavar.h>
52 #define ATPIC_MASTER 0
58 /* I/O port resources for master & slave. */
59 struct resource *sc_res[2];
62 /* Our "routing" interrupt */
63 struct resource *sc_ires;
71 static int atpic_isa_attach(device_t);
72 static void atpic_isa_identify(driver_t *, device_t);
73 static int atpic_isa_probe(device_t);
75 static void atpic_config(device_t, u_int, enum intr_trigger,
77 static void atpic_dispatch(device_t, struct trapframe *);
78 static void atpic_enable(device_t, u_int, u_int);
79 static void atpic_eoi(device_t, u_int);
80 static void atpic_ipi(device_t, u_int);
81 static void atpic_mask(device_t, u_int);
82 static void atpic_unmask(device_t, u_int);
84 static void atpic_ofw_translate_code(device_t, u_int irq, int code,
85 enum intr_trigger *trig, enum intr_polarity *pol);
87 static device_method_t atpic_isa_methods[] = {
88 /* Device interface */
89 DEVMETHOD(device_identify, atpic_isa_identify),
90 DEVMETHOD(device_probe, atpic_isa_probe),
91 DEVMETHOD(device_attach, atpic_isa_attach),
94 DEVMETHOD(pic_config, atpic_config),
95 DEVMETHOD(pic_dispatch, atpic_dispatch),
96 DEVMETHOD(pic_enable, atpic_enable),
97 DEVMETHOD(pic_eoi, atpic_eoi),
98 DEVMETHOD(pic_ipi, atpic_ipi),
99 DEVMETHOD(pic_mask, atpic_mask),
100 DEVMETHOD(pic_unmask, atpic_unmask),
102 DEVMETHOD(pic_translate_code, atpic_ofw_translate_code),
107 static driver_t atpic_isa_driver = {
110 sizeof(struct atpic_softc)
113 static devclass_t atpic_devclass;
115 static struct isa_pnp_id atpic_ids[] = {
116 { 0x0000d041 /* PNP0000 */, "AT interrupt controller" },
120 DRIVER_MODULE(atpic, isa, atpic_isa_driver, atpic_devclass, 0, 0);
121 ISA_PNP_INFO(atpic_ids);
123 static __inline uint8_t
124 atpic_read(struct atpic_softc *sc, int icu, int ofs)
128 val = bus_read_1(sc->sc_res[icu], ofs);
133 atpic_write(struct atpic_softc *sc, int icu, int ofs, uint8_t val)
136 bus_write_1(sc->sc_res[icu], ofs, val);
137 bus_barrier(sc->sc_res[icu], ofs, 2 - ofs,
138 BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE);
142 atpic_intr(void *arg)
145 atpic_dispatch(arg, NULL);
149 atpic_isa_identify(driver_t *drv, device_t parent)
153 child = BUS_ADD_CHILD(parent, ISA_ORDER_SENSITIVE, drv->name, -1);
154 device_set_driver(child, drv);
155 isa_set_logicalid(child, atpic_ids[0].ip_id);
156 isa_set_vendorid(child, atpic_ids[0].ip_id);
158 bus_set_resource(child, SYS_RES_IOPORT, ATPIC_MASTER, IO_ICU1, 2);
159 bus_set_resource(child, SYS_RES_IOPORT, ATPIC_SLAVE, IO_ICU2, 2);
161 /* ISA interrupts are routed through external interrupt 0. */
162 bus_set_resource(child, SYS_RES_IRQ, 0, 16, 1);
166 atpic_isa_probe(device_t dev)
170 res = ISA_PNP_PROBE(device_get_parent(dev), dev, atpic_ids);
174 device_set_desc(dev, "PC/AT compatible PIC");
179 atpic_init(struct atpic_softc *sc, int icu)
182 sc->sc_mask[icu] = 0xff - ((icu == ATPIC_MASTER) ? 4 : 0);
184 atpic_write(sc, icu, 0, ICW1_RESET | ICW1_IC4);
185 atpic_write(sc, icu, 1, (icu == ATPIC_SLAVE) ? 8 : 0);
186 atpic_write(sc, icu, 1, (icu == ATPIC_SLAVE) ? 2 : 4);
187 atpic_write(sc, icu, 1, ICW4_8086);
188 atpic_write(sc, icu, 1, sc->sc_mask[icu]);
189 atpic_write(sc, icu, 0, OCW3_SEL | OCW3_RR);
193 atpic_isa_attach(device_t dev)
195 struct atpic_softc *sc;
198 sc = device_get_softc(dev);
203 sc->sc_rid[ATPIC_MASTER] = 0;
204 sc->sc_res[ATPIC_MASTER] = bus_alloc_resource_any(dev, SYS_RES_IOPORT,
205 &sc->sc_rid[ATPIC_MASTER], RF_ACTIVE);
206 if (sc->sc_res[ATPIC_MASTER] == NULL)
209 sc->sc_rid[ATPIC_SLAVE] = 1;
210 sc->sc_res[ATPIC_SLAVE] = bus_alloc_resource_any(dev, SYS_RES_IOPORT,
211 &sc->sc_rid[ATPIC_SLAVE], RF_ACTIVE);
212 if (sc->sc_res[ATPIC_SLAVE] == NULL)
216 sc->sc_ires = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->sc_irid,
218 if (sc->sc_ires == NULL)
221 error = bus_setup_intr(dev, sc->sc_ires, INTR_TYPE_MISC | INTR_MPSAFE,
222 NULL, atpic_intr, dev, &sc->sc_icookie);
226 atpic_init(sc, ATPIC_SLAVE);
227 atpic_init(sc, ATPIC_MASTER);
229 powerpc_register_pic(dev, 0, 16, 0, TRUE);
233 if (sc->sc_ires != NULL)
234 bus_release_resource(dev, SYS_RES_IRQ, sc->sc_irid,
236 if (sc->sc_res[ATPIC_SLAVE] != NULL)
237 bus_release_resource(dev, SYS_RES_IOPORT,
238 sc->sc_rid[ATPIC_SLAVE], sc->sc_res[ATPIC_SLAVE]);
239 if (sc->sc_res[ATPIC_MASTER] != NULL)
240 bus_release_resource(dev, SYS_RES_IOPORT,
241 sc->sc_rid[ATPIC_MASTER], sc->sc_res[ATPIC_MASTER]);
250 atpic_config(device_t dev, u_int irq, enum intr_trigger trig,
251 enum intr_polarity pol)
256 atpic_dispatch(device_t dev, struct trapframe *tf)
258 struct atpic_softc *sc;
261 sc = device_get_softc(dev);
262 atpic_write(sc, ATPIC_MASTER, 0, OCW3_SEL | OCW3_P);
263 irq = atpic_read(sc, ATPIC_MASTER, 0);
264 atpic_write(sc, ATPIC_MASTER, 0, OCW3_SEL | OCW3_RR);
265 if ((irq & 0x80) == 0)
269 atpic_write(sc, ATPIC_SLAVE, 0, OCW3_SEL | OCW3_P);
270 irq = atpic_read(sc, ATPIC_SLAVE, 0) + 8;
271 atpic_write(sc, ATPIC_SLAVE, 0, OCW3_SEL | OCW3_RR);
272 if ((irq & 0x80) == 0)
276 powerpc_dispatch_intr(sc->sc_vector[irq & 0x0f], tf);
280 atpic_enable(device_t dev, u_int irq, u_int vector)
282 struct atpic_softc *sc;
284 sc = device_get_softc(dev);
285 sc->sc_vector[irq] = vector;
286 atpic_unmask(dev, irq);
290 atpic_eoi(device_t dev, u_int irq)
292 struct atpic_softc *sc;
294 sc = device_get_softc(dev);
296 atpic_write(sc, ATPIC_SLAVE, 0, OCW2_EOI);
297 atpic_write(sc, ATPIC_MASTER, 0, OCW2_EOI);
301 atpic_ipi(device_t dev, u_int cpu)
303 /* No SMP support. */
307 atpic_mask(device_t dev, u_int irq)
309 struct atpic_softc *sc;
311 sc = device_get_softc(dev);
313 sc->sc_mask[ATPIC_SLAVE] |= 1 << (irq - 8);
314 atpic_write(sc, ATPIC_SLAVE, 1, sc->sc_mask[ATPIC_SLAVE]);
316 sc->sc_mask[ATPIC_MASTER] |= 1 << irq;
317 atpic_write(sc, ATPIC_MASTER, 1, sc->sc_mask[ATPIC_MASTER]);
322 atpic_unmask(device_t dev, u_int irq)
324 struct atpic_softc *sc;
326 sc = device_get_softc(dev);
328 sc->sc_mask[ATPIC_SLAVE] &= ~(1 << (irq - 8));
329 atpic_write(sc, ATPIC_SLAVE, 1, sc->sc_mask[ATPIC_SLAVE]);
331 sc->sc_mask[ATPIC_MASTER] &= ~(1 << irq);
332 atpic_write(sc, ATPIC_MASTER, 1, sc->sc_mask[ATPIC_MASTER]);
337 atpic_ofw_translate_code(device_t dev, u_int irq, int code,
338 enum intr_trigger *trig, enum intr_polarity *pol)
343 *trig = INTR_TRIGGER_LEVEL;
344 *pol = INTR_POLARITY_LOW;
348 *trig = INTR_TRIGGER_LEVEL;
349 *pol = INTR_POLARITY_HIGH;
353 *trig = INTR_TRIGGER_EDGE;
354 *pol = INTR_POLARITY_LOW;
358 *trig = INTR_TRIGGER_EDGE;
359 *pol = INTR_POLARITY_HIGH;
362 *trig = INTR_TRIGGER_CONFORM;
363 *pol = INTR_POLARITY_CONFORM;