2 * Copyright (c) 2009 Marcel Moolenaar
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
14 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
15 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
16 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
17 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
18 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
19 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
20 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
21 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 #include <sys/cdefs.h>
27 __FBSDID("$FreeBSD$");
29 #include <sys/param.h>
30 #include <sys/systm.h>
32 #include <sys/cpuset.h>
33 #include <sys/kernel.h>
34 #include <sys/module.h>
37 #include <machine/bus.h>
38 #include <machine/intr_machdep.h>
39 #include <machine/pio.h>
41 #include <powerpc/mpc85xx/mpc85xx.h>
43 #include <dev/ic/i8259.h>
45 #include <isa/isareg.h>
46 #include <isa/isavar.h>
50 #define ATPIC_MASTER 0
56 /* I/O port resources for master & slave. */
57 struct resource *sc_res[2];
60 /* Our "routing" interrupt */
61 struct resource *sc_ires;
69 static int atpic_isa_attach(device_t);
70 static void atpic_isa_identify(driver_t *, device_t);
71 static int atpic_isa_probe(device_t);
73 static void atpic_config(device_t, u_int, enum intr_trigger,
75 static void atpic_dispatch(device_t, struct trapframe *);
76 static void atpic_enable(device_t, u_int, u_int);
77 static void atpic_eoi(device_t, u_int);
78 static void atpic_ipi(device_t, u_int);
79 static void atpic_mask(device_t, u_int);
80 static void atpic_unmask(device_t, u_int);
82 static device_method_t atpic_isa_methods[] = {
83 /* Device interface */
84 DEVMETHOD(device_identify, atpic_isa_identify),
85 DEVMETHOD(device_probe, atpic_isa_probe),
86 DEVMETHOD(device_attach, atpic_isa_attach),
89 DEVMETHOD(pic_config, atpic_config),
90 DEVMETHOD(pic_dispatch, atpic_dispatch),
91 DEVMETHOD(pic_enable, atpic_enable),
92 DEVMETHOD(pic_eoi, atpic_eoi),
93 DEVMETHOD(pic_ipi, atpic_ipi),
94 DEVMETHOD(pic_mask, atpic_mask),
95 DEVMETHOD(pic_unmask, atpic_unmask),
100 static driver_t atpic_isa_driver = {
103 sizeof(struct atpic_softc)
106 static devclass_t atpic_devclass;
108 DRIVER_MODULE(atpic, isa, atpic_isa_driver, atpic_devclass, 0, 0);
110 static struct isa_pnp_id atpic_ids[] = {
111 { 0x0000d041 /* PNP0000 */, "AT interrupt controller" },
115 static __inline uint8_t
116 atpic_read(struct atpic_softc *sc, int icu, int ofs)
120 val = bus_read_1(sc->sc_res[icu], ofs);
125 atpic_write(struct atpic_softc *sc, int icu, int ofs, uint8_t val)
128 bus_write_1(sc->sc_res[icu], ofs, val);
129 bus_barrier(sc->sc_res[icu], ofs, 2 - ofs,
130 BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE);
134 atpic_intr(void *arg)
137 atpic_dispatch(arg, NULL);
141 atpic_isa_identify(driver_t *drv, device_t parent)
145 child = BUS_ADD_CHILD(parent, ISA_ORDER_SENSITIVE, drv->name, -1);
146 device_set_driver(child, drv);
147 isa_set_logicalid(child, atpic_ids[0].ip_id);
148 isa_set_vendorid(child, atpic_ids[0].ip_id);
150 bus_set_resource(child, SYS_RES_IOPORT, ATPIC_MASTER, IO_ICU1, 2);
151 bus_set_resource(child, SYS_RES_IOPORT, ATPIC_SLAVE, IO_ICU2, 2);
153 /* ISA interrupts are routed through external interrupt 0. */
154 bus_set_resource(child, SYS_RES_IRQ, 0, 16, 1);
158 atpic_isa_probe(device_t dev)
162 res = ISA_PNP_PROBE(device_get_parent(dev), dev, atpic_ids);
166 device_set_desc(dev, "PC/AT compatible PIC");
171 atpic_init(struct atpic_softc *sc, int icu)
174 sc->sc_mask[icu] = 0xff - ((icu == ATPIC_MASTER) ? 4 : 0);
176 atpic_write(sc, icu, 0, ICW1_RESET | ICW1_IC4);
177 atpic_write(sc, icu, 1, (icu == ATPIC_SLAVE) ? 8 : 0);
178 atpic_write(sc, icu, 1, (icu == ATPIC_SLAVE) ? 2 : 4);
179 atpic_write(sc, icu, 1, ICW4_8086);
180 atpic_write(sc, icu, 1, sc->sc_mask[icu]);
181 atpic_write(sc, icu, 0, OCW3_SEL | OCW3_RR);
185 atpic_isa_attach(device_t dev)
187 struct atpic_softc *sc;
190 sc = device_get_softc(dev);
195 sc->sc_rid[ATPIC_MASTER] = 0;
196 sc->sc_res[ATPIC_MASTER] = bus_alloc_resource_any(dev, SYS_RES_IOPORT,
197 &sc->sc_rid[ATPIC_MASTER], RF_ACTIVE);
198 if (sc->sc_res[ATPIC_MASTER] == NULL)
201 sc->sc_rid[ATPIC_SLAVE] = 1;
202 sc->sc_res[ATPIC_SLAVE] = bus_alloc_resource_any(dev, SYS_RES_IOPORT,
203 &sc->sc_rid[ATPIC_SLAVE], RF_ACTIVE);
204 if (sc->sc_res[ATPIC_SLAVE] == NULL)
208 sc->sc_ires = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->sc_irid,
210 if (sc->sc_ires == NULL)
213 error = bus_setup_intr(dev, sc->sc_ires, INTR_TYPE_MISC | INTR_MPSAFE,
214 NULL, atpic_intr, dev, &sc->sc_icookie);
218 atpic_init(sc, ATPIC_SLAVE);
219 atpic_init(sc, ATPIC_MASTER);
221 powerpc_register_pic(dev, 0, 16, 0, TRUE);
225 if (sc->sc_ires != NULL)
226 bus_release_resource(dev, SYS_RES_IRQ, sc->sc_irid,
228 if (sc->sc_res[ATPIC_SLAVE] != NULL)
229 bus_release_resource(dev, SYS_RES_IOPORT,
230 sc->sc_rid[ATPIC_SLAVE], sc->sc_res[ATPIC_SLAVE]);
231 if (sc->sc_res[ATPIC_MASTER] != NULL)
232 bus_release_resource(dev, SYS_RES_IOPORT,
233 sc->sc_rid[ATPIC_MASTER], sc->sc_res[ATPIC_MASTER]);
243 atpic_config(device_t dev, u_int irq, enum intr_trigger trig,
244 enum intr_polarity pol)
249 atpic_dispatch(device_t dev, struct trapframe *tf)
251 struct atpic_softc *sc;
254 sc = device_get_softc(dev);
255 atpic_write(sc, ATPIC_MASTER, 0, OCW3_SEL | OCW3_P);
256 irq = atpic_read(sc, ATPIC_MASTER, 0);
257 atpic_write(sc, ATPIC_MASTER, 0, OCW3_SEL | OCW3_RR);
258 if ((irq & 0x80) == 0)
262 atpic_write(sc, ATPIC_SLAVE, 0, OCW3_SEL | OCW3_P);
263 irq = atpic_read(sc, ATPIC_SLAVE, 0) + 8;
264 atpic_write(sc, ATPIC_SLAVE, 0, OCW3_SEL | OCW3_RR);
265 if ((irq & 0x80) == 0)
269 powerpc_dispatch_intr(sc->sc_vector[irq & 0x0f], tf);
273 atpic_enable(device_t dev, u_int irq, u_int vector)
275 struct atpic_softc *sc;
277 sc = device_get_softc(dev);
278 sc->sc_vector[irq] = vector;
279 atpic_unmask(dev, irq);
283 atpic_eoi(device_t dev, u_int irq)
285 struct atpic_softc *sc;
287 sc = device_get_softc(dev);
289 atpic_write(sc, ATPIC_SLAVE, 0, OCW2_EOI);
290 atpic_write(sc, ATPIC_MASTER, 0, OCW2_EOI);
294 atpic_ipi(device_t dev, u_int cpu)
296 /* No SMP support. */
300 atpic_mask(device_t dev, u_int irq)
302 struct atpic_softc *sc;
304 sc = device_get_softc(dev);
306 sc->sc_mask[ATPIC_SLAVE] |= 1 << (irq - 8);
307 atpic_write(sc, ATPIC_SLAVE, 1, sc->sc_mask[ATPIC_SLAVE]);
309 sc->sc_mask[ATPIC_MASTER] |= 1 << irq;
310 atpic_write(sc, ATPIC_MASTER, 1, sc->sc_mask[ATPIC_MASTER]);
315 atpic_unmask(device_t dev, u_int irq)
317 struct atpic_softc *sc;
319 sc = device_get_softc(dev);
321 sc->sc_mask[ATPIC_SLAVE] &= ~(1 << (irq - 8));
322 atpic_write(sc, ATPIC_SLAVE, 1, sc->sc_mask[ATPIC_SLAVE]);
324 sc->sc_mask[ATPIC_MASTER] &= ~(1 << irq);
325 atpic_write(sc, ATPIC_MASTER, 1, sc->sc_mask[ATPIC_MASTER]);