2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (C) 2008 Semihalf, Rafal Jaworowski
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 #include <sys/cdefs.h>
30 #include "opt_platform.h"
31 #include <sys/param.h>
32 #include <sys/systm.h>
34 #include <sys/mutex.h>
35 #include <sys/reboot.h>
39 #include <vm/vm_param.h>
42 #include <machine/cpu.h>
43 #include <machine/cpufunc.h>
44 #include <machine/machdep.h>
45 #include <machine/pio.h>
46 #include <machine/spr.h>
48 #include <dev/fdt/fdt_common.h>
50 #include <dev/fdt/fdt_common.h>
51 #include <dev/ofw/ofw_bus.h>
52 #include <dev/ofw/ofw_bus_subr.h>
53 #include <dev/ofw/openfirm.h>
55 #include <powerpc/mpc85xx/mpc85xx.h>
58 * MPC85xx system specific routines
62 ccsr_read4(uintptr_t addr)
64 volatile uint32_t *ptr = (void *)addr;
70 ccsr_write4(uintptr_t addr, uint32_t val)
72 volatile uint32_t *ptr = (void *)addr;
84 ver = SVR_VER(mfspr(SPR_SVR));
112 law_write(uint32_t n, uint64_t bar, uint32_t sr)
115 if (mpc85xx_is_qoriq()) {
116 ccsr_write4(OCP85XX_LAWBARH(n), bar >> 32);
117 ccsr_write4(OCP85XX_LAWBARL(n), bar);
118 ccsr_write4(OCP85XX_LAWSR_QORIQ(n), sr);
119 ccsr_read4(OCP85XX_LAWSR_QORIQ(n));
121 ccsr_write4(OCP85XX_LAWBAR(n), bar >> 12);
122 ccsr_write4(OCP85XX_LAWSR_85XX(n), sr);
123 ccsr_read4(OCP85XX_LAWSR_85XX(n));
127 * The last write to LAWAR should be followed by a read
128 * of LAWAR before any device try to use any of windows.
129 * What more the read of LAWAR should be followed by isync
137 law_read(uint32_t n, uint64_t *bar, uint32_t *sr)
140 if (mpc85xx_is_qoriq()) {
141 *bar = (uint64_t)ccsr_read4(OCP85XX_LAWBARH(n)) << 32 |
142 ccsr_read4(OCP85XX_LAWBARL(n));
143 *sr = ccsr_read4(OCP85XX_LAWSR_QORIQ(n));
145 *bar = (uint64_t)ccsr_read4(OCP85XX_LAWBAR(n)) << 12;
146 *sr = ccsr_read4(OCP85XX_LAWSR_85XX(n));
157 law_max = law_getmax();
159 for (i = 0; i < law_max; i++) {
160 law_read(i, &bar, &sr);
161 if ((sr & 0x80000000) == 0)
168 #define _LAW_SR(trgt,size) (0x80000000 | (trgt << 20) | \
169 (flsl(size + (size - 1)) - 2))
172 law_enable(int trgt, uint64_t bar, uint32_t size)
181 law_max = law_getmax();
182 sr = _LAW_SR(trgt, size);
184 /* Bail if already programmed. */
185 for (i = 0; i < law_max; i++) {
186 law_read(i, &bar_tmp, &sr_tmp);
187 if (sr == sr_tmp && bar == bar_tmp)
191 /* Find an unused access window. */
197 law_write(i, bar, sr);
202 law_disable(int trgt, uint64_t bar, uint32_t size)
208 law_max = law_getmax();
209 sr = _LAW_SR(trgt, size);
211 /* Find and disable requested LAW. */
212 for (i = 0; i < law_max; i++) {
213 law_read(i, &bar_tmp, &sr_tmp);
214 if (sr == sr_tmp && bar == bar_tmp) {
224 law_pci_target(struct resource *res, int *trgt_mem, int *trgt_io)
230 ver = SVR_VER(mfspr(SPR_SVR));
232 start = rman_get_start(res) & 0xf000;
247 if (ver == SVR_MPC8548E || ver == SVR_MPC8548)
254 if (ver == SVR_MPC8548E || ver == SVR_MPC8548)
273 /* Flash invalidate the CPC and clear all the locks */
274 ccsr_write4(OCP85XX_CPC_CSR0, OCP85XX_CPC_CSR0_FI |
275 OCP85XX_CPC_CSR0_LFC);
276 while (ccsr_read4(OCP85XX_CPC_CSR0) & (OCP85XX_CPC_CSR0_FI |
277 OCP85XX_CPC_CSR0_LFC))
285 ccsr_write4(OCP85XX_CPC_CSR0, OCP85XX_CPC_CSR0_CE |
286 OCP85XX_CPC_CSR0_PE);
287 /* Read back to sync write */
288 ccsr_read4(OCP85XX_CPC_CSR0);
292 mpc85xx_enable_l3_cache(void)
294 uint32_t csr, size, ver;
296 /* Enable L3 CoreNet Platform Cache (CPC) */
297 ver = SVR_VER(mfspr(SPR_SVR));
298 if (ver == SVR_P2041 || ver == SVR_P2041E || ver == SVR_P3041 ||
299 ver == SVR_P3041E || ver == SVR_P5020 || ver == SVR_P5020E) {
300 csr = ccsr_read4(OCP85XX_CPC_CSR0);
301 if ((csr & OCP85XX_CPC_CSR0_CE) == 0) {
306 csr = ccsr_read4(OCP85XX_CPC_CSR0);
307 if ((boothowto & RB_VERBOSE) != 0 ||
308 (csr & OCP85XX_CPC_CSR0_CE) == 0) {
309 size = OCP85XX_CPC_CFG0_SZ_K(ccsr_read4(OCP85XX_CPC_CFG0));
310 printf("L3 Corenet Platform Cache: %d KB %sabled\n",
311 size, (csr & OCP85XX_CPC_CSR0_CE) == 0 ?
318 mpc85xx_is_qoriq(void)
320 uint16_t pvr = mfpvr() >> 16;
322 /* QorIQ register set is only in e500mc and derivative core based SoCs. */
323 if (pvr == FSL_E500mc || pvr == FSL_E5500 || pvr == FSL_E6500)
330 mpc85xx_get_platform_clock(void)
333 static uint32_t freq;
338 soc = OF_finddevice("/soc");
340 /* freq isn't modified on error. */
341 OF_getencprop(soc, "bus-frequency", (void *)&freq, sizeof(freq));
347 mpc85xx_get_system_clock(void)
351 freq = mpc85xx_get_platform_clock();