2 * Copyright (C) 2008 Semihalf, Rafal Jaworowski
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
30 #include "opt_platform.h"
31 #include <sys/param.h>
32 #include <sys/systm.h>
34 #include <sys/mutex.h>
35 #include <sys/reboot.h>
39 #include <vm/vm_param.h>
42 #include <machine/cpu.h>
43 #include <machine/cpufunc.h>
44 #include <machine/machdep.h>
45 #include <machine/pio.h>
46 #include <machine/spr.h>
48 #include <dev/fdt/fdt_common.h>
50 #include <dev/fdt/fdt_common.h>
51 #include <dev/ofw/ofw_bus.h>
52 #include <dev/ofw/ofw_bus_subr.h>
53 #include <dev/ofw/openfirm.h>
55 #include <powerpc/mpc85xx/mpc85xx.h>
59 * MPC85xx system specific routines
63 ccsr_read4(uintptr_t addr)
65 volatile uint32_t *ptr = (void *)addr;
71 ccsr_write4(uintptr_t addr, uint32_t val)
73 volatile uint32_t *ptr = (void *)addr;
85 ver = SVR_VER(mfspr(SPR_SVR));
113 law_write(uint32_t n, uint64_t bar, uint32_t sr)
116 if (mpc85xx_is_qoriq()) {
117 ccsr_write4(OCP85XX_LAWBARH(n), bar >> 32);
118 ccsr_write4(OCP85XX_LAWBARL(n), bar);
119 ccsr_write4(OCP85XX_LAWSR_QORIQ(n), sr);
120 ccsr_read4(OCP85XX_LAWSR_QORIQ(n));
122 ccsr_write4(OCP85XX_LAWBAR(n), bar >> 12);
123 ccsr_write4(OCP85XX_LAWSR_85XX(n), sr);
124 ccsr_read4(OCP85XX_LAWSR_85XX(n));
128 * The last write to LAWAR should be followed by a read
129 * of LAWAR before any device try to use any of windows.
130 * What more the read of LAWAR should be followed by isync
138 law_read(uint32_t n, uint64_t *bar, uint32_t *sr)
141 if (mpc85xx_is_qoriq()) {
142 *bar = (uint64_t)ccsr_read4(OCP85XX_LAWBARH(n)) << 32 |
143 ccsr_read4(OCP85XX_LAWBARL(n));
144 *sr = ccsr_read4(OCP85XX_LAWSR_QORIQ(n));
146 *bar = (uint64_t)ccsr_read4(OCP85XX_LAWBAR(n)) << 12;
147 *sr = ccsr_read4(OCP85XX_LAWSR_85XX(n));
158 law_max = law_getmax();
160 for (i = 0; i < law_max; i++) {
161 law_read(i, &bar, &sr);
162 if ((sr & 0x80000000) == 0)
169 #define _LAW_SR(trgt,size) (0x80000000 | (trgt << 20) | \
170 (flsl(size + (size - 1)) - 2))
173 law_enable(int trgt, uint64_t bar, uint32_t size)
182 law_max = law_getmax();
183 sr = _LAW_SR(trgt, size);
185 /* Bail if already programmed. */
186 for (i = 0; i < law_max; i++) {
187 law_read(i, &bar_tmp, &sr_tmp);
188 if (sr == sr_tmp && bar == bar_tmp)
192 /* Find an unused access window. */
198 law_write(i, bar, sr);
203 law_disable(int trgt, uint64_t bar, uint32_t size)
209 law_max = law_getmax();
210 sr = _LAW_SR(trgt, size);
212 /* Find and disable requested LAW. */
213 for (i = 0; i < law_max; i++) {
214 law_read(i, &bar_tmp, &sr_tmp);
215 if (sr == sr_tmp && bar == bar_tmp) {
225 law_pci_target(struct resource *res, int *trgt_mem, int *trgt_io)
231 ver = SVR_VER(mfspr(SPR_SVR));
233 start = rman_get_start(res) & 0xf000;
248 if (ver == SVR_MPC8548E || ver == SVR_MPC8548)
255 if (ver == SVR_MPC8548E || ver == SVR_MPC8548)
274 /* Flash invalidate the CPC and clear all the locks */
275 ccsr_write4(OCP85XX_CPC_CSR0, OCP85XX_CPC_CSR0_FI |
276 OCP85XX_CPC_CSR0_LFC);
277 while (ccsr_read4(OCP85XX_CPC_CSR0) & (OCP85XX_CPC_CSR0_FI |
278 OCP85XX_CPC_CSR0_LFC))
286 ccsr_write4(OCP85XX_CPC_CSR0, OCP85XX_CPC_CSR0_CE |
287 OCP85XX_CPC_CSR0_PE);
288 /* Read back to sync write */
289 ccsr_read4(OCP85XX_CPC_CSR0);
293 mpc85xx_enable_l3_cache(void)
295 uint32_t csr, size, ver;
297 /* Enable L3 CoreNet Platform Cache (CPC) */
298 ver = SVR_VER(mfspr(SPR_SVR));
299 if (ver == SVR_P2041 || ver == SVR_P2041E || ver == SVR_P3041 ||
300 ver == SVR_P3041E || ver == SVR_P5020 || ver == SVR_P5020E) {
301 csr = ccsr_read4(OCP85XX_CPC_CSR0);
302 if ((csr & OCP85XX_CPC_CSR0_CE) == 0) {
307 csr = ccsr_read4(OCP85XX_CPC_CSR0);
308 if ((boothowto & RB_VERBOSE) != 0 ||
309 (csr & OCP85XX_CPC_CSR0_CE) == 0) {
310 size = OCP85XX_CPC_CFG0_SZ_K(ccsr_read4(OCP85XX_CPC_CFG0));
311 printf("L3 Corenet Platform Cache: %d KB %sabled\n",
312 size, (csr & OCP85XX_CPC_CSR0_CE) == 0 ?
319 mpc85xx_is_qoriq(void)
321 uint16_t pvr = mfpvr() >> 16;
323 /* QorIQ register set is only in e500mc and derivative core based SoCs. */
324 if (pvr == FSL_E500mc || pvr == FSL_E5500 || pvr == FSL_E6500)
331 mpc85xx_dataloss_erratum_spr976(void)
333 uint32_t svr = SVR_VER(mfspr(SPR_SVR));
335 /* Ignore whether it's the E variant */
338 if (svr != SVR_P3041 && svr != SVR_P4040 &&
339 svr != SVR_P4080 && svr != SVR_P5020)
344 mtspr(976, (mfspr(976) & ~0x1f8) | 0x48);
349 mpc85xx_map_dcsr(void)
356 * Try to access the dcsr node directly i.e. through /aliases/.
358 if ((node = OF_finddevice("dcsr")) != -1)
359 if (fdt_is_compatible_strict(node, "fsl,dcsr"))
362 * Find the node the long way.
364 if ((node = OF_finddevice("/")) == -1)
367 if ((node = ofw_bus_find_compatible(node, "fsl,dcsr")) == 0)
371 err = fdt_get_range(node, 0, &b, &s);
376 law_enable(OCP85XX_TGTIF_DCSR, b, 0x400000);
377 return pmap_early_io_map(b, 0x400000);
383 mpc85xx_fix_errata(vm_offset_t va_ccsr)
385 uint32_t svr = SVR_VER(mfspr(SPR_SVR));
388 /* Ignore whether it's the E variant */
391 if (svr != SVR_P3041 && svr != SVR_P4040 &&
392 svr != SVR_P4080 && svr != SVR_P5020)
395 if (mfmsr() & PSL_EE)
399 * dcsr region need to be mapped thus patch can refer to.
400 * Align dcsr right after ccsbar.
402 va_dcsr = mpc85xx_map_dcsr();
407 * As A004510 errata specify, special purpose register 976
408 * SPR976[56:60] = 6'b001001 must be set. e500mc core reference manual
409 * does not document SPR976 register.
411 mpc85xx_dataloss_erratum_spr976();
414 * Specific settings in the CCF and core platform cache (CPC)
415 * are required to reconfigure the CoreNet coherency fabric.
416 * The register settings that should be updated are described
417 * in errata and relay on base address, offset and updated value.
418 * Special conditions must be used to update these registers correctly.
420 dataloss_erratum_access(va_dcsr + 0xb0e08, 0xe0201800);
421 dataloss_erratum_access(va_dcsr + 0xb0e18, 0xe0201800);
422 dataloss_erratum_access(va_dcsr + 0xb0e38, 0xe0400000);
423 dataloss_erratum_access(va_dcsr + 0xb0008, 0x00900000);
424 dataloss_erratum_access(va_dcsr + 0xb0e40, 0xe00a0000);
428 dataloss_erratum_access(va_ccsr + 0x18600, 0xc0000000);
432 dataloss_erratum_access(va_ccsr + 0x18600, 0xff000000);
435 dataloss_erratum_access(va_ccsr + 0x18600, 0xf0000000);
437 dataloss_erratum_access(va_ccsr + 0x10f00, 0x415e5000);
438 dataloss_erratum_access(va_ccsr + 0x11f00, 0x415e5000);
445 mpc85xx_get_platform_clock(void)
448 static uint32_t freq;
453 soc = OF_finddevice("/soc");
455 /* freq isn't modified on error. */
456 OF_getencprop(soc, "bus-frequency", (void *)&freq, sizeof(freq));
462 mpc85xx_get_system_clock(void)
466 freq = mpc85xx_get_platform_clock();