2 * Copyright (C) 2008 Semihalf, Rafal Jaworowski
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
30 #include "opt_platform.h"
31 #include <sys/param.h>
32 #include <sys/systm.h>
34 #include <sys/mutex.h>
35 #include <sys/reboot.h>
39 #include <vm/vm_param.h>
42 #include <machine/cpu.h>
43 #include <machine/cpufunc.h>
44 #include <machine/machdep.h>
45 #include <machine/pio.h>
46 #include <machine/spr.h>
48 #include <dev/fdt/fdt_common.h>
50 #include <dev/fdt/fdt_common.h>
51 #include <dev/ofw/ofw_bus.h>
52 #include <dev/ofw/ofw_bus_subr.h>
53 #include <dev/ofw/openfirm.h>
55 #include <powerpc/mpc85xx/mpc85xx.h>
59 * MPC85xx system specific routines
63 ccsr_read4(uintptr_t addr)
65 volatile uint32_t *ptr = (void *)addr;
71 ccsr_write4(uintptr_t addr, uint32_t val)
73 volatile uint32_t *ptr = (void *)addr;
85 ver = SVR_VER(mfspr(SPR_SVR));
109 law_write(uint32_t n, uint64_t bar, uint32_t sr)
112 if (mpc85xx_is_qoriq()) {
113 ccsr_write4(OCP85XX_LAWBARH(n), bar >> 32);
114 ccsr_write4(OCP85XX_LAWBARL(n), bar);
115 ccsr_write4(OCP85XX_LAWSR_QORIQ(n), sr);
116 ccsr_read4(OCP85XX_LAWSR_QORIQ(n));
118 ccsr_write4(OCP85XX_LAWBAR(n), bar >> 12);
119 ccsr_write4(OCP85XX_LAWSR_85XX(n), sr);
120 ccsr_read4(OCP85XX_LAWSR_85XX(n));
124 * The last write to LAWAR should be followed by a read
125 * of LAWAR before any device try to use any of windows.
126 * What more the read of LAWAR should be followed by isync
134 law_read(uint32_t n, uint64_t *bar, uint32_t *sr)
137 if (mpc85xx_is_qoriq()) {
138 *bar = (uint64_t)ccsr_read4(OCP85XX_LAWBARH(n)) << 32 |
139 ccsr_read4(OCP85XX_LAWBARL(n));
140 *sr = ccsr_read4(OCP85XX_LAWSR_QORIQ(n));
142 *bar = (uint64_t)ccsr_read4(OCP85XX_LAWBAR(n)) << 12;
143 *sr = ccsr_read4(OCP85XX_LAWSR_85XX(n));
154 law_max = law_getmax();
156 for (i = 0; i < law_max; i++) {
157 law_read(i, &bar, &sr);
158 if ((sr & 0x80000000) == 0)
165 #define _LAW_SR(trgt,size) (0x80000000 | (trgt << 20) | \
166 (flsl(size + (size - 1)) - 2))
169 law_enable(int trgt, uint64_t bar, uint32_t size)
178 law_max = law_getmax();
179 sr = _LAW_SR(trgt, size);
181 /* Bail if already programmed. */
182 for (i = 0; i < law_max; i++) {
183 law_read(i, &bar_tmp, &sr_tmp);
184 if (sr == sr_tmp && bar == bar_tmp)
188 /* Find an unused access window. */
194 law_write(i, bar, sr);
199 law_disable(int trgt, uint64_t bar, uint32_t size)
205 law_max = law_getmax();
206 sr = _LAW_SR(trgt, size);
208 /* Find and disable requested LAW. */
209 for (i = 0; i < law_max; i++) {
210 law_read(i, &bar_tmp, &sr_tmp);
211 if (sr == sr_tmp && bar == bar_tmp) {
221 law_pci_target(struct resource *res, int *trgt_mem, int *trgt_io)
227 ver = SVR_VER(mfspr(SPR_SVR));
229 start = rman_get_start(res) & 0xf000;
244 if (ver == SVR_MPC8548E || ver == SVR_MPC8548)
251 if (ver == SVR_MPC8548E || ver == SVR_MPC8548)
270 /* Flash invalidate the CPC and clear all the locks */
271 ccsr_write4(OCP85XX_CPC_CSR0, OCP85XX_CPC_CSR0_FI |
272 OCP85XX_CPC_CSR0_LFC);
273 while (ccsr_read4(OCP85XX_CPC_CSR0) & (OCP85XX_CPC_CSR0_FI |
274 OCP85XX_CPC_CSR0_LFC))
282 ccsr_write4(OCP85XX_CPC_CSR0, OCP85XX_CPC_CSR0_CE |
283 OCP85XX_CPC_CSR0_PE);
284 /* Read back to sync write */
285 ccsr_read4(OCP85XX_CPC_CSR0);
289 mpc85xx_enable_l3_cache(void)
291 uint32_t csr, size, ver;
293 /* Enable L3 CoreNet Platform Cache (CPC) */
294 ver = SVR_VER(mfspr(SPR_SVR));
295 if (ver == SVR_P2041 || ver == SVR_P2041E || ver == SVR_P3041 ||
296 ver == SVR_P3041E || ver == SVR_P5020 || ver == SVR_P5020E) {
297 csr = ccsr_read4(OCP85XX_CPC_CSR0);
298 if ((csr & OCP85XX_CPC_CSR0_CE) == 0) {
303 csr = ccsr_read4(OCP85XX_CPC_CSR0);
304 if ((boothowto & RB_VERBOSE) != 0 ||
305 (csr & OCP85XX_CPC_CSR0_CE) == 0) {
306 size = OCP85XX_CPC_CFG0_SZ_K(ccsr_read4(OCP85XX_CPC_CFG0));
307 printf("L3 Corenet Platform Cache: %d KB %sabled\n",
308 size, (csr & OCP85XX_CPC_CSR0_CE) == 0 ?
315 mpc85xx_is_qoriq(void)
317 uint16_t pvr = mfpvr() >> 16;
319 /* QorIQ register set is only in e500mc and derivative core based SoCs. */
320 if (pvr == FSL_E500mc || pvr == FSL_E5500 || pvr == FSL_E6500)
327 mpc85xx_dataloss_erratum_spr976(void)
329 uint32_t svr = SVR_VER(mfspr(SPR_SVR));
331 /* Ignore whether it's the E variant */
334 if (svr != SVR_P3041 && svr != SVR_P4040 &&
335 svr != SVR_P4080 && svr != SVR_P5020)
340 mtspr(976, (mfspr(976) & ~0x1f8) | 0x48);
345 mpc85xx_map_dcsr(void)
352 * Try to access the dcsr node directly i.e. through /aliases/.
354 if ((node = OF_finddevice("dcsr")) != -1)
355 if (fdt_is_compatible_strict(node, "fsl,dcsr"))
358 * Find the node the long way.
360 if ((node = OF_finddevice("/")) == -1)
363 if ((node = ofw_bus_find_compatible(node, "fsl,dcsr")) == 0)
367 err = fdt_get_range(node, 0, &b, &s);
372 law_enable(OCP85XX_TGTIF_DCSR, b, 0x400000);
373 return pmap_early_io_map(b, 0x400000);
379 mpc85xx_fix_errata(vm_offset_t va_ccsr)
381 uint32_t svr = SVR_VER(mfspr(SPR_SVR));
384 /* Ignore whether it's the E variant */
387 if (svr != SVR_P3041 && svr != SVR_P4040 &&
388 svr != SVR_P4080 && svr != SVR_P5020)
391 if (mfmsr() & PSL_EE)
395 * dcsr region need to be mapped thus patch can refer to.
396 * Align dcsr right after ccsbar.
398 va_dcsr = mpc85xx_map_dcsr();
403 * As A004510 errata specify, special purpose register 976
404 * SPR976[56:60] = 6'b001001 must be set. e500mc core reference manual
405 * does not document SPR976 register.
407 mpc85xx_dataloss_erratum_spr976();
410 * Specific settings in the CCF and core platform cache (CPC)
411 * are required to reconfigure the CoreNet coherency fabric.
412 * The register settings that should be updated are described
413 * in errata and relay on base address, offset and updated value.
414 * Special conditions must be used to update these registers correctly.
416 dataloss_erratum_access(va_dcsr + 0xb0e08, 0xe0201800);
417 dataloss_erratum_access(va_dcsr + 0xb0e18, 0xe0201800);
418 dataloss_erratum_access(va_dcsr + 0xb0e38, 0xe0400000);
419 dataloss_erratum_access(va_dcsr + 0xb0008, 0x00900000);
420 dataloss_erratum_access(va_dcsr + 0xb0e40, 0xe00a0000);
424 dataloss_erratum_access(va_ccsr + 0x18600, 0xc0000000);
428 dataloss_erratum_access(va_ccsr + 0x18600, 0xff000000);
431 dataloss_erratum_access(va_ccsr + 0x18600, 0xf0000000);
433 dataloss_erratum_access(va_ccsr + 0x10f00, 0x415e5000);
434 dataloss_erratum_access(va_ccsr + 0x11f00, 0x415e5000);
441 mpc85xx_get_system_clock(void)
446 soc = OF_finddevice("/soc");
449 /* freq isn't modified on error. */
450 OF_getencprop(soc, "bus-frequency", (void *)&freq, sizeof(freq));