2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (C) 2008 Semihalf, Rafal Jaworowski
5 * Copyright 2006 by Juniper Networks.
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
35 #include <machine/platformvar.h>
38 * Configuration control and status registers
40 extern vm_offset_t ccsrbar_va;
41 extern vm_paddr_t ccsrbar_pa;
42 extern vm_size_t ccsrbar_size;
43 #define CCSRBAR_VA ccsrbar_va
44 #define OCP85XX_CCSRBAR (CCSRBAR_VA + 0x0)
45 #define OCP85XX_BPTR (CCSRBAR_VA + 0x20)
47 #define OCP85XX_BSTRH (CCSRBAR_VA + 0x20)
48 #define OCP85XX_BSTRL (CCSRBAR_VA + 0x24)
49 #define OCP85XX_BSTAR (CCSRBAR_VA + 0x28)
51 #define OCP85XX_COREDISR (CCSRBAR_VA + 0xE0094)
52 #define OCP85XX_BRR (CCSRBAR_VA + 0xE00E4)
55 * Run Control and Power Management registers
57 #define CCSR_CTBENR (CCSRBAR_VA + 0xE2084)
58 #define CCSR_CTBCKSELR (CCSRBAR_VA + 0xE208C)
59 #define CCSR_CTBCHLTCR (CCSRBAR_VA + 0xE2094)
62 * DDR Memory controller.
64 #define OCP85XX_DDR1_CS0_CONFIG (CCSRBAR_VA + 0x8080)
67 * E500 Coherency Module registers
69 #define OCP85XX_EEBPCR (CCSRBAR_VA + 0x1010)
72 * Local access registers
74 /* Write order: OCP_LAWBARH -> OCP_LAWBARL -> OCP_LAWSR */
75 #define OCP85XX_LAWBARH(n) (CCSRBAR_VA + 0xc00 + 0x10 * (n))
76 #define OCP85XX_LAWBARL(n) (CCSRBAR_VA + 0xc04 + 0x10 * (n))
77 #define OCP85XX_LAWSR_QORIQ(n) (CCSRBAR_VA + 0xc08 + 0x10 * (n))
78 #define OCP85XX_LAWBAR(n) (CCSRBAR_VA + 0xc08 + 0x10 * (n))
79 #define OCP85XX_LAWSR_85XX(n) (CCSRBAR_VA + 0xc10 + 0x10 * (n))
80 #define OCP85XX_LAWSR(n) (mpc85xx_is_qoriq() ? OCP85XX_LAWSR_QORIQ(n) : \
81 OCP85XX_LAWSR_85XX(n))
83 /* Attribute register */
84 #define OCP85XX_ENA_MASK 0x80000000
85 #define OCP85XX_DIS_MASK 0x7fffffff
87 #define OCP85XX_TGTIF_LBC_QORIQ 0x1f
88 #define OCP85XX_TGTIF_RAM_INTL_QORIQ 0x14
89 #define OCP85XX_TGTIF_RAM1_QORIQ 0x10
90 #define OCP85XX_TGTIF_RAM2_QORIQ 0x11
91 #define OCP85XX_TGTIF_BMAN 0x18
92 #define OCP85XX_TGTIF_DCSR 0x1D
93 #define OCP85XX_TGTIF_QMAN 0x3C
94 #define OCP85XX_TRGT_SHIFT_QORIQ 20
96 #define OCP85XX_TGTIF_LBC_85XX 0x04
97 #define OCP85XX_TGTIF_RAM_INTL_85XX 0x0b
98 #define OCP85XX_TGTIF_RIO_85XX 0x0c
99 #define OCP85XX_TGTIF_RAM1_85XX 0x0f
100 #define OCP85XX_TGTIF_RAM2_85XX 0x16
102 #define OCP85XX_TGTIF_LBC \
103 (mpc85xx_is_qoriq() ? OCP85XX_TGTIF_LBC_QORIQ : OCP85XX_TGTIF_LBC_85XX)
104 #define OCP85XX_TGTIF_RAM_INTL \
105 (mpc85xx_is_qoriq() ? OCP85XX_TGTIF_RAM_INTL_QORIQ : OCP85XX_TGTIF_RAM_INTL_85XX)
106 #define OCP85XX_TGTIF_RIO \
107 (mpc85xx_is_qoriq() ? OCP85XX_TGTIF_RIO_QORIQ : OCP85XX_TGTIF_RIO_85XX)
108 #define OCP85XX_TGTIF_RAM1 \
109 (mpc85xx_is_qoriq() ? OCP85XX_TGTIF_RAM1_QORIQ : OCP85XX_TGTIF_RAM1_85XX)
110 #define OCP85XX_TGTIF_RAM2 \
111 (mpc85xx_is_qoriq() ? OCP85XX_TGTIF_RAM2_QORIQ : OCP85XX_TGTIF_RAM2_85XX)
116 #define OCP85XX_L2CTL (CCSRBAR_VA + 0x20000)
119 * L3 CoreNet platform cache (CPC) registers
121 #define OCP85XX_CPC_CSR0 (CCSRBAR_VA + 0x10000)
122 #define OCP85XX_CPC_CSR0_CE 0x80000000
123 #define OCP85XX_CPC_CSR0_PE 0x40000000
124 #define OCP85XX_CPC_CSR0_FI 0x00200000
125 #define OCP85XX_CPC_CSR0_WT 0x00080000
126 #define OCP85XX_CPC_CSR0_FL 0x00000800
127 #define OCP85XX_CPC_CSR0_LFC 0x00000400
128 #define OCP85XX_CPC_CFG0 (CCSRBAR_VA + 0x10008)
129 #define OCP85XX_CPC_CFG_SZ_MASK 0x00003fff
130 #define OCP85XX_CPC_CFG0_SZ_K(x) (((x) & OCP85XX_CPC_CFG_SZ_MASK) << 6)
133 * Power-On Reset configuration
135 #define OCP85XX_PORDEVSR (CCSRBAR_VA + 0xe000c)
136 #define OCP85XX_PORDEVSR_IO_SEL 0x00780000
137 #define OCP85XX_PORDEVSR_IO_SEL_SHIFT 19
139 #define OCP85XX_PORDEVSR2 (CCSRBAR_VA + 0xe0014)
144 #define OCP85XX_RSTCR (CCSRBAR_VA + 0xe00b0)
146 #define OCP85XX_CLKDVDR (CCSRBAR_VA + 0xe0800)
147 #define OCP85XX_CLKDVDR_PXCKEN 0x80000000
148 #define OCP85XX_CLKDVDR_SSICKEN 0x20000000
149 #define OCP85XX_CLKDVDR_PXCKINV 0x10000000
150 #define OCP85XX_CLKDVDR_PXCLK_MASK 0x00FF0000
151 #define OCP85XX_CLKDVDR_SSICLK_MASK 0x000000FF
154 * Run Control/Power Management Registers.
156 #define OCP85XX_RCPM_CDOZSR (CCSRBAR_VA + 0xe2004)
157 #define OCP85XX_RCPM_CDOZCR (CCSRBAR_VA + 0xe200c)
162 uint32_t ccsr_read4(uintptr_t addr);
163 void ccsr_write4(uintptr_t addr, uint32_t val);
164 int law_enable(int trgt, uint64_t bar, uint32_t size);
165 int law_disable(int trgt, uint64_t bar, uint32_t size);
166 int law_getmax(void);
167 int law_pci_target(struct resource *, int *, int *);
169 DECLARE_CLASS(mpc85xx_platform);
170 int mpc85xx_attach(platform_t);
172 void mpc85xx_enable_l3_cache(void);
173 int mpc85xx_is_qoriq(void);
174 uint32_t mpc85xx_get_platform_clock(void);
175 uint32_t mpc85xx_get_system_clock(void);
177 #endif /* _MPC85XX_H_ */