2 * SPDX-License-Identifier: BSD-3-Clause
4 * Copyright 2006-2007 by Juniper Networks.
5 * Copyright 2008 Semihalf.
6 * Copyright 2010 The FreeBSD Foundation
9 * Portions of this software were developed by Semihalf
10 * under sponsorship from the FreeBSD Foundation.
12 * Redistribution and use in source and binary forms, with or without
13 * modification, are permitted provided that the following conditions
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in the
19 * documentation and/or other materials provided with the distribution.
20 * 3. The name of the author may not be used to endorse or promote products
21 * derived from this software without specific prior written permission.
23 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
26 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
28 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
30 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
31 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
35 * From: FreeBSD: src/sys/powerpc/mpc85xx/pci_ocp.c,v 1.9 2010/03/23 23:46:28 marcel
38 #include <sys/cdefs.h>
39 __FBSDID("$FreeBSD$");
41 #include <sys/param.h>
42 #include <sys/systm.h>
44 #include <sys/sockio.h>
46 #include <sys/malloc.h>
47 #include <sys/kernel.h>
48 #include <sys/module.h>
49 #include <sys/socket.h>
50 #include <sys/queue.h>
53 #include <sys/mutex.h>
54 #include <sys/queue.h>
56 #include <sys/endian.h>
62 #include <dev/ofw/ofw_pci.h>
63 #include <dev/ofw/ofw_bus.h>
64 #include <dev/ofw/ofw_bus_subr.h>
65 #include <dev/ofw/ofwpci.h>
66 #include <dev/pci/pcivar.h>
67 #include <dev/pci/pcireg.h>
68 #include <dev/pci/pcib_private.h>
70 #include "ofw_bus_if.h"
74 #include <machine/resource.h>
75 #include <machine/bus.h>
76 #include <machine/intr_machdep.h>
78 #include <powerpc/mpc85xx/mpc85xx.h>
80 #define REG_CFG_ADDR 0x0000
81 #define CONFIG_ACCESS_ENABLE 0x80000000
83 #define REG_CFG_DATA 0x0004
84 #define REG_INT_ACK 0x0008
86 #define REG_PEX_IP_BLK_REV1 0x0bf8
87 #define IP_MJ_M 0x0000ff00
89 #define IP_MN_M 0x000000ff
92 #define REG_POTAR(n) (0x0c00 + 0x20 * (n))
93 #define REG_POTEAR(n) (0x0c04 + 0x20 * (n))
94 #define REG_POWBAR(n) (0x0c08 + 0x20 * (n))
95 #define REG_POWAR(n) (0x0c10 + 0x20 * (n))
97 #define REG_PITAR(n) (0x0e00 - 0x20 * (n))
98 #define REG_PIWBAR(n) (0x0e08 - 0x20 * (n))
99 #define REG_PIWBEAR(n) (0x0e0c - 0x20 * (n))
100 #define REG_PIWAR(n) (0x0e10 - 0x20 * (n))
101 #define PIWAR_EN 0x80000000
102 #define PIWAR_PF 0x40000000
103 #define PIWAR_TRGT_M 0x00f00000
104 #define PIWAR_TRGT_S 20
105 #define PIWAR_TRGT_CCSR 0xe
106 #define PIWAR_TRGT_LOCAL 0xf
108 #define REG_PEX_MES_DR 0x0020
109 #define REG_PEX_MES_IER 0x0028
110 #define REG_PEX_ERR_DR 0x0e00
111 #define REG_PEX_ERR_EN 0x0e08
113 #define REG_PEX_ERR_DR 0x0e00
114 #define REG_PEX_ERR_DR_ME 0x80000000
115 #define REG_PEX_ERR_DR_PCT 0x800000
116 #define REG_PEX_ERR_DR_PAT 0x400000
117 #define REG_PEX_ERR_DR_PCAC 0x200000
118 #define REG_PEX_ERR_DR_PNM 0x100000
119 #define REG_PEX_ERR_DR_CDNSC 0x80000
120 #define REG_PEX_ERR_DR_CRSNC 0x40000
121 #define REG_PEX_ERR_DR_ICCA 0x20000
122 #define REG_PEX_ERR_DR_IACA 0x10000
123 #define REG_PEX_ERR_DR_CRST 0x8000
124 #define REG_PEX_ERR_DR_MIS 0x4000
125 #define REG_PEX_ERR_DR_IOIS 0x2000
126 #define REG_PEX_ERR_DR_CIS 0x1000
127 #define REG_PEX_ERR_DR_CIEP 0x800
128 #define REG_PEX_ERR_DR_IOIEP 0x400
129 #define REG_PEX_ERR_DR_OAC 0x200
130 #define REG_PEX_ERR_DR_IOIA 0x100
131 #define REG_PEX_ERR_DR_IMBA 0x80
132 #define REG_PEX_ERR_DR_IIOBA 0x40
133 #define REG_PEX_ERR_DR_LDDE 0x20
134 #define REG_PEX_ERR_EN 0x0e08
136 #define PCIR_LTSSM 0x404
137 #define LTSSM_STAT_L0 0x16
139 #define DEVFN(b, s, f) ((b << 16) | (s << 8) | f)
141 #define FSL_NUM_MSIS 256 /* 8 registers of 32 bits (8 hardware IRQs) */
142 #define PCI_SLOT_FIRST 0x1 /* used to be 0x11 but qemu-ppce500 starts from 0x1 */
144 struct fsl_pcib_softc {
145 struct ofw_pci_softc pci_sc;
147 struct mtx sc_cfg_mtx;
152 bus_addr_t sc_iomem_start, sc_iomem_end;
153 int sc_ioport_target;
154 bus_addr_t sc_ioport_start, sc_ioport_end;
156 struct resource *sc_res;
157 bus_space_handle_t sc_bsh;
158 bus_space_tag_t sc_bst;
161 struct resource *sc_irq_res;
166 uint8_t sc_pcie_capreg; /* PCI-E Capability Reg Set */
169 struct fsl_pcib_err_dr {
171 uint32_t err_dr_mask;
175 SLIST_ENTRY(fsl_msi_map) slist;
180 SLIST_HEAD(msi_head, fsl_msi_map) fsl_msis = SLIST_HEAD_INITIALIZER(msi_head);
182 static const struct fsl_pcib_err_dr pci_err[] = {
183 {"ME", REG_PEX_ERR_DR_ME},
184 {"PCT", REG_PEX_ERR_DR_PCT},
185 {"PAT", REG_PEX_ERR_DR_PAT},
186 {"PCAC", REG_PEX_ERR_DR_PCAC},
187 {"PNM", REG_PEX_ERR_DR_PNM},
188 {"CDNSC", REG_PEX_ERR_DR_CDNSC},
189 {"CRSNC", REG_PEX_ERR_DR_CRSNC},
190 {"ICCA", REG_PEX_ERR_DR_ICCA},
191 {"IACA", REG_PEX_ERR_DR_IACA},
192 {"CRST", REG_PEX_ERR_DR_CRST},
193 {"MIS", REG_PEX_ERR_DR_MIS},
194 {"IOIS", REG_PEX_ERR_DR_IOIS},
195 {"CIS", REG_PEX_ERR_DR_CIS},
196 {"CIEP", REG_PEX_ERR_DR_CIEP},
197 {"IOIEP", REG_PEX_ERR_DR_IOIEP},
198 {"OAC", REG_PEX_ERR_DR_OAC},
199 {"IOIA", REG_PEX_ERR_DR_IOIA},
200 {"IMBA", REG_PEX_ERR_DR_IMBA},
201 {"IIOBA", REG_PEX_ERR_DR_IIOBA},
202 {"LDDE", REG_PEX_ERR_DR_LDDE}
205 /* Local forward declerations. */
206 static uint32_t fsl_pcib_cfgread(struct fsl_pcib_softc *, u_int, u_int, u_int,
208 static void fsl_pcib_cfgwrite(struct fsl_pcib_softc *, u_int, u_int, u_int,
209 u_int, uint32_t, int);
210 static int fsl_pcib_decode_win(phandle_t, struct fsl_pcib_softc *);
211 static void fsl_pcib_err_init(device_t);
212 static void fsl_pcib_inbound(struct fsl_pcib_softc *, int, int, uint64_t,
214 static void fsl_pcib_outbound(struct fsl_pcib_softc *, int, int, uint64_t,
217 /* Forward declerations. */
218 static int fsl_pcib_attach(device_t);
219 static int fsl_pcib_detach(device_t);
220 static int fsl_pcib_probe(device_t);
222 static int fsl_pcib_maxslots(device_t);
223 static uint32_t fsl_pcib_read_config(device_t, u_int, u_int, u_int, u_int, int);
224 static void fsl_pcib_write_config(device_t, u_int, u_int, u_int, u_int,
226 static int fsl_pcib_alloc_msi(device_t dev, device_t child,
227 int count, int maxcount, int *irqs);
228 static int fsl_pcib_release_msi(device_t dev, device_t child,
229 int count, int *irqs);
230 static int fsl_pcib_alloc_msix(device_t dev, device_t child, int *irq);
231 static int fsl_pcib_release_msix(device_t dev, device_t child, int irq);
232 static int fsl_pcib_map_msi(device_t dev, device_t child,
233 int irq, uint64_t *addr, uint32_t *data);
235 static vmem_t *msi_vmem; /* Global MSI vmem, holds all MSI ranges. */
238 * Bus interface definitions.
240 static device_method_t fsl_pcib_methods[] = {
241 /* Device interface */
242 DEVMETHOD(device_probe, fsl_pcib_probe),
243 DEVMETHOD(device_attach, fsl_pcib_attach),
244 DEVMETHOD(device_detach, fsl_pcib_detach),
247 DEVMETHOD(pcib_maxslots, fsl_pcib_maxslots),
248 DEVMETHOD(pcib_read_config, fsl_pcib_read_config),
249 DEVMETHOD(pcib_write_config, fsl_pcib_write_config),
250 DEVMETHOD(pcib_alloc_msi, fsl_pcib_alloc_msi),
251 DEVMETHOD(pcib_release_msi, fsl_pcib_release_msi),
252 DEVMETHOD(pcib_alloc_msix, fsl_pcib_alloc_msix),
253 DEVMETHOD(pcib_release_msix, fsl_pcib_release_msix),
254 DEVMETHOD(pcib_map_msi, fsl_pcib_map_msi),
259 DEFINE_CLASS_1(pcib, fsl_pcib_driver, fsl_pcib_methods,
260 sizeof(struct fsl_pcib_softc), ofw_pcib_driver);
261 EARLY_DRIVER_MODULE(pcib, ofwbus, fsl_pcib_driver, 0, 0, BUS_PASS_BUS);
264 fsl_pcib_err_intr(void *v)
266 struct fsl_pcib_softc *sc;
268 uint32_t err_reg, clear_reg;
272 sc = device_get_softc(dev);
275 err_reg = bus_space_read_4(sc->sc_bst, sc->sc_bsh, REG_PEX_ERR_DR);
277 /* Check which one error occurred */
278 for (i = 0; i < sizeof(pci_err)/sizeof(struct fsl_pcib_err_dr); i++) {
279 if (err_reg & pci_err[i].err_dr_mask) {
280 device_printf(dev, "PCI %d: report %s error\n",
281 device_get_unit(dev), pci_err[i].msg);
282 clear_reg |= pci_err[i].err_dr_mask;
286 /* Clear pending errors */
287 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_PEX_ERR_DR, clear_reg);
291 fsl_pcib_probe(device_t dev)
294 if (ofw_bus_get_type(dev) == NULL ||
295 strcmp(ofw_bus_get_type(dev), "pci") != 0)
298 if (!(ofw_bus_is_compatible(dev, "fsl,mpc8540-pci") ||
299 ofw_bus_is_compatible(dev, "fsl,mpc8540-pcie") ||
300 ofw_bus_is_compatible(dev, "fsl,mpc8548-pcie") ||
301 ofw_bus_is_compatible(dev, "fsl,p5020-pcie") ||
302 ofw_bus_is_compatible(dev, "fsl,p5040-pcie") ||
303 ofw_bus_is_compatible(dev, "fsl,qoriq-pcie-v2.2") ||
304 ofw_bus_is_compatible(dev, "fsl,qoriq-pcie-v2.4") ||
305 ofw_bus_is_compatible(dev, "fsl,qoriq-pcie")))
308 device_set_desc(dev, "Freescale Integrated PCI/PCI-E Controller");
309 return (BUS_PROBE_DEFAULT);
313 fsl_pcib_attach(device_t dev)
315 struct fsl_pcib_softc *sc;
317 uint32_t cfgreg, brctl, ipreg;
318 int do_reset, error, rid;
319 uint8_t ltssm, capptr;
321 sc = device_get_softc(dev);
325 sc->sc_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->sc_rid,
327 if (sc->sc_res == NULL) {
328 device_printf(dev, "could not map I/O memory\n");
331 sc->sc_bst = rman_get_bustag(sc->sc_res);
332 sc->sc_bsh = rman_get_bushandle(sc->sc_res);
335 ipreg = bus_read_4(sc->sc_res, REG_PEX_IP_BLK_REV1);
336 sc->sc_ip_min = (ipreg & IP_MN_M) >> IP_MN_S;
337 sc->sc_ip_maj = (ipreg & IP_MJ_M) >> IP_MJ_S;
338 mtx_init(&sc->sc_cfg_mtx, "pcicfg", NULL, MTX_SPIN);
340 cfgreg = fsl_pcib_cfgread(sc, 0, 0, 0, PCIR_VENDOR, 2);
341 if (cfgreg != 0x1057 && cfgreg != 0x1957)
344 capptr = fsl_pcib_cfgread(sc, 0, 0, 0, PCIR_CAP_PTR, 1);
345 while (capptr != 0) {
346 cfgreg = fsl_pcib_cfgread(sc, 0, 0, 0, capptr, 2);
347 switch (cfgreg & 0xff) {
352 sc->sc_pcie_capreg = capptr;
355 capptr = (cfgreg >> 8) & 0xff;
358 node = ofw_bus_get_node(dev);
361 * Initialize generic OF PCI interface (ranges, etc.)
364 error = ofw_pcib_init(dev);
369 * Configure decode windows for PCI(E) access.
371 if (fsl_pcib_decode_win(node, sc) != 0)
374 cfgreg = fsl_pcib_cfgread(sc, 0, 0, 0, PCIR_COMMAND, 2);
375 cfgreg |= PCIM_CMD_SERRESPEN | PCIM_CMD_BUSMASTEREN | PCIM_CMD_MEMEN |
377 fsl_pcib_cfgwrite(sc, 0, 0, 0, PCIR_COMMAND, cfgreg, 2);
380 resource_int_value("pcib", device_get_unit(dev), "reset", &do_reset);
382 /* Reset the bus. Needed for Radeon video cards. */
383 brctl = fsl_pcib_read_config(sc->sc_dev, 0, 0, 0,
384 PCIR_BRIDGECTL_1, 1);
385 brctl |= PCIB_BCR_SECBUS_RESET;
386 fsl_pcib_write_config(sc->sc_dev, 0, 0, 0,
387 PCIR_BRIDGECTL_1, brctl, 1);
389 brctl &= ~PCIB_BCR_SECBUS_RESET;
390 fsl_pcib_write_config(sc->sc_dev, 0, 0, 0,
391 PCIR_BRIDGECTL_1, brctl, 1);
396 ltssm = fsl_pcib_cfgread(sc, 0, 0, 0, PCIR_LTSSM, 1);
397 if (ltssm < LTSSM_STAT_L0) {
399 printf("PCI %d: no PCIE link, skipping\n",
400 device_get_unit(dev));
407 sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
408 RF_ACTIVE | RF_SHAREABLE);
409 if (sc->sc_irq_res == NULL) {
410 error = fsl_pcib_detach(dev);
413 "Detach of the driver failed with error %d\n",
419 /* Setup interrupt handler */
420 error = bus_setup_intr(dev, sc->sc_irq_res, INTR_TYPE_MISC | INTR_MPSAFE,
421 NULL, fsl_pcib_err_intr, dev, &sc->sc_ih);
423 device_printf(dev, "Could not setup irq, %d\n", error);
425 error = fsl_pcib_detach(dev);
428 "Detach of the driver failed with error %d\n",
434 fsl_pcib_err_init(dev);
436 return (ofw_pcib_attach(dev));
443 fsl_pcib_cfgread(struct fsl_pcib_softc *sc, u_int bus, u_int slot, u_int func,
444 u_int reg, int bytes)
448 addr = CONFIG_ACCESS_ENABLE;
449 addr |= (bus & 0xff) << 16;
450 addr |= (slot & 0x1f) << 11;
451 addr |= (func & 0x7) << 8;
454 addr |= (reg & 0xf00) << 16;
456 mtx_lock_spin(&sc->sc_cfg_mtx);
457 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_CFG_ADDR, addr);
461 data = bus_space_read_1(sc->sc_bst, sc->sc_bsh,
462 REG_CFG_DATA + (reg & 3));
465 data = le16toh(bus_space_read_2(sc->sc_bst, sc->sc_bsh,
466 REG_CFG_DATA + (reg & 2)));
469 data = le32toh(bus_space_read_4(sc->sc_bst, sc->sc_bsh,
476 mtx_unlock_spin(&sc->sc_cfg_mtx);
481 fsl_pcib_cfgwrite(struct fsl_pcib_softc *sc, u_int bus, u_int slot, u_int func,
482 u_int reg, uint32_t data, int bytes)
486 addr = CONFIG_ACCESS_ENABLE;
487 addr |= (bus & 0xff) << 16;
488 addr |= (slot & 0x1f) << 11;
489 addr |= (func & 0x7) << 8;
492 addr |= (reg & 0xf00) << 16;
494 mtx_lock_spin(&sc->sc_cfg_mtx);
495 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_CFG_ADDR, addr);
499 bus_space_write_1(sc->sc_bst, sc->sc_bsh,
500 REG_CFG_DATA + (reg & 3), data);
503 bus_space_write_2(sc->sc_bst, sc->sc_bsh,
504 REG_CFG_DATA + (reg & 2), htole16(data));
507 bus_space_write_4(sc->sc_bst, sc->sc_bsh,
508 REG_CFG_DATA, htole32(data));
511 mtx_unlock_spin(&sc->sc_cfg_mtx);
516 dump(struct fsl_pcib_softc *sc)
520 #define RD(o) bus_space_read_4(sc->sc_bst, sc->sc_bsh, o)
521 for (i = 0; i < 5; i++) {
522 printf("POTAR%u =0x%08x\n", i, RD(REG_POTAR(i)));
523 printf("POTEAR%u =0x%08x\n", i, RD(REG_POTEAR(i)));
524 printf("POWBAR%u =0x%08x\n", i, RD(REG_POWBAR(i)));
525 printf("POWAR%u =0x%08x\n", i, RD(REG_POWAR(i)));
528 for (i = 1; i < 4; i++) {
529 printf("PITAR%u =0x%08x\n", i, RD(REG_PITAR(i)));
530 printf("PIWBAR%u =0x%08x\n", i, RD(REG_PIWBAR(i)));
531 printf("PIWBEAR%u=0x%08x\n", i, RD(REG_PIWBEAR(i)));
532 printf("PIWAR%u =0x%08x\n", i, RD(REG_PIWAR(i)));
537 for (i = 0; i < 0x48; i += 4) {
538 printf("cfg%02x=0x%08x\n", i, fsl_pcib_cfgread(sc, 0, 0, 0,
545 fsl_pcib_maxslots(device_t dev)
547 struct fsl_pcib_softc *sc = device_get_softc(dev);
549 return ((sc->sc_pcie) ? 0 : PCI_SLOTMAX);
553 fsl_pcib_read_config(device_t dev, u_int bus, u_int slot, u_int func,
554 u_int reg, int bytes)
556 struct fsl_pcib_softc *sc = device_get_softc(dev);
558 if (bus == sc->sc_busnr && !sc->sc_pcie &&
559 slot < PCI_SLOT_FIRST)
562 return (fsl_pcib_cfgread(sc, bus, slot, func, reg, bytes));
566 fsl_pcib_write_config(device_t dev, u_int bus, u_int slot, u_int func,
567 u_int reg, uint32_t val, int bytes)
569 struct fsl_pcib_softc *sc = device_get_softc(dev);
571 if (bus == sc->sc_busnr && !sc->sc_pcie &&
572 slot < PCI_SLOT_FIRST)
574 fsl_pcib_cfgwrite(sc, bus, slot, func, reg, val, bytes);
578 fsl_pcib_inbound(struct fsl_pcib_softc *sc, int wnd, int tgt, uint64_t start,
579 uint64_t size, uint64_t pci_start)
581 uint32_t attr, bar, tar;
583 KASSERT(wnd > 0, ("%s: inbound window 0 is invalid", __func__));
591 case PIWAR_TRGT_LOCAL:
592 attr |= (ffsl(size) - 2);
594 attr |= (tgt << PIWAR_TRGT_S);
598 bar = pci_start >> 12;
600 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_PITAR(wnd), tar);
601 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_PIWBEAR(wnd), 0);
602 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_PIWBAR(wnd), bar);
603 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_PIWAR(wnd), attr);
607 fsl_pcib_outbound(struct fsl_pcib_softc *sc, int wnd, int res, uint64_t start,
608 uint64_t size, uint64_t pci_start)
610 uint32_t attr, bar, tar;
614 attr = 0x80044000 | (ffsll(size) - 2);
617 attr = 0x80088000 | (ffsll(size) - 2);
624 tar = pci_start >> 12;
626 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_POTAR(wnd), tar);
627 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_POTEAR(wnd), 0);
628 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_POWBAR(wnd), bar);
629 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_POWAR(wnd), attr);
633 fsl_pcib_err_init(device_t dev)
635 struct fsl_pcib_softc *sc;
636 uint16_t sec_stat, dsr;
637 uint32_t dcr, err_en;
639 sc = device_get_softc(dev);
641 sec_stat = fsl_pcib_cfgread(sc, 0, 0, 0, PCIR_SECSTAT_1, 2);
643 fsl_pcib_cfgwrite(sc, 0, 0, 0, PCIR_SECSTAT_1, 0xffff, 2);
645 /* Clear error bits */
646 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_PEX_MES_IER,
648 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_PEX_MES_DR,
650 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_PEX_ERR_DR,
653 dsr = fsl_pcib_cfgread(sc, 0, 0, 0,
654 sc->sc_pcie_capreg + PCIER_DEVICE_STA, 2);
656 fsl_pcib_cfgwrite(sc, 0, 0, 0,
657 sc->sc_pcie_capreg + PCIER_DEVICE_STA,
660 /* Enable all errors reporting */
662 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_PEX_ERR_EN,
665 /* Enable error reporting: URR, FER, NFER */
666 dcr = fsl_pcib_cfgread(sc, 0, 0, 0,
667 sc->sc_pcie_capreg + PCIER_DEVICE_CTL, 4);
668 dcr |= PCIEM_CTL_URR_ENABLE | PCIEM_CTL_FER_ENABLE |
669 PCIEM_CTL_NFER_ENABLE;
670 fsl_pcib_cfgwrite(sc, 0, 0, 0,
671 sc->sc_pcie_capreg + PCIER_DEVICE_CTL, dcr, 4);
676 fsl_pcib_detach(device_t dev)
678 struct fsl_pcib_softc *sc;
680 sc = device_get_softc(dev);
682 mtx_destroy(&sc->sc_cfg_mtx);
684 return (bus_generic_detach(dev));
688 fsl_pcib_decode_win(phandle_t node, struct fsl_pcib_softc *sc)
695 fsl_pcib_outbound(sc, 0, -1, 0, 0, 0);
698 * Configure LAW decode windows.
700 error = law_pci_target(sc->sc_res, &sc->sc_iomem_target,
701 &sc->sc_ioport_target);
703 device_printf(dev, "could not retrieve PCI LAW target info\n");
707 for (i = 0; i < sc->pci_sc.sc_nrange; i++) {
708 switch (sc->pci_sc.sc_range[i].pci_hi &
709 OFW_PCI_PHYS_HI_SPACEMASK) {
710 case OFW_PCI_PHYS_HI_SPACE_CONFIG:
712 case OFW_PCI_PHYS_HI_SPACE_IO:
713 trgt = sc->sc_ioport_target;
714 fsl_pcib_outbound(sc, 2, SYS_RES_IOPORT,
715 sc->pci_sc.sc_range[i].host,
716 sc->pci_sc.sc_range[i].size,
717 sc->pci_sc.sc_range[i].pci);
718 sc->sc_ioport_start = sc->pci_sc.sc_range[i].pci;
719 sc->sc_ioport_end = sc->pci_sc.sc_range[i].pci +
720 sc->pci_sc.sc_range[i].size - 1;
722 case OFW_PCI_PHYS_HI_SPACE_MEM32:
723 case OFW_PCI_PHYS_HI_SPACE_MEM64:
724 trgt = sc->sc_iomem_target;
725 fsl_pcib_outbound(sc, 1, SYS_RES_MEMORY,
726 sc->pci_sc.sc_range[i].host,
727 sc->pci_sc.sc_range[i].size,
728 sc->pci_sc.sc_range[i].pci);
729 sc->sc_iomem_start = sc->pci_sc.sc_range[i].pci;
730 sc->sc_iomem_end = sc->pci_sc.sc_range[i].pci +
731 sc->pci_sc.sc_range[i].size - 1;
734 panic("Unknown range type %#x\n",
735 sc->pci_sc.sc_range[i].pci_hi &
736 OFW_PCI_PHYS_HI_SPACEMASK);
738 error = law_enable(trgt, sc->pci_sc.sc_range[i].host,
739 sc->pci_sc.sc_range[i].size);
741 device_printf(dev, "could not program LAW for range "
748 * Set outbout and inbound windows.
750 fsl_pcib_outbound(sc, 3, -1, 0, 0, 0);
751 fsl_pcib_outbound(sc, 4, -1, 0, 0, 0);
753 fsl_pcib_inbound(sc, 1, -1, 0, 0, 0);
754 fsl_pcib_inbound(sc, 2, -1, 0, 0, 0);
755 fsl_pcib_inbound(sc, 3, PIWAR_TRGT_LOCAL, 0,
758 /* Direct-map the CCSR for MSIs. */
759 /* Freescale PCIe 2.x has a dedicated MSI window. */
760 /* inbound window 8 makes it hit 0xD00 offset, the MSI window. */
761 if (sc->sc_ip_maj >= 2)
762 fsl_pcib_inbound(sc, 8, PIWAR_TRGT_CCSR, ccsrbar_pa,
763 ccsrbar_size, ccsrbar_pa);
765 fsl_pcib_inbound(sc, 1, PIWAR_TRGT_CCSR, ccsrbar_pa,
766 ccsrbar_size, ccsrbar_pa);
771 static int fsl_pcib_alloc_msi(device_t dev, device_t child,
772 int count, int maxcount, int *irqs)
777 if (msi_vmem == NULL)
780 err = vmem_xalloc(msi_vmem, count, powerof2(count), 0, 0,
781 VMEM_ADDR_MIN, VMEM_ADDR_MAX, M_BESTFIT | M_WAITOK, &start);
786 for (i = 0; i < count; i++)
792 static int fsl_pcib_release_msi(device_t dev, device_t child,
793 int count, int *irqs)
795 if (msi_vmem == NULL)
798 vmem_xfree(msi_vmem, irqs[0], count);
802 static int fsl_pcib_alloc_msix(device_t dev, device_t child, int *irq)
804 return (fsl_pcib_alloc_msi(dev, child, 1, 1, irq));
807 static int fsl_pcib_release_msix(device_t dev, device_t child, int irq)
809 return (fsl_pcib_release_msi(dev, child, 1, &irq));
812 static int fsl_pcib_map_msi(device_t dev, device_t child,
813 int irq, uint64_t *addr, uint32_t *data)
815 struct fsl_msi_map *mp;
817 SLIST_FOREACH(mp, &fsl_msis, slist) {
818 if (irq >= mp->irq_base && irq < mp->irq_base + FSL_NUM_MSIS)
826 *addr = ccsrbar_pa + mp->target;
832 * Linux device trees put the msi@<x> as children of the SoC, with ranges based
833 * on the CCSR. Since rman doesn't permit overlapping or sub-ranges between
834 * devices (bus_space_subregion(9) could do it, but let's not touch the PIC
835 * driver just to allocate a subregion for a sibling driver). This driver will
836 * use ccsr_write() and ccsr_read() instead.
839 #define FSL_NUM_IRQS 8
840 #define FSL_NUM_MSI_PER_IRQ 32
841 #define FSL_MSI_TARGET 0x140
843 struct fsl_msi_softc {
845 vm_offset_t sc_target;
847 struct fsl_msi_map sc_map;
849 /* This struct gets passed as the filter private data. */
850 struct fsl_msi_softc *sc_ptr; /* Pointer back to softc. */
851 struct resource *res;
854 int vectors[FSL_NUM_MSI_PER_IRQ];
856 } sc_msi_irq[FSL_NUM_IRQS];
860 fsl_msi_intr_filter(void *priv)
862 struct fsl_msi_irq *data = priv;
866 reg = ccsr_read4(ccsrbar_va + data->reg);
870 powerpc_dispatch_intr(data->vectors[i], NULL);
875 return (FILTER_HANDLED);
879 fsl_msi_probe(device_t dev)
881 if (!ofw_bus_is_compatible(dev, "fsl,mpic-msi"))
884 device_set_desc(dev, "Freescale MSI");
886 return (BUS_PROBE_DEFAULT);
890 fsl_msi_attach(device_t dev)
892 struct fsl_msi_softc *sc;
893 struct fsl_msi_irq *irq;
896 sc = device_get_softc(dev);
898 if (msi_vmem == NULL)
899 msi_vmem = vmem_create("MPIC MSI", 0, 0, 1, 0, M_BESTFIT | M_WAITOK);
901 /* Manually play with resource entries. */
902 sc->sc_base = bus_get_resource_start(dev, SYS_RES_MEMORY, 0);
903 sc->sc_map.target = bus_get_resource_start(dev, SYS_RES_MEMORY, 1);
905 if (sc->sc_map.target == 0)
906 sc->sc_map.target = sc->sc_base + FSL_MSI_TARGET;
908 for (i = 0; i < FSL_NUM_IRQS; i++) {
909 irq = &sc->sc_msi_irq[i];
911 irq->reg = sc->sc_base + 16 * i;
912 irq->res = bus_alloc_resource_any(dev, SYS_RES_IRQ,
913 &irq->irq, RF_ACTIVE);
914 bus_setup_intr(dev, irq->res, INTR_TYPE_MISC | INTR_MPSAFE,
915 fsl_msi_intr_filter, NULL, irq, &irq->cookie);
917 sc->sc_map.irq_base = powerpc_register_pic(dev, ofw_bus_get_node(dev),
920 /* Let vmem and the IRQ subsystem work their magic for allocations. */
921 vmem_add(msi_vmem, sc->sc_map.irq_base, FSL_NUM_MSIS, M_WAITOK);
923 SLIST_INSERT_HEAD(&fsl_msis, &sc->sc_map, slist);
929 fsl_msi_enable(device_t dev, u_int irq, u_int vector, void **priv)
931 struct fsl_msi_softc *sc;
932 struct fsl_msi_irq *irqd;
934 sc = device_get_softc(dev);
936 irqd = &sc->sc_msi_irq[irq / FSL_NUM_MSI_PER_IRQ];
937 irqd->vectors[irq % FSL_NUM_MSI_PER_IRQ] = vector;
940 static device_method_t fsl_msi_methods[] = {
941 DEVMETHOD(device_probe, fsl_msi_probe),
942 DEVMETHOD(device_attach, fsl_msi_attach),
944 DEVMETHOD(pic_enable, fsl_msi_enable),
948 static driver_t fsl_msi_driver = {
951 sizeof(struct fsl_msi_softc)
954 EARLY_DRIVER_MODULE(fsl_msi, simplebus, fsl_msi_driver, 0, 0,
955 BUS_PASS_INTERRUPT + 1);