2 * SPDX-License-Identifier: BSD-3-Clause
4 * Copyright 2006-2007 by Juniper Networks.
5 * Copyright 2008 Semihalf.
6 * Copyright 2010 The FreeBSD Foundation
9 * Portions of this software were developed by Semihalf
10 * under sponsorship from the FreeBSD Foundation.
12 * Redistribution and use in source and binary forms, with or without
13 * modification, are permitted provided that the following conditions
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in the
19 * documentation and/or other materials provided with the distribution.
20 * 3. The name of the author may not be used to endorse or promote products
21 * derived from this software without specific prior written permission.
23 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
26 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
28 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
30 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
31 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
35 * From: FreeBSD: src/sys/powerpc/mpc85xx/pci_ocp.c,v 1.9 2010/03/23 23:46:28 marcel
38 #include <sys/cdefs.h>
39 #include <sys/param.h>
40 #include <sys/systm.h>
42 #include <sys/sockio.h>
44 #include <sys/malloc.h>
45 #include <sys/kernel.h>
46 #include <sys/module.h>
47 #include <sys/socket.h>
48 #include <sys/queue.h>
51 #include <sys/mutex.h>
52 #include <sys/queue.h>
54 #include <sys/endian.h>
60 #include <dev/ofw/ofw_pci.h>
61 #include <dev/ofw/ofw_bus.h>
62 #include <dev/ofw/ofw_bus_subr.h>
63 #include <dev/ofw/ofwpci.h>
64 #include <dev/pci/pcivar.h>
65 #include <dev/pci/pcireg.h>
66 #include <dev/pci/pcib_private.h>
68 #include "ofw_bus_if.h"
72 #include <machine/resource.h>
73 #include <machine/bus.h>
74 #include <machine/intr_machdep.h>
76 #include <powerpc/mpc85xx/mpc85xx.h>
78 #define REG_CFG_ADDR 0x0000
79 #define CONFIG_ACCESS_ENABLE 0x80000000
81 #define REG_CFG_DATA 0x0004
82 #define REG_INT_ACK 0x0008
84 #define REG_PEX_IP_BLK_REV1 0x0bf8
85 #define IP_MJ_M 0x0000ff00
87 #define IP_MN_M 0x000000ff
90 #define REG_POTAR(n) (0x0c00 + 0x20 * (n))
91 #define REG_POTEAR(n) (0x0c04 + 0x20 * (n))
92 #define REG_POWBAR(n) (0x0c08 + 0x20 * (n))
93 #define REG_POWAR(n) (0x0c10 + 0x20 * (n))
95 #define REG_PITAR(n) (0x0e00 - 0x20 * (n))
96 #define REG_PIWBAR(n) (0x0e08 - 0x20 * (n))
97 #define REG_PIWBEAR(n) (0x0e0c - 0x20 * (n))
98 #define REG_PIWAR(n) (0x0e10 - 0x20 * (n))
99 #define PIWAR_EN 0x80000000
100 #define PIWAR_PF 0x40000000
101 #define PIWAR_TRGT_M 0x00f00000
102 #define PIWAR_TRGT_S 20
103 #define PIWAR_TRGT_CCSR 0xe
104 #define PIWAR_TRGT_LOCAL 0xf
106 #define REG_PEX_MES_DR 0x0020
107 #define REG_PEX_MES_IER 0x0028
108 #define REG_PEX_ERR_DR 0x0e00
109 #define REG_PEX_ERR_EN 0x0e08
111 #define REG_PEX_ERR_DR 0x0e00
112 #define REG_PEX_ERR_DR_ME 0x80000000
113 #define REG_PEX_ERR_DR_PCT 0x800000
114 #define REG_PEX_ERR_DR_PAT 0x400000
115 #define REG_PEX_ERR_DR_PCAC 0x200000
116 #define REG_PEX_ERR_DR_PNM 0x100000
117 #define REG_PEX_ERR_DR_CDNSC 0x80000
118 #define REG_PEX_ERR_DR_CRSNC 0x40000
119 #define REG_PEX_ERR_DR_ICCA 0x20000
120 #define REG_PEX_ERR_DR_IACA 0x10000
121 #define REG_PEX_ERR_DR_CRST 0x8000
122 #define REG_PEX_ERR_DR_MIS 0x4000
123 #define REG_PEX_ERR_DR_IOIS 0x2000
124 #define REG_PEX_ERR_DR_CIS 0x1000
125 #define REG_PEX_ERR_DR_CIEP 0x800
126 #define REG_PEX_ERR_DR_IOIEP 0x400
127 #define REG_PEX_ERR_DR_OAC 0x200
128 #define REG_PEX_ERR_DR_IOIA 0x100
129 #define REG_PEX_ERR_DR_IMBA 0x80
130 #define REG_PEX_ERR_DR_IIOBA 0x40
131 #define REG_PEX_ERR_DR_LDDE 0x20
132 #define REG_PEX_ERR_EN 0x0e08
134 #define PCIR_LTSSM 0x404
135 #define LTSSM_STAT_L0 0x16
137 #define DEVFN(b, s, f) ((b << 16) | (s << 8) | f)
139 #define FSL_NUM_MSIS 256 /* 8 registers of 32 bits (8 hardware IRQs) */
140 #define PCI_SLOT_FIRST 0x1 /* used to be 0x11 but qemu-ppce500 starts from 0x1 */
142 struct fsl_pcib_softc {
143 struct ofw_pci_softc pci_sc;
145 struct mtx sc_cfg_mtx;
150 bus_addr_t sc_iomem_start, sc_iomem_end;
151 int sc_ioport_target;
152 bus_addr_t sc_ioport_start, sc_ioport_end;
154 struct resource *sc_res;
155 bus_space_handle_t sc_bsh;
156 bus_space_tag_t sc_bst;
159 struct resource *sc_irq_res;
164 uint8_t sc_pcie_capreg; /* PCI-E Capability Reg Set */
167 struct fsl_pcib_err_dr {
169 uint32_t err_dr_mask;
173 SLIST_ENTRY(fsl_msi_map) slist;
178 SLIST_HEAD(msi_head, fsl_msi_map) fsl_msis = SLIST_HEAD_INITIALIZER(msi_head);
180 static const struct fsl_pcib_err_dr pci_err[] = {
181 {"ME", REG_PEX_ERR_DR_ME},
182 {"PCT", REG_PEX_ERR_DR_PCT},
183 {"PAT", REG_PEX_ERR_DR_PAT},
184 {"PCAC", REG_PEX_ERR_DR_PCAC},
185 {"PNM", REG_PEX_ERR_DR_PNM},
186 {"CDNSC", REG_PEX_ERR_DR_CDNSC},
187 {"CRSNC", REG_PEX_ERR_DR_CRSNC},
188 {"ICCA", REG_PEX_ERR_DR_ICCA},
189 {"IACA", REG_PEX_ERR_DR_IACA},
190 {"CRST", REG_PEX_ERR_DR_CRST},
191 {"MIS", REG_PEX_ERR_DR_MIS},
192 {"IOIS", REG_PEX_ERR_DR_IOIS},
193 {"CIS", REG_PEX_ERR_DR_CIS},
194 {"CIEP", REG_PEX_ERR_DR_CIEP},
195 {"IOIEP", REG_PEX_ERR_DR_IOIEP},
196 {"OAC", REG_PEX_ERR_DR_OAC},
197 {"IOIA", REG_PEX_ERR_DR_IOIA},
198 {"IMBA", REG_PEX_ERR_DR_IMBA},
199 {"IIOBA", REG_PEX_ERR_DR_IIOBA},
200 {"LDDE", REG_PEX_ERR_DR_LDDE}
203 /* Local forward declerations. */
204 static uint32_t fsl_pcib_cfgread(struct fsl_pcib_softc *, u_int, u_int, u_int,
206 static void fsl_pcib_cfgwrite(struct fsl_pcib_softc *, u_int, u_int, u_int,
207 u_int, uint32_t, int);
208 static int fsl_pcib_decode_win(phandle_t, struct fsl_pcib_softc *);
209 static void fsl_pcib_err_init(device_t);
210 static void fsl_pcib_inbound(struct fsl_pcib_softc *, int, int, uint64_t,
212 static void fsl_pcib_outbound(struct fsl_pcib_softc *, int, int, uint64_t,
215 /* Forward declerations. */
216 static int fsl_pcib_attach(device_t);
217 static int fsl_pcib_detach(device_t);
218 static int fsl_pcib_probe(device_t);
220 static int fsl_pcib_maxslots(device_t);
221 static uint32_t fsl_pcib_read_config(device_t, u_int, u_int, u_int, u_int, int);
222 static void fsl_pcib_write_config(device_t, u_int, u_int, u_int, u_int,
224 static int fsl_pcib_alloc_msi(device_t dev, device_t child,
225 int count, int maxcount, int *irqs);
226 static int fsl_pcib_release_msi(device_t dev, device_t child,
227 int count, int *irqs);
228 static int fsl_pcib_alloc_msix(device_t dev, device_t child, int *irq);
229 static int fsl_pcib_release_msix(device_t dev, device_t child, int irq);
230 static int fsl_pcib_map_msi(device_t dev, device_t child,
231 int irq, uint64_t *addr, uint32_t *data);
233 static vmem_t *msi_vmem; /* Global MSI vmem, holds all MSI ranges. */
236 * Bus interface definitions.
238 static device_method_t fsl_pcib_methods[] = {
239 /* Device interface */
240 DEVMETHOD(device_probe, fsl_pcib_probe),
241 DEVMETHOD(device_attach, fsl_pcib_attach),
242 DEVMETHOD(device_detach, fsl_pcib_detach),
245 DEVMETHOD(pcib_maxslots, fsl_pcib_maxslots),
246 DEVMETHOD(pcib_read_config, fsl_pcib_read_config),
247 DEVMETHOD(pcib_write_config, fsl_pcib_write_config),
248 DEVMETHOD(pcib_alloc_msi, fsl_pcib_alloc_msi),
249 DEVMETHOD(pcib_release_msi, fsl_pcib_release_msi),
250 DEVMETHOD(pcib_alloc_msix, fsl_pcib_alloc_msix),
251 DEVMETHOD(pcib_release_msix, fsl_pcib_release_msix),
252 DEVMETHOD(pcib_map_msi, fsl_pcib_map_msi),
257 DEFINE_CLASS_1(pcib, fsl_pcib_driver, fsl_pcib_methods,
258 sizeof(struct fsl_pcib_softc), ofw_pcib_driver);
259 EARLY_DRIVER_MODULE(pcib, ofwbus, fsl_pcib_driver, 0, 0, BUS_PASS_BUS);
262 fsl_pcib_err_intr(void *v)
264 struct fsl_pcib_softc *sc;
266 uint32_t err_reg, clear_reg;
270 sc = device_get_softc(dev);
273 err_reg = bus_space_read_4(sc->sc_bst, sc->sc_bsh, REG_PEX_ERR_DR);
275 /* Check which one error occurred */
276 for (i = 0; i < sizeof(pci_err)/sizeof(struct fsl_pcib_err_dr); i++) {
277 if (err_reg & pci_err[i].err_dr_mask) {
278 device_printf(dev, "PCI %d: report %s error\n",
279 device_get_unit(dev), pci_err[i].msg);
280 clear_reg |= pci_err[i].err_dr_mask;
284 /* Clear pending errors */
285 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_PEX_ERR_DR, clear_reg);
289 fsl_pcib_probe(device_t dev)
292 if (ofw_bus_get_type(dev) == NULL ||
293 strcmp(ofw_bus_get_type(dev), "pci") != 0)
296 if (!(ofw_bus_is_compatible(dev, "fsl,mpc8540-pci") ||
297 ofw_bus_is_compatible(dev, "fsl,mpc8540-pcie") ||
298 ofw_bus_is_compatible(dev, "fsl,mpc8548-pcie") ||
299 ofw_bus_is_compatible(dev, "fsl,p5020-pcie") ||
300 ofw_bus_is_compatible(dev, "fsl,p5040-pcie") ||
301 ofw_bus_is_compatible(dev, "fsl,qoriq-pcie-v2.2") ||
302 ofw_bus_is_compatible(dev, "fsl,qoriq-pcie-v2.4") ||
303 ofw_bus_is_compatible(dev, "fsl,qoriq-pcie")))
306 device_set_desc(dev, "Freescale Integrated PCI/PCI-E Controller");
307 return (BUS_PROBE_DEFAULT);
311 fsl_pcib_attach(device_t dev)
313 struct fsl_pcib_softc *sc;
315 uint32_t cfgreg, brctl, ipreg;
316 int do_reset, error, rid;
317 uint8_t ltssm, capptr;
319 sc = device_get_softc(dev);
323 sc->sc_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->sc_rid,
325 if (sc->sc_res == NULL) {
326 device_printf(dev, "could not map I/O memory\n");
329 sc->sc_bst = rman_get_bustag(sc->sc_res);
330 sc->sc_bsh = rman_get_bushandle(sc->sc_res);
333 ipreg = bus_read_4(sc->sc_res, REG_PEX_IP_BLK_REV1);
334 sc->sc_ip_min = (ipreg & IP_MN_M) >> IP_MN_S;
335 sc->sc_ip_maj = (ipreg & IP_MJ_M) >> IP_MJ_S;
336 mtx_init(&sc->sc_cfg_mtx, "pcicfg", NULL, MTX_SPIN);
338 cfgreg = fsl_pcib_cfgread(sc, 0, 0, 0, PCIR_VENDOR, 2);
339 if (cfgreg != 0x1057 && cfgreg != 0x1957)
342 capptr = fsl_pcib_cfgread(sc, 0, 0, 0, PCIR_CAP_PTR, 1);
343 while (capptr != 0) {
344 cfgreg = fsl_pcib_cfgread(sc, 0, 0, 0, capptr, 2);
345 switch (cfgreg & 0xff) {
350 sc->sc_pcie_capreg = capptr;
353 capptr = (cfgreg >> 8) & 0xff;
356 node = ofw_bus_get_node(dev);
359 * Initialize generic OF PCI interface (ranges, etc.)
362 error = ofw_pcib_init(dev);
367 * Configure decode windows for PCI(E) access.
369 if (fsl_pcib_decode_win(node, sc) != 0)
372 cfgreg = fsl_pcib_cfgread(sc, 0, 0, 0, PCIR_COMMAND, 2);
373 cfgreg |= PCIM_CMD_SERRESPEN | PCIM_CMD_BUSMASTEREN | PCIM_CMD_MEMEN |
375 fsl_pcib_cfgwrite(sc, 0, 0, 0, PCIR_COMMAND, cfgreg, 2);
378 resource_int_value("pcib", device_get_unit(dev), "reset", &do_reset);
380 /* Reset the bus. Needed for Radeon video cards. */
381 brctl = fsl_pcib_read_config(sc->sc_dev, 0, 0, 0,
382 PCIR_BRIDGECTL_1, 1);
383 brctl |= PCIB_BCR_SECBUS_RESET;
384 fsl_pcib_write_config(sc->sc_dev, 0, 0, 0,
385 PCIR_BRIDGECTL_1, brctl, 1);
387 brctl &= ~PCIB_BCR_SECBUS_RESET;
388 fsl_pcib_write_config(sc->sc_dev, 0, 0, 0,
389 PCIR_BRIDGECTL_1, brctl, 1);
394 ltssm = fsl_pcib_cfgread(sc, 0, 0, 0, PCIR_LTSSM, 1);
395 if (ltssm < LTSSM_STAT_L0) {
397 printf("PCI %d: no PCIE link, skipping\n",
398 device_get_unit(dev));
405 sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
406 RF_ACTIVE | RF_SHAREABLE);
407 if (sc->sc_irq_res == NULL) {
408 error = fsl_pcib_detach(dev);
411 "Detach of the driver failed with error %d\n",
417 /* Setup interrupt handler */
418 error = bus_setup_intr(dev, sc->sc_irq_res, INTR_TYPE_MISC | INTR_MPSAFE,
419 NULL, fsl_pcib_err_intr, dev, &sc->sc_ih);
421 device_printf(dev, "Could not setup irq, %d\n", error);
423 error = fsl_pcib_detach(dev);
426 "Detach of the driver failed with error %d\n",
432 fsl_pcib_err_init(dev);
434 return (ofw_pcib_attach(dev));
441 fsl_pcib_cfgread(struct fsl_pcib_softc *sc, u_int bus, u_int slot, u_int func,
442 u_int reg, int bytes)
446 addr = CONFIG_ACCESS_ENABLE;
447 addr |= (bus & 0xff) << 16;
448 addr |= (slot & 0x1f) << 11;
449 addr |= (func & 0x7) << 8;
452 addr |= (reg & 0xf00) << 16;
454 mtx_lock_spin(&sc->sc_cfg_mtx);
455 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_CFG_ADDR, addr);
459 data = bus_space_read_1(sc->sc_bst, sc->sc_bsh,
460 REG_CFG_DATA + (reg & 3));
463 data = le16toh(bus_space_read_2(sc->sc_bst, sc->sc_bsh,
464 REG_CFG_DATA + (reg & 2)));
467 data = le32toh(bus_space_read_4(sc->sc_bst, sc->sc_bsh,
474 mtx_unlock_spin(&sc->sc_cfg_mtx);
479 fsl_pcib_cfgwrite(struct fsl_pcib_softc *sc, u_int bus, u_int slot, u_int func,
480 u_int reg, uint32_t data, int bytes)
484 addr = CONFIG_ACCESS_ENABLE;
485 addr |= (bus & 0xff) << 16;
486 addr |= (slot & 0x1f) << 11;
487 addr |= (func & 0x7) << 8;
490 addr |= (reg & 0xf00) << 16;
492 mtx_lock_spin(&sc->sc_cfg_mtx);
493 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_CFG_ADDR, addr);
497 bus_space_write_1(sc->sc_bst, sc->sc_bsh,
498 REG_CFG_DATA + (reg & 3), data);
501 bus_space_write_2(sc->sc_bst, sc->sc_bsh,
502 REG_CFG_DATA + (reg & 2), htole16(data));
505 bus_space_write_4(sc->sc_bst, sc->sc_bsh,
506 REG_CFG_DATA, htole32(data));
509 mtx_unlock_spin(&sc->sc_cfg_mtx);
514 dump(struct fsl_pcib_softc *sc)
518 #define RD(o) bus_space_read_4(sc->sc_bst, sc->sc_bsh, o)
519 for (i = 0; i < 5; i++) {
520 printf("POTAR%u =0x%08x\n", i, RD(REG_POTAR(i)));
521 printf("POTEAR%u =0x%08x\n", i, RD(REG_POTEAR(i)));
522 printf("POWBAR%u =0x%08x\n", i, RD(REG_POWBAR(i)));
523 printf("POWAR%u =0x%08x\n", i, RD(REG_POWAR(i)));
526 for (i = 1; i < 4; i++) {
527 printf("PITAR%u =0x%08x\n", i, RD(REG_PITAR(i)));
528 printf("PIWBAR%u =0x%08x\n", i, RD(REG_PIWBAR(i)));
529 printf("PIWBEAR%u=0x%08x\n", i, RD(REG_PIWBEAR(i)));
530 printf("PIWAR%u =0x%08x\n", i, RD(REG_PIWAR(i)));
535 for (i = 0; i < 0x48; i += 4) {
536 printf("cfg%02x=0x%08x\n", i, fsl_pcib_cfgread(sc, 0, 0, 0,
543 fsl_pcib_maxslots(device_t dev)
545 struct fsl_pcib_softc *sc = device_get_softc(dev);
547 return ((sc->sc_pcie) ? 0 : PCI_SLOTMAX);
551 fsl_pcib_read_config(device_t dev, u_int bus, u_int slot, u_int func,
552 u_int reg, int bytes)
554 struct fsl_pcib_softc *sc = device_get_softc(dev);
556 if (bus == sc->sc_busnr && !sc->sc_pcie &&
557 slot < PCI_SLOT_FIRST)
560 return (fsl_pcib_cfgread(sc, bus, slot, func, reg, bytes));
564 fsl_pcib_write_config(device_t dev, u_int bus, u_int slot, u_int func,
565 u_int reg, uint32_t val, int bytes)
567 struct fsl_pcib_softc *sc = device_get_softc(dev);
569 if (bus == sc->sc_busnr && !sc->sc_pcie &&
570 slot < PCI_SLOT_FIRST)
572 fsl_pcib_cfgwrite(sc, bus, slot, func, reg, val, bytes);
576 fsl_pcib_inbound(struct fsl_pcib_softc *sc, int wnd, int tgt, uint64_t start,
577 uint64_t size, uint64_t pci_start)
579 uint32_t attr, bar, tar;
581 KASSERT(wnd > 0, ("%s: inbound window 0 is invalid", __func__));
589 case PIWAR_TRGT_LOCAL:
590 attr |= (ffsl(size) - 2);
592 attr |= (tgt << PIWAR_TRGT_S);
596 bar = pci_start >> 12;
598 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_PITAR(wnd), tar);
599 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_PIWBEAR(wnd), 0);
600 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_PIWBAR(wnd), bar);
601 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_PIWAR(wnd), attr);
605 fsl_pcib_outbound(struct fsl_pcib_softc *sc, int wnd, int res, uint64_t start,
606 uint64_t size, uint64_t pci_start)
608 uint32_t attr, bar, tar;
612 attr = 0x80044000 | (ffsll(size) - 2);
615 attr = 0x80088000 | (ffsll(size) - 2);
622 tar = pci_start >> 12;
624 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_POTAR(wnd), tar);
625 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_POTEAR(wnd), 0);
626 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_POWBAR(wnd), bar);
627 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_POWAR(wnd), attr);
631 fsl_pcib_err_init(device_t dev)
633 struct fsl_pcib_softc *sc;
634 uint16_t sec_stat, dsr;
635 uint32_t dcr, err_en;
637 sc = device_get_softc(dev);
639 sec_stat = fsl_pcib_cfgread(sc, 0, 0, 0, PCIR_SECSTAT_1, 2);
641 fsl_pcib_cfgwrite(sc, 0, 0, 0, PCIR_SECSTAT_1, 0xffff, 2);
643 /* Clear error bits */
644 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_PEX_MES_IER,
646 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_PEX_MES_DR,
648 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_PEX_ERR_DR,
651 dsr = fsl_pcib_cfgread(sc, 0, 0, 0,
652 sc->sc_pcie_capreg + PCIER_DEVICE_STA, 2);
654 fsl_pcib_cfgwrite(sc, 0, 0, 0,
655 sc->sc_pcie_capreg + PCIER_DEVICE_STA,
658 /* Enable all errors reporting */
660 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_PEX_ERR_EN,
663 /* Enable error reporting: URR, FER, NFER */
664 dcr = fsl_pcib_cfgread(sc, 0, 0, 0,
665 sc->sc_pcie_capreg + PCIER_DEVICE_CTL, 4);
666 dcr |= PCIEM_CTL_URR_ENABLE | PCIEM_CTL_FER_ENABLE |
667 PCIEM_CTL_NFER_ENABLE;
668 fsl_pcib_cfgwrite(sc, 0, 0, 0,
669 sc->sc_pcie_capreg + PCIER_DEVICE_CTL, dcr, 4);
674 fsl_pcib_detach(device_t dev)
676 struct fsl_pcib_softc *sc;
678 sc = device_get_softc(dev);
680 mtx_destroy(&sc->sc_cfg_mtx);
682 return (bus_generic_detach(dev));
686 fsl_pcib_decode_win(phandle_t node, struct fsl_pcib_softc *sc)
693 fsl_pcib_outbound(sc, 0, -1, 0, 0, 0);
696 * Configure LAW decode windows.
698 error = law_pci_target(sc->sc_res, &sc->sc_iomem_target,
699 &sc->sc_ioport_target);
701 device_printf(dev, "could not retrieve PCI LAW target info\n");
705 for (i = 0; i < sc->pci_sc.sc_nrange; i++) {
706 switch (sc->pci_sc.sc_range[i].pci_hi &
707 OFW_PCI_PHYS_HI_SPACEMASK) {
708 case OFW_PCI_PHYS_HI_SPACE_CONFIG:
710 case OFW_PCI_PHYS_HI_SPACE_IO:
711 trgt = sc->sc_ioport_target;
712 fsl_pcib_outbound(sc, 2, SYS_RES_IOPORT,
713 sc->pci_sc.sc_range[i].host,
714 sc->pci_sc.sc_range[i].size,
715 sc->pci_sc.sc_range[i].pci);
716 sc->sc_ioport_start = sc->pci_sc.sc_range[i].pci;
717 sc->sc_ioport_end = sc->pci_sc.sc_range[i].pci +
718 sc->pci_sc.sc_range[i].size - 1;
720 case OFW_PCI_PHYS_HI_SPACE_MEM32:
721 case OFW_PCI_PHYS_HI_SPACE_MEM64:
722 trgt = sc->sc_iomem_target;
723 fsl_pcib_outbound(sc, 1, SYS_RES_MEMORY,
724 sc->pci_sc.sc_range[i].host,
725 sc->pci_sc.sc_range[i].size,
726 sc->pci_sc.sc_range[i].pci);
727 sc->sc_iomem_start = sc->pci_sc.sc_range[i].pci;
728 sc->sc_iomem_end = sc->pci_sc.sc_range[i].pci +
729 sc->pci_sc.sc_range[i].size - 1;
732 panic("Unknown range type %#x\n",
733 sc->pci_sc.sc_range[i].pci_hi &
734 OFW_PCI_PHYS_HI_SPACEMASK);
736 error = law_enable(trgt, sc->pci_sc.sc_range[i].host,
737 sc->pci_sc.sc_range[i].size);
739 device_printf(dev, "could not program LAW for range "
746 * Set outbout and inbound windows.
748 fsl_pcib_outbound(sc, 3, -1, 0, 0, 0);
749 fsl_pcib_outbound(sc, 4, -1, 0, 0, 0);
751 fsl_pcib_inbound(sc, 1, -1, 0, 0, 0);
752 fsl_pcib_inbound(sc, 2, -1, 0, 0, 0);
753 fsl_pcib_inbound(sc, 3, PIWAR_TRGT_LOCAL, 0,
756 /* Direct-map the CCSR for MSIs. */
757 /* Freescale PCIe 2.x has a dedicated MSI window. */
758 /* inbound window 8 makes it hit 0xD00 offset, the MSI window. */
759 if (sc->sc_ip_maj >= 2)
760 fsl_pcib_inbound(sc, 8, PIWAR_TRGT_CCSR, ccsrbar_pa,
761 ccsrbar_size, ccsrbar_pa);
763 fsl_pcib_inbound(sc, 1, PIWAR_TRGT_CCSR, ccsrbar_pa,
764 ccsrbar_size, ccsrbar_pa);
769 static int fsl_pcib_alloc_msi(device_t dev, device_t child,
770 int count, int maxcount, int *irqs)
775 if (msi_vmem == NULL)
778 err = vmem_xalloc(msi_vmem, count, powerof2(count), 0, 0,
779 VMEM_ADDR_MIN, VMEM_ADDR_MAX, M_BESTFIT | M_WAITOK, &start);
784 for (i = 0; i < count; i++)
790 static int fsl_pcib_release_msi(device_t dev, device_t child,
791 int count, int *irqs)
793 if (msi_vmem == NULL)
796 vmem_xfree(msi_vmem, irqs[0], count);
800 static int fsl_pcib_alloc_msix(device_t dev, device_t child, int *irq)
802 return (fsl_pcib_alloc_msi(dev, child, 1, 1, irq));
805 static int fsl_pcib_release_msix(device_t dev, device_t child, int irq)
807 return (fsl_pcib_release_msi(dev, child, 1, &irq));
810 static int fsl_pcib_map_msi(device_t dev, device_t child,
811 int irq, uint64_t *addr, uint32_t *data)
813 struct fsl_msi_map *mp;
815 SLIST_FOREACH(mp, &fsl_msis, slist) {
816 if (irq >= mp->irq_base && irq < mp->irq_base + FSL_NUM_MSIS)
824 *addr = ccsrbar_pa + mp->target;
830 * Linux device trees put the msi@<x> as children of the SoC, with ranges based
831 * on the CCSR. Since rman doesn't permit overlapping or sub-ranges between
832 * devices (bus_space_subregion(9) could do it, but let's not touch the PIC
833 * driver just to allocate a subregion for a sibling driver). This driver will
834 * use ccsr_write() and ccsr_read() instead.
837 #define FSL_NUM_IRQS 8
838 #define FSL_NUM_MSI_PER_IRQ 32
839 #define FSL_MSI_TARGET 0x140
841 struct fsl_msi_softc {
843 vm_offset_t sc_target;
845 struct fsl_msi_map sc_map;
847 /* This struct gets passed as the filter private data. */
848 struct fsl_msi_softc *sc_ptr; /* Pointer back to softc. */
849 struct resource *res;
852 int vectors[FSL_NUM_MSI_PER_IRQ];
854 } sc_msi_irq[FSL_NUM_IRQS];
858 fsl_msi_intr_filter(void *priv)
860 struct fsl_msi_irq *data = priv;
864 reg = ccsr_read4(ccsrbar_va + data->reg);
868 powerpc_dispatch_intr(data->vectors[i], NULL);
873 return (FILTER_HANDLED);
877 fsl_msi_probe(device_t dev)
879 if (!ofw_bus_is_compatible(dev, "fsl,mpic-msi"))
882 device_set_desc(dev, "Freescale MSI");
884 return (BUS_PROBE_DEFAULT);
888 fsl_msi_attach(device_t dev)
890 struct fsl_msi_softc *sc;
891 struct fsl_msi_irq *irq;
894 sc = device_get_softc(dev);
896 if (msi_vmem == NULL)
897 msi_vmem = vmem_create("MPIC MSI", 0, 0, 1, 0, M_BESTFIT | M_WAITOK);
899 /* Manually play with resource entries. */
900 sc->sc_base = bus_get_resource_start(dev, SYS_RES_MEMORY, 0);
901 sc->sc_map.target = bus_get_resource_start(dev, SYS_RES_MEMORY, 1);
903 if (sc->sc_map.target == 0)
904 sc->sc_map.target = sc->sc_base + FSL_MSI_TARGET;
906 for (i = 0; i < FSL_NUM_IRQS; i++) {
907 irq = &sc->sc_msi_irq[i];
909 irq->reg = sc->sc_base + 16 * i;
910 irq->res = bus_alloc_resource_any(dev, SYS_RES_IRQ,
911 &irq->irq, RF_ACTIVE);
912 bus_setup_intr(dev, irq->res, INTR_TYPE_MISC | INTR_MPSAFE,
913 fsl_msi_intr_filter, NULL, irq, &irq->cookie);
915 sc->sc_map.irq_base = powerpc_register_pic(dev, ofw_bus_get_node(dev),
918 /* Let vmem and the IRQ subsystem work their magic for allocations. */
919 vmem_add(msi_vmem, sc->sc_map.irq_base, FSL_NUM_MSIS, M_WAITOK);
921 SLIST_INSERT_HEAD(&fsl_msis, &sc->sc_map, slist);
927 fsl_msi_enable(device_t dev, u_int irq, u_int vector, void **priv)
929 struct fsl_msi_softc *sc;
930 struct fsl_msi_irq *irqd;
932 sc = device_get_softc(dev);
934 irqd = &sc->sc_msi_irq[irq / FSL_NUM_MSI_PER_IRQ];
935 irqd->vectors[irq % FSL_NUM_MSI_PER_IRQ] = vector;
938 static device_method_t fsl_msi_methods[] = {
939 DEVMETHOD(device_probe, fsl_msi_probe),
940 DEVMETHOD(device_attach, fsl_msi_attach),
942 DEVMETHOD(pic_enable, fsl_msi_enable),
946 static driver_t fsl_msi_driver = {
949 sizeof(struct fsl_msi_softc)
952 EARLY_DRIVER_MODULE(fsl_msi, simplebus, fsl_msi_driver, 0, 0,
953 BUS_PASS_INTERRUPT + 1);