2 * Copyright 2006-2007 by Juniper Networks.
3 * Copyright 2008 Semihalf.
4 * Copyright 2010 The FreeBSD Foundation
7 * Portions of this software were developed by Semihalf
8 * under sponsorship from the FreeBSD Foundation.
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 * 3. The name of the author may not be used to endorse or promote products
19 * derived from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
26 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
27 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
28 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
29 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
33 * From: FreeBSD: src/sys/powerpc/mpc85xx/pci_ocp.c,v 1.9 2010/03/23 23:46:28 marcel
36 #include <sys/cdefs.h>
37 __FBSDID("$FreeBSD$");
39 #include <sys/param.h>
40 #include <sys/systm.h>
42 #include <sys/sockio.h>
44 #include <sys/malloc.h>
45 #include <sys/kernel.h>
46 #include <sys/module.h>
47 #include <sys/socket.h>
48 #include <sys/queue.h>
51 #include <sys/mutex.h>
53 #include <sys/endian.h>
58 #include <dev/ofw/ofw_pci.h>
59 #include <dev/ofw/ofw_bus.h>
60 #include <dev/ofw/ofw_bus_subr.h>
61 #include <dev/pci/pcivar.h>
62 #include <dev/pci/pcireg.h>
63 #include <dev/pci/pcib_private.h>
65 #include <powerpc/ofw/ofw_pci.h>
67 #include "ofw_bus_if.h"
70 #include <machine/resource.h>
71 #include <machine/bus.h>
72 #include <machine/intr_machdep.h>
74 #include <powerpc/mpc85xx/mpc85xx.h>
76 #define REG_CFG_ADDR 0x0000
77 #define CONFIG_ACCESS_ENABLE 0x80000000
79 #define REG_CFG_DATA 0x0004
80 #define REG_INT_ACK 0x0008
82 #define REG_POTAR(n) (0x0c00 + 0x20 * (n))
83 #define REG_POTEAR(n) (0x0c04 + 0x20 * (n))
84 #define REG_POWBAR(n) (0x0c08 + 0x20 * (n))
85 #define REG_POWAR(n) (0x0c10 + 0x20 * (n))
87 #define REG_PITAR(n) (0x0e00 - 0x20 * (n))
88 #define REG_PIWBAR(n) (0x0e08 - 0x20 * (n))
89 #define REG_PIWBEAR(n) (0x0e0c - 0x20 * (n))
90 #define REG_PIWAR(n) (0x0e10 - 0x20 * (n))
92 #define REG_PEX_MES_DR 0x0020
93 #define REG_PEX_MES_IER 0x0028
94 #define REG_PEX_ERR_DR 0x0e00
95 #define REG_PEX_ERR_EN 0x0e08
97 #define PCIR_LTSSM 0x404
98 #define LTSSM_STAT_L0 0x16
100 #define DEVFN(b, s, f) ((b << 16) | (s << 8) | f)
102 struct fsl_pcib_softc {
103 struct ofw_pci_softc pci_sc;
107 bus_addr_t sc_iomem_alloc, sc_iomem_start, sc_iomem_end;
108 int sc_ioport_target;
109 bus_addr_t sc_ioport_alloc, sc_ioport_start, sc_ioport_end;
111 struct resource *sc_res;
112 bus_space_handle_t sc_bsh;
113 bus_space_tag_t sc_bst;
118 uint8_t sc_pcie_capreg; /* PCI-E Capability Reg Set */
120 /* Devices that need special attention. */
122 int sc_devfn_via_ide;
125 /* Local forward declerations. */
126 static uint32_t fsl_pcib_cfgread(struct fsl_pcib_softc *, u_int, u_int, u_int,
128 static void fsl_pcib_cfgwrite(struct fsl_pcib_softc *, u_int, u_int, u_int,
129 u_int, uint32_t, int);
130 static int fsl_pcib_decode_win(phandle_t, struct fsl_pcib_softc *);
131 static void fsl_pcib_err_init(device_t);
132 static void fsl_pcib_inbound(struct fsl_pcib_softc *, int, int, u_long,
134 static int fsl_pcib_init(struct fsl_pcib_softc *, int, int);
135 static void fsl_pcib_outbound(struct fsl_pcib_softc *, int, int, u_long,
138 /* Forward declerations. */
139 static int fsl_pcib_attach(device_t);
140 static int fsl_pcib_detach(device_t);
141 static int fsl_pcib_probe(device_t);
143 static int fsl_pcib_maxslots(device_t);
144 static uint32_t fsl_pcib_read_config(device_t, u_int, u_int, u_int, u_int, int);
145 static void fsl_pcib_write_config(device_t, u_int, u_int, u_int, u_int,
148 /* Configuration r/w mutex. */
149 struct mtx pcicfg_mtx;
150 static int mtx_initialized = 0;
153 * Bus interface definitions.
155 static device_method_t fsl_pcib_methods[] = {
156 /* Device interface */
157 DEVMETHOD(device_probe, fsl_pcib_probe),
158 DEVMETHOD(device_attach, fsl_pcib_attach),
159 DEVMETHOD(device_detach, fsl_pcib_detach),
162 DEVMETHOD(pcib_maxslots, fsl_pcib_maxslots),
163 DEVMETHOD(pcib_read_config, fsl_pcib_read_config),
164 DEVMETHOD(pcib_write_config, fsl_pcib_write_config),
169 static devclass_t fsl_pcib_devclass;
171 DEFINE_CLASS_1(pcib, fsl_pcib_driver, fsl_pcib_methods,
172 sizeof(struct fsl_pcib_softc), ofw_pci_driver);
173 DRIVER_MODULE(pcib, ofwbus, fsl_pcib_driver, fsl_pcib_devclass, 0, 0);
176 fsl_pcib_probe(device_t dev)
179 if (ofw_bus_get_type(dev) == NULL ||
180 strcmp(ofw_bus_get_type(dev), "pci") != 0)
183 if (!(ofw_bus_is_compatible(dev, "fsl,mpc8540-pci") ||
184 ofw_bus_is_compatible(dev, "fsl,mpc8540-pcie") ||
185 ofw_bus_is_compatible(dev, "fsl,mpc8548-pcie")))
188 device_set_desc(dev, "Freescale Integrated PCI/PCI-E Controller");
189 return (BUS_PROBE_DEFAULT);
193 fsl_pcib_attach(device_t dev)
195 struct fsl_pcib_softc *sc;
199 uint8_t ltssm, capptr;
201 sc = device_get_softc(dev);
205 sc->sc_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->sc_rid,
207 if (sc->sc_res == NULL) {
208 device_printf(dev, "could not map I/O memory\n");
211 sc->sc_bst = rman_get_bustag(sc->sc_res);
212 sc->sc_bsh = rman_get_bushandle(sc->sc_res);
215 if (!mtx_initialized) {
216 mtx_init(&pcicfg_mtx, "pcicfg", NULL, MTX_SPIN);
220 cfgreg = fsl_pcib_cfgread(sc, 0, 0, 0, PCIR_VENDOR, 2);
221 if (cfgreg != 0x1057 && cfgreg != 0x1957)
224 capptr = fsl_pcib_cfgread(sc, 0, 0, 0, PCIR_CAP_PTR, 1);
225 while (capptr != 0) {
226 cfgreg = fsl_pcib_cfgread(sc, 0, 0, 0, capptr, 2);
227 switch (cfgreg & 0xff) {
232 sc->sc_pcie_capreg = capptr;
235 capptr = (cfgreg >> 8) & 0xff;
238 node = ofw_bus_get_node(dev);
241 * Initialize generic OF PCI interface (ranges, etc.)
244 error = ofw_pci_init(dev);
249 * Configure decode windows for PCI(E) access.
251 if (fsl_pcib_decode_win(node, sc) != 0)
254 cfgreg = fsl_pcib_cfgread(sc, 0, 0, 0, PCIR_COMMAND, 2);
255 cfgreg |= PCIM_CMD_SERRESPEN | PCIM_CMD_BUSMASTEREN | PCIM_CMD_MEMEN |
257 fsl_pcib_cfgwrite(sc, 0, 0, 0, PCIR_COMMAND, cfgreg, 2);
259 sc->sc_devfn_tundra = -1;
260 sc->sc_devfn_via_ide = -1;
264 * Scan bus using firmware configured, 0 based bus numbering.
267 maxslot = (sc->sc_pcie) ? 0 : PCI_SLOTMAX;
268 fsl_pcib_init(sc, sc->sc_busnr, maxslot);
271 ltssm = fsl_pcib_cfgread(sc, 0, 0, 0, PCIR_LTSSM, 1);
272 if (ltssm < LTSSM_STAT_L0) {
274 printf("PCI %d: no PCIE link, skipping\n",
275 device_get_unit(dev));
280 fsl_pcib_err_init(dev);
282 return (ofw_pci_attach(dev));
289 fsl_pcib_cfgread(struct fsl_pcib_softc *sc, u_int bus, u_int slot, u_int func,
290 u_int reg, int bytes)
294 if (bus == sc->sc_busnr - 1)
297 addr = CONFIG_ACCESS_ENABLE;
298 addr |= (bus & 0xff) << 16;
299 addr |= (slot & 0x1f) << 11;
300 addr |= (func & 0x7) << 8;
303 addr |= (reg & 0xf00) << 16;
305 mtx_lock_spin(&pcicfg_mtx);
306 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_CFG_ADDR, addr);
310 data = bus_space_read_1(sc->sc_bst, sc->sc_bsh,
311 REG_CFG_DATA + (reg & 3));
314 data = le16toh(bus_space_read_2(sc->sc_bst, sc->sc_bsh,
315 REG_CFG_DATA + (reg & 2)));
318 data = le32toh(bus_space_read_4(sc->sc_bst, sc->sc_bsh,
325 mtx_unlock_spin(&pcicfg_mtx);
330 fsl_pcib_cfgwrite(struct fsl_pcib_softc *sc, u_int bus, u_int slot, u_int func,
331 u_int reg, uint32_t data, int bytes)
335 if (bus == sc->sc_busnr - 1)
338 addr = CONFIG_ACCESS_ENABLE;
339 addr |= (bus & 0xff) << 16;
340 addr |= (slot & 0x1f) << 11;
341 addr |= (func & 0x7) << 8;
344 addr |= (reg & 0xf00) << 16;
346 mtx_lock_spin(&pcicfg_mtx);
347 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_CFG_ADDR, addr);
351 bus_space_write_1(sc->sc_bst, sc->sc_bsh,
352 REG_CFG_DATA + (reg & 3), data);
355 bus_space_write_2(sc->sc_bst, sc->sc_bsh,
356 REG_CFG_DATA + (reg & 2), htole16(data));
359 bus_space_write_4(sc->sc_bst, sc->sc_bsh,
360 REG_CFG_DATA, htole32(data));
363 mtx_unlock_spin(&pcicfg_mtx);
368 dump(struct fsl_pcib_softc *sc)
372 #define RD(o) bus_space_read_4(sc->sc_bst, sc->sc_bsh, o)
373 for (i = 0; i < 5; i++) {
374 printf("POTAR%u =0x%08x\n", i, RD(REG_POTAR(i)));
375 printf("POTEAR%u =0x%08x\n", i, RD(REG_POTEAR(i)));
376 printf("POWBAR%u =0x%08x\n", i, RD(REG_POWBAR(i)));
377 printf("POWAR%u =0x%08x\n", i, RD(REG_POWAR(i)));
380 for (i = 1; i < 4; i++) {
381 printf("PITAR%u =0x%08x\n", i, RD(REG_PITAR(i)));
382 printf("PIWBAR%u =0x%08x\n", i, RD(REG_PIWBAR(i)));
383 printf("PIWBEAR%u=0x%08x\n", i, RD(REG_PIWBEAR(i)));
384 printf("PIWAR%u =0x%08x\n", i, RD(REG_PIWAR(i)));
389 for (i = 0; i < 0x48; i += 4) {
390 printf("cfg%02x=0x%08x\n", i, fsl_pcib_cfgread(sc, 0, 0, 0,
397 fsl_pcib_maxslots(device_t dev)
399 struct fsl_pcib_softc *sc = device_get_softc(dev);
401 return ((sc->sc_pcie) ? 0 : PCI_SLOTMAX);
405 fsl_pcib_read_config(device_t dev, u_int bus, u_int slot, u_int func,
406 u_int reg, int bytes)
408 struct fsl_pcib_softc *sc = device_get_softc(dev);
411 if (bus == sc->sc_busnr && !sc->sc_pcie && slot < 10)
413 devfn = DEVFN(bus, slot, func);
414 if (devfn == sc->sc_devfn_tundra)
416 if (devfn == sc->sc_devfn_via_ide && reg == PCIR_INTPIN)
418 return (fsl_pcib_cfgread(sc, bus, slot, func, reg, bytes));
422 fsl_pcib_write_config(device_t dev, u_int bus, u_int slot, u_int func,
423 u_int reg, uint32_t val, int bytes)
425 struct fsl_pcib_softc *sc = device_get_softc(dev);
427 if (bus == sc->sc_busnr && !sc->sc_pcie && slot < 10)
429 fsl_pcib_cfgwrite(sc, bus, slot, func, reg, val, bytes);
433 fsl_pcib_init_via(struct fsl_pcib_softc *sc, uint16_t device, int bus,
437 if (device == 0x0686) {
438 fsl_pcib_write_config(sc->sc_dev, bus, slot, fn, 0x52, 0x34, 1);
439 fsl_pcib_write_config(sc->sc_dev, bus, slot, fn, 0x77, 0x00, 1);
440 fsl_pcib_write_config(sc->sc_dev, bus, slot, fn, 0x83, 0x98, 1);
441 fsl_pcib_write_config(sc->sc_dev, bus, slot, fn, 0x85, 0x03, 1);
442 } else if (device == 0x0571) {
443 sc->sc_devfn_via_ide = DEVFN(bus, slot, fn);
444 fsl_pcib_write_config(sc->sc_dev, bus, slot, fn, 0x40, 0x0b, 1);
449 fsl_pcib_init_bar(struct fsl_pcib_softc *sc, int bus, int slot, int func,
453 uint32_t addr, mask, size;
456 reg = PCIR_BAR(barno);
458 if (DEVFN(bus, slot, func) == sc->sc_devfn_via_ide) {
460 case 0: addr = 0x1f0; break;
461 case 1: addr = 0x3f4; break;
462 case 2: addr = 0x170; break;
463 case 3: addr = 0x374; break;
464 case 4: addr = 0xcc0; break;
467 fsl_pcib_write_config(sc->sc_dev, bus, slot, func, reg, addr, 4);
471 fsl_pcib_write_config(sc->sc_dev, bus, slot, func, reg, ~0, 4);
472 size = fsl_pcib_read_config(sc->sc_dev, bus, slot, func, reg, 4);
475 width = ((size & 7) == 4) ? 2 : 1;
477 if (size & 1) { /* I/O port */
478 allocp = &sc->sc_ioport_alloc;
480 if ((size & 0xffff0000) == 0)
482 } else { /* memory */
483 allocp = &sc->sc_iomem_alloc;
488 /* Sanity check (must be a power of 2). */
492 addr = (*allocp + mask) & ~mask;
493 *allocp = addr + size;
496 printf("PCI %u:%u:%u:%u: reg %x: size=%08x: addr=%08x\n",
497 device_get_unit(sc->sc_dev), bus, slot, func, reg,
500 fsl_pcib_write_config(sc->sc_dev, bus, slot, func, reg, addr, 4);
502 fsl_pcib_write_config(sc->sc_dev, bus, slot, func, reg + 4,
508 fsl_pcib_init(struct fsl_pcib_softc *sc, int bus, int maxslot)
511 int old_pribus, old_secbus, old_subbus;
512 int new_pribus, new_secbus, new_subbus;
513 int slot, func, maxfunc;
515 uint16_t vendor, device;
516 uint8_t command, hdrtype, class, subclass;
519 for (slot = 0; slot <= maxslot; slot++) {
521 for (func = 0; func <= maxfunc; func++) {
522 hdrtype = fsl_pcib_read_config(sc->sc_dev, bus, slot,
523 func, PCIR_HDRTYPE, 1);
525 if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE)
528 if (func == 0 && (hdrtype & PCIM_MFDEV))
529 maxfunc = PCI_FUNCMAX;
531 vendor = fsl_pcib_read_config(sc->sc_dev, bus, slot,
532 func, PCIR_VENDOR, 2);
533 device = fsl_pcib_read_config(sc->sc_dev, bus, slot,
534 func, PCIR_DEVICE, 2);
536 if (vendor == 0x1957 && device == 0x3fff) {
537 sc->sc_devfn_tundra = DEVFN(bus, slot, func);
541 command = fsl_pcib_read_config(sc->sc_dev, bus, slot,
542 func, PCIR_COMMAND, 1);
543 command &= ~(PCIM_CMD_MEMEN | PCIM_CMD_PORTEN);
544 fsl_pcib_write_config(sc->sc_dev, bus, slot, func,
545 PCIR_COMMAND, command, 1);
547 if (vendor == 0x1106)
548 fsl_pcib_init_via(sc, device, bus, slot, func);
550 /* Program the base address registers. */
551 maxbar = (hdrtype & PCIM_HDRTYPE) ? 1 : 6;
554 bar += fsl_pcib_init_bar(sc, bus, slot, func,
557 /* Put a placeholder interrupt value */
558 fsl_pcib_write_config(sc->sc_dev, bus, slot, func,
559 PCIR_INTLINE, PCI_INVALID_IRQ, 1);
561 command |= PCIM_CMD_MEMEN | PCIM_CMD_PORTEN;
562 fsl_pcib_write_config(sc->sc_dev, bus, slot, func,
563 PCIR_COMMAND, command, 1);
566 * Handle PCI-PCI bridges
568 class = fsl_pcib_read_config(sc->sc_dev, bus, slot,
569 func, PCIR_CLASS, 1);
570 subclass = fsl_pcib_read_config(sc->sc_dev, bus, slot,
571 func, PCIR_SUBCLASS, 1);
574 * The PCI Root Complex comes up as a Processor/PowerPC,
577 /* Allow only proper PCI-PCI briges */
578 if (class != PCIC_BRIDGE && class != PCIC_PROCESSOR)
580 if (subclass != PCIS_BRIDGE_PCI &&
581 subclass != PCIS_PROCESSOR_POWERPC)
584 if (subclass == PCIS_PROCESSOR_POWERPC &&
585 hdrtype != PCIM_HDRTYPE_BRIDGE)
590 /* Program I/O decoder. */
591 fsl_pcib_write_config(sc->sc_dev, bus, slot, func,
592 PCIR_IOBASEL_1, sc->sc_ioport_start >> 8, 1);
593 fsl_pcib_write_config(sc->sc_dev, bus, slot, func,
594 PCIR_IOLIMITL_1, sc->sc_ioport_end >> 8, 1);
595 fsl_pcib_write_config(sc->sc_dev, bus, slot, func,
596 PCIR_IOBASEH_1, sc->sc_ioport_start >> 16, 2);
597 fsl_pcib_write_config(sc->sc_dev, bus, slot, func,
598 PCIR_IOLIMITH_1, sc->sc_ioport_end >> 16, 2);
600 /* Program (non-prefetchable) memory decoder. */
601 fsl_pcib_write_config(sc->sc_dev, bus, slot, func,
602 PCIR_MEMBASE_1, sc->sc_iomem_start >> 16, 2);
603 fsl_pcib_write_config(sc->sc_dev, bus, slot, func,
604 PCIR_MEMLIMIT_1, sc->sc_iomem_end >> 16, 2);
606 /* Program prefetchable memory decoder. */
607 fsl_pcib_write_config(sc->sc_dev, bus, slot, func,
608 PCIR_PMBASEL_1, 0x0010, 2);
609 fsl_pcib_write_config(sc->sc_dev, bus, slot, func,
610 PCIR_PMLIMITL_1, 0x000f, 2);
611 fsl_pcib_write_config(sc->sc_dev, bus, slot, func,
612 PCIR_PMBASEH_1, 0x00000000, 4);
613 fsl_pcib_write_config(sc->sc_dev, bus, slot, func,
614 PCIR_PMLIMITH_1, 0x00000000, 4);
616 /* Read currect bus register configuration */
617 old_pribus = fsl_pcib_read_config(sc->sc_dev, bus,
618 slot, func, PCIR_PRIBUS_1, 1);
619 old_secbus = fsl_pcib_read_config(sc->sc_dev, bus,
620 slot, func, PCIR_SECBUS_1, 1);
621 old_subbus = fsl_pcib_read_config(sc->sc_dev, bus,
622 slot, func, PCIR_SUBBUS_1, 1);
625 printf("PCI: reading firmware bus numbers for "
626 "secbus = %d (bus/sec/sub) = (%d/%d/%d)\n",
627 secbus, old_pribus, old_secbus, old_subbus);
632 secbus = fsl_pcib_init(sc, secbus,
633 (subclass == PCIS_BRIDGE_PCI) ? PCI_SLOTMAX : 0);
638 printf("PCI: translate firmware bus numbers "
639 "for secbus %d (%d/%d/%d) -> (%d/%d/%d)\n",
640 secbus, old_pribus, old_secbus, old_subbus,
641 new_pribus, new_secbus, new_subbus);
643 fsl_pcib_write_config(sc->sc_dev, bus, slot, func,
644 PCIR_PRIBUS_1, new_pribus, 1);
645 fsl_pcib_write_config(sc->sc_dev, bus, slot, func,
646 PCIR_SECBUS_1, new_secbus, 1);
647 fsl_pcib_write_config(sc->sc_dev, bus, slot, func,
648 PCIR_SUBBUS_1, new_subbus, 1);
656 fsl_pcib_inbound(struct fsl_pcib_softc *sc, int wnd, int tgt, u_long start,
657 u_long size, u_long pci_start)
659 uint32_t attr, bar, tar;
661 KASSERT(wnd > 0, ("%s: inbound window 0 is invalid", __func__));
664 /* XXX OCP85XX_TGTIF_RAM2, OCP85XX_TGTIF_RAM_INTL should be handled */
665 case OCP85XX_TGTIF_RAM1:
666 attr = 0xa0f55000 | (ffsl(size) - 2);
673 bar = pci_start >> 12;
675 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_PITAR(wnd), tar);
676 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_PIWBEAR(wnd), 0);
677 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_PIWBAR(wnd), bar);
678 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_PIWAR(wnd), attr);
682 fsl_pcib_outbound(struct fsl_pcib_softc *sc, int wnd, int res, u_long start,
683 u_long size, u_long pci_start)
685 uint32_t attr, bar, tar;
689 attr = 0x80044000 | (ffsl(size) - 2);
692 attr = 0x80088000 | (ffsl(size) - 2);
699 tar = pci_start >> 12;
701 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_POTAR(wnd), tar);
702 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_POTEAR(wnd), 0);
703 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_POWBAR(wnd), bar);
704 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_POWAR(wnd), attr);
709 fsl_pcib_err_init(device_t dev)
711 struct fsl_pcib_softc *sc;
712 uint16_t sec_stat, dsr;
713 uint32_t dcr, err_en;
715 sc = device_get_softc(dev);
717 sec_stat = fsl_pcib_cfgread(sc, 0, 0, 0, PCIR_SECSTAT_1, 2);
719 fsl_pcib_cfgwrite(sc, 0, 0, 0, PCIR_SECSTAT_1, 0xffff, 2);
721 /* Clear error bits */
722 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_PEX_MES_IER,
724 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_PEX_MES_DR,
726 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_PEX_ERR_DR,
729 dsr = fsl_pcib_cfgread(sc, 0, 0, 0,
730 sc->sc_pcie_capreg + PCIER_DEVICE_STA, 2);
732 fsl_pcib_cfgwrite(sc, 0, 0, 0,
733 sc->sc_pcie_capreg + PCIER_DEVICE_STA,
736 /* Enable all errors reporting */
738 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_PEX_ERR_EN,
741 /* Enable error reporting: URR, FER, NFER */
742 dcr = fsl_pcib_cfgread(sc, 0, 0, 0,
743 sc->sc_pcie_capreg + PCIER_DEVICE_CTL, 4);
744 dcr |= PCIEM_CTL_URR_ENABLE | PCIEM_CTL_FER_ENABLE |
745 PCIEM_CTL_NFER_ENABLE;
746 fsl_pcib_cfgwrite(sc, 0, 0, 0,
747 sc->sc_pcie_capreg + PCIER_DEVICE_CTL, dcr, 4);
752 fsl_pcib_detach(device_t dev)
755 if (mtx_initialized) {
756 mtx_destroy(&pcicfg_mtx);
759 return (bus_generic_detach(dev));
763 fsl_pcib_decode_win(phandle_t node, struct fsl_pcib_softc *sc)
770 fsl_pcib_outbound(sc, 0, -1, 0, 0, 0);
773 * Configure LAW decode windows.
775 error = law_pci_target(sc->sc_res, &sc->sc_iomem_target,
776 &sc->sc_ioport_target);
778 device_printf(dev, "could not retrieve PCI LAW target info\n");
782 for (i = 0; i < sc->pci_sc.sc_nrange; i++) {
783 switch (sc->pci_sc.sc_range[i].pci_hi &
784 OFW_PCI_PHYS_HI_SPACEMASK) {
785 case OFW_PCI_PHYS_HI_SPACE_CONFIG:
787 case OFW_PCI_PHYS_HI_SPACE_IO:
788 trgt = sc->sc_ioport_target;
789 fsl_pcib_outbound(sc, 2, SYS_RES_IOPORT,
790 sc->pci_sc.sc_range[i].host,
791 sc->pci_sc.sc_range[i].size,
792 sc->pci_sc.sc_range[i].pci);
793 sc->sc_ioport_start = sc->pci_sc.sc_range[i].host;
794 sc->sc_ioport_end = sc->pci_sc.sc_range[i].host +
795 sc->pci_sc.sc_range[i].size;
796 sc->sc_ioport_alloc = 0x1000 + sc->pci_sc.sc_range[i].pci;
798 case OFW_PCI_PHYS_HI_SPACE_MEM32:
799 case OFW_PCI_PHYS_HI_SPACE_MEM64:
800 trgt = sc->sc_iomem_target;
801 fsl_pcib_outbound(sc, 1, SYS_RES_MEMORY,
802 sc->pci_sc.sc_range[i].host,
803 sc->pci_sc.sc_range[i].size,
804 sc->pci_sc.sc_range[i].pci);
805 sc->sc_iomem_start = sc->pci_sc.sc_range[i].host;
806 sc->sc_iomem_end = sc->pci_sc.sc_range[i].host +
807 sc->pci_sc.sc_range[i].size;
808 sc->sc_iomem_alloc = sc->pci_sc.sc_range[i].pci;
811 panic("Unknown range type %#x\n",
812 sc->pci_sc.sc_range[i].pci_hi &
813 OFW_PCI_PHYS_HI_SPACEMASK);
815 error = law_enable(trgt, sc->pci_sc.sc_range[i].host,
816 sc->pci_sc.sc_range[i].size);
818 device_printf(dev, "could not program LAW for range "
825 * Set outbout and inbound windows.
827 fsl_pcib_outbound(sc, 3, -1, 0, 0, 0);
828 fsl_pcib_outbound(sc, 4, -1, 0, 0, 0);
830 fsl_pcib_inbound(sc, 1, -1, 0, 0, 0);
831 fsl_pcib_inbound(sc, 2, -1, 0, 0, 0);
832 fsl_pcib_inbound(sc, 3, OCP85XX_TGTIF_RAM1, 0,
833 2U * 1024U * 1024U * 1024U, 0);