2 * Copyright (c) 2008-2012 Semihalf.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
30 #include <sys/param.h>
31 #include <sys/systm.h>
32 #include <sys/kernel.h>
38 #include <machine/bus.h>
39 #include <machine/cpu.h>
40 #include <machine/hid.h>
41 #include <machine/platform.h>
42 #include <machine/platformvar.h>
43 #include <machine/smp.h>
44 #include <machine/spr.h>
45 #include <machine/vmparam.h>
47 #include <dev/fdt/fdt_common.h>
48 #include <dev/ofw/ofw_bus.h>
49 #include <dev/ofw/ofw_bus_subr.h>
50 #include <dev/ofw/openfirm.h>
55 #include <powerpc/mpc85xx/mpc85xx.h>
57 #include "platform_if.h"
61 extern vm_paddr_t kernload; /* Kernel physical load address */
62 extern uint8_t __boot_page[]; /* Boot page body */
63 extern uint32_t bp_ntlb1s;
64 extern uint32_t bp_tlb1[];
65 extern uint32_t bp_tlb1_end[];
68 extern uint32_t *bootinfo;
69 vm_offset_t ccsrbar_va;
71 static int cpu, maxcpu;
73 static int mpc85xx_probe(platform_t);
74 static void mpc85xx_mem_regions(platform_t, struct mem_region *phys,
75 int *physsz, struct mem_region *avail, int *availsz);
76 static u_long mpc85xx_timebase_freq(platform_t, struct cpuref *cpuref);
77 static int mpc85xx_smp_first_cpu(platform_t, struct cpuref *cpuref);
78 static int mpc85xx_smp_next_cpu(platform_t, struct cpuref *cpuref);
79 static int mpc85xx_smp_get_bsp(platform_t, struct cpuref *cpuref);
80 static int mpc85xx_smp_start_cpu(platform_t, struct pcpu *cpu);
82 static void mpc85xx_reset(platform_t);
84 static platform_method_t mpc85xx_methods[] = {
85 PLATFORMMETHOD(platform_probe, mpc85xx_probe),
86 PLATFORMMETHOD(platform_attach, mpc85xx_attach),
87 PLATFORMMETHOD(platform_mem_regions, mpc85xx_mem_regions),
88 PLATFORMMETHOD(platform_timebase_freq, mpc85xx_timebase_freq),
90 PLATFORMMETHOD(platform_smp_first_cpu, mpc85xx_smp_first_cpu),
91 PLATFORMMETHOD(platform_smp_next_cpu, mpc85xx_smp_next_cpu),
92 PLATFORMMETHOD(platform_smp_get_bsp, mpc85xx_smp_get_bsp),
93 PLATFORMMETHOD(platform_smp_start_cpu, mpc85xx_smp_start_cpu),
95 PLATFORMMETHOD(platform_reset, mpc85xx_reset),
100 DEFINE_CLASS_0(mpc85xx, mpc85xx_platform, mpc85xx_methods, 0);
102 PLATFORM_DEF(mpc85xx_platform);
105 mpc85xx_probe(platform_t plat)
107 u_int pvr = mfpvr() >> 16;
109 if ((pvr & 0xfff0) == FSL_E500v1)
110 return (BUS_PROBE_DEFAULT);
116 mpc85xx_attach(platform_t plat)
118 phandle_t cpus, child, ccsr;
119 const char *soc_name_guesses[] = {"/soc", "soc", NULL};
121 pcell_t ranges[6], acells, pacells, scells;
123 uint64_t ccsrbar, ccsrsize;
126 if ((cpus = OF_finddevice("/cpus")) != -1) {
127 for (maxcpu = 0, child = OF_child(cpus); child != 0;
128 child = OF_peer(child), maxcpu++)
134 * Locate CCSR region. Irritatingly, there is no way to find it
135 * unless you already know where it is. Try to infer its location
136 * from the device tree.
140 for (name = soc_name_guesses; *name != NULL && ccsr == -1; name++)
141 ccsr = OF_finddevice(*name);
145 /* That didn't work. Search for devices of type "soc" */
146 child = OF_child(OF_peer(0));
147 for (OF_child(child); child != 0; child = OF_peer(child)) {
148 if (OF_getprop(child, "device_type", type, sizeof(type))
152 if (strcmp(type, "soc") == 0) {
160 panic("Could not locate CCSR window!");
162 OF_getprop(ccsr, "#size-cells", &scells, sizeof(scells));
163 OF_getprop(ccsr, "#address-cells", &acells, sizeof(acells));
164 OF_searchprop(OF_parent(ccsr), "#address-cells", &pacells,
166 OF_getprop(ccsr, "ranges", ranges, sizeof(ranges));
167 ccsrbar = ccsrsize = 0;
168 for (i = acells; i < acells + pacells; i++) {
170 ccsrbar |= ranges[i];
172 for (i = acells + pacells; i < acells + pacells + scells; i++) {
174 ccsrsize |= ranges[i];
176 ccsrbar_va = pmap_early_io_map(ccsrbar, ccsrsize);
179 * Clear local access windows. Skip DRAM entries, so we don't shoot
180 * ourselves in the foot.
182 law_max = law_getmax();
183 for (i = 0; i < law_max; i++) {
184 sr = ccsr_read4(OCP85XX_LAWSR(i));
185 if ((sr & 0x80000000) == 0)
187 tgt = (sr & 0x01f00000) >> 20;
188 if (tgt == OCP85XX_TGTIF_RAM1 || tgt == OCP85XX_TGTIF_RAM2 ||
189 tgt == OCP85XX_TGTIF_RAM_INTL)
192 ccsr_write4(OCP85XX_LAWSR(i), sr & 0x7fffffff);
199 mpc85xx_mem_regions(platform_t plat, struct mem_region *phys, int *physsz,
200 struct mem_region *avail, int *availsz)
203 ofw_mem_regions(phys, physsz, avail, availsz);
207 mpc85xx_timebase_freq(platform_t plat, struct cpuref *cpuref)
210 phandle_t cpus, child;
213 if (bootinfo != NULL) {
214 if (bootinfo[0] == 1) {
215 /* Backward compatibility. See 8-STABLE. */
216 ticks = bootinfo[3] >> 3;
218 /* Compatibility with Juniper's loader. */
219 ticks = bootinfo[5] >> 3;
224 if ((cpus = OF_finddevice("/cpus")) == -1)
227 if ((child = OF_child(cpus)) == 0)
230 switch (OF_getproplen(child, "timebase-frequency")) {
234 OF_getprop(child, "timebase-frequency", &tbase, sizeof(tbase));
241 OF_getprop(child, "timebase-frequency", &tbase, sizeof(tbase));
250 if (OF_getprop(child, "bus-frequency", (void *)&freq,
255 * Time Base and Decrementer are updated every 8 CCB bus clocks.
256 * HID0[SEL_TBCLK] = 0
263 panic("Unable to determine timebase frequency!");
269 mpc85xx_smp_first_cpu(platform_t plat, struct cpuref *cpuref)
273 cpuref->cr_cpuid = cpu;
274 cpuref->cr_hwref = cpuref->cr_cpuid;
276 printf("powerpc_smp_first_cpu: cpuid %d\n", cpuref->cr_cpuid);
283 mpc85xx_smp_next_cpu(platform_t plat, struct cpuref *cpuref)
289 cpuref->cr_cpuid = cpu++;
290 cpuref->cr_hwref = cpuref->cr_cpuid;
292 printf("powerpc_smp_next_cpu: cpuid %d\n", cpuref->cr_cpuid);
298 mpc85xx_smp_get_bsp(platform_t plat, struct cpuref *cpuref)
301 cpuref->cr_cpuid = mfspr(SPR_PIR);
302 cpuref->cr_hwref = cpuref->cr_cpuid;
308 mpc85xx_smp_start_cpu(platform_t plat, struct pcpu *pc)
312 uint32_t bptr, eebpcr;
315 eebpcr = ccsr_read4(OCP85XX_EEBPCR);
316 if ((eebpcr & (1 << (pc->pc_cpuid + 24))) != 0) {
317 printf("SMP: CPU %d already out of hold-off state!\n",
326 while (i < bp_ntlb1s && tlb1 < bp_tlb1_end) {
327 mtspr(SPR_MAS0, MAS0_TLBSEL(1) | MAS0_ESEL(i));
328 __asm __volatile("isync; tlbre");
329 tlb1[0] = mfspr(SPR_MAS1);
330 tlb1[1] = mfspr(SPR_MAS2);
331 tlb1[2] = mfspr(SPR_MAS3);
339 * Set BPTR to the physical address of the boot page
341 bptr = ((uint32_t)__boot_page - KERNBASE) + kernload;
342 KASSERT((bptr & 0xfff) == 0,
343 ("%s: boot page is not aligned (%#x)", __func__, bptr));
344 bptr = (bptr >> 12) | 0x80000000u;
345 ccsr_write4(OCP85XX_BPTR, bptr);
346 __asm __volatile("isync; msync");
348 /* Flush caches to have our changes hit DRAM. */
349 cpu_flush_dcache(__boot_page, 4096);
352 * Release AP from hold-off state
354 eebpcr |= (1 << (pc->pc_cpuid + 24));
355 ccsr_write4(OCP85XX_EEBPCR, eebpcr);
356 __asm __volatile("isync; msync");
359 while (!pc->pc_awake && timeout--)
360 DELAY(1000); /* wait 1ms */
363 * Disable boot page translation so that the 4K page at the default
364 * address (= 0xfffff000) isn't permanently remapped and thus not
367 ccsr_write4(OCP85XX_BPTR, 0);
368 __asm __volatile("isync; msync");
371 printf("SMP: CPU %d didn't wake up.\n", pc->pc_cpuid);
372 return ((pc->pc_awake) ? 0 : EBUSY);
380 mpc85xx_reset(platform_t plat)
384 * Try the dedicated reset register first.
385 * If the SoC doesn't have one, we'll fall
386 * back to using the debug control register.
388 ccsr_write4(OCP85XX_RSTCR, 2);
390 /* Clear DBCR0, disables debug interrupts and events. */
392 __asm __volatile("isync");
394 /* Enable Debug Interrupts in MSR. */
395 mtmsr(mfmsr() | PSL_DE);
397 /* Enable debug interrupts and issue reset. */
398 mtspr(SPR_DBCR0, mfspr(SPR_DBCR0) | DBCR0_IDM | DBCR0_RST_SYSTEM);
400 printf("Reset failed...\n");