2 * Copyright (c) 2008-2012 Semihalf.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 #include "opt_platform.h"
28 #include <sys/cdefs.h>
29 __FBSDID("$FreeBSD$");
31 #include <sys/param.h>
32 #include <sys/systm.h>
33 #include <sys/kernel.h>
39 #include <machine/bus.h>
40 #include <machine/cpu.h>
41 #include <machine/hid.h>
42 #include <machine/_inttypes.h>
43 #include <machine/machdep.h>
44 #include <machine/md_var.h>
45 #include <machine/platform.h>
46 #include <machine/platformvar.h>
47 #include <machine/smp.h>
48 #include <machine/spr.h>
49 #include <machine/vmparam.h>
51 #include <dev/fdt/fdt_common.h>
52 #include <dev/ofw/ofw_bus.h>
53 #include <dev/ofw/ofw_bus_subr.h>
54 #include <dev/ofw/openfirm.h>
58 #include <vm/vm_extern.h>
60 #include <powerpc/mpc85xx/mpc85xx.h>
62 #include "platform_if.h"
66 extern vm_paddr_t kernload; /* Kernel physical load address */
67 extern uint8_t __boot_page[]; /* Boot page body */
68 extern uint32_t bp_kernload;
80 extern uint32_t *bootinfo;
81 vm_paddr_t ccsrbar_pa;
82 vm_offset_t ccsrbar_va;
83 vm_size_t ccsrbar_size;
85 static int cpu, maxcpu;
87 static int mpc85xx_probe(platform_t);
88 static void mpc85xx_mem_regions(platform_t, struct mem_region *phys,
89 int *physsz, struct mem_region *avail, int *availsz);
90 static u_long mpc85xx_timebase_freq(platform_t, struct cpuref *cpuref);
91 static int mpc85xx_smp_first_cpu(platform_t, struct cpuref *cpuref);
92 static int mpc85xx_smp_next_cpu(platform_t, struct cpuref *cpuref);
93 static int mpc85xx_smp_get_bsp(platform_t, struct cpuref *cpuref);
94 static int mpc85xx_smp_start_cpu(platform_t, struct pcpu *cpu);
95 static void mpc85xx_idle(platform_t, int cpu);
96 static int mpc85xx_idle_wakeup(platform_t plat, int cpu);
98 static void mpc85xx_reset(platform_t);
100 static platform_method_t mpc85xx_methods[] = {
101 PLATFORMMETHOD(platform_probe, mpc85xx_probe),
102 PLATFORMMETHOD(platform_attach, mpc85xx_attach),
103 PLATFORMMETHOD(platform_mem_regions, mpc85xx_mem_regions),
104 PLATFORMMETHOD(platform_timebase_freq, mpc85xx_timebase_freq),
106 PLATFORMMETHOD(platform_smp_first_cpu, mpc85xx_smp_first_cpu),
107 PLATFORMMETHOD(platform_smp_next_cpu, mpc85xx_smp_next_cpu),
108 PLATFORMMETHOD(platform_smp_get_bsp, mpc85xx_smp_get_bsp),
109 PLATFORMMETHOD(platform_smp_start_cpu, mpc85xx_smp_start_cpu),
111 PLATFORMMETHOD(platform_reset, mpc85xx_reset),
112 PLATFORMMETHOD(platform_idle, mpc85xx_idle),
113 PLATFORMMETHOD(platform_idle_wakeup, mpc85xx_idle_wakeup),
118 DEFINE_CLASS_0(mpc85xx, mpc85xx_platform, mpc85xx_methods, 0);
120 PLATFORM_DEF(mpc85xx_platform);
123 mpc85xx_probe(platform_t plat)
125 u_int pvr = (mfpvr() >> 16) & 0xFFFF;
133 return (BUS_PROBE_DEFAULT);
139 mpc85xx_attach(platform_t plat)
141 phandle_t cpus, child, ccsr;
142 const char *soc_name_guesses[] = {"/soc", "soc", NULL};
144 pcell_t ranges[6], acells, pacells, scells;
145 uint64_t ccsrbar, ccsrsize;
148 if ((cpus = OF_finddevice("/cpus")) != -1) {
149 for (maxcpu = 0, child = OF_child(cpus); child != 0;
150 child = OF_peer(child), maxcpu++)
156 * Locate CCSR region. Irritatingly, there is no way to find it
157 * unless you already know where it is. Try to infer its location
158 * from the device tree.
162 for (name = soc_name_guesses; *name != NULL && ccsr == -1; name++)
163 ccsr = OF_finddevice(*name);
167 /* That didn't work. Search for devices of type "soc" */
168 child = OF_child(OF_peer(0));
169 for (OF_child(child); child != 0; child = OF_peer(child)) {
170 if (OF_getprop(child, "device_type", type, sizeof(type))
174 if (strcmp(type, "soc") == 0) {
182 panic("Could not locate CCSR window!");
184 OF_getprop(ccsr, "#size-cells", &scells, sizeof(scells));
185 OF_getprop(ccsr, "#address-cells", &acells, sizeof(acells));
186 OF_searchprop(OF_parent(ccsr), "#address-cells", &pacells,
188 OF_getprop(ccsr, "ranges", ranges, sizeof(ranges));
189 ccsrbar = ccsrsize = 0;
190 for (i = acells; i < acells + pacells; i++) {
192 ccsrbar |= ranges[i];
194 for (i = acells + pacells; i < acells + pacells + scells; i++) {
196 ccsrsize |= ranges[i];
198 ccsrbar_va = pmap_early_io_map(ccsrbar, ccsrsize);
199 ccsrbar_pa = ccsrbar;
200 ccsrbar_size = ccsrsize;
203 mpc85xx_fix_errata(ccsrbar_va);
205 mpc85xx_enable_l3_cache();
211 mpc85xx_mem_regions(platform_t plat, struct mem_region *phys, int *physsz,
212 struct mem_region *avail, int *availsz)
215 ofw_mem_regions(phys, physsz, avail, availsz);
219 mpc85xx_timebase_freq(platform_t plat, struct cpuref *cpuref)
222 phandle_t cpus, child;
225 if (bootinfo != NULL) {
226 if (bootinfo[0] == 1) {
227 /* Backward compatibility. See 8-STABLE. */
228 ticks = bootinfo[3] >> 3;
230 /* Compatibility with Juniper's loader. */
231 ticks = bootinfo[5] >> 3;
236 if ((cpus = OF_finddevice("/cpus")) == -1)
239 if ((child = OF_child(cpus)) == 0)
242 switch (OF_getproplen(child, "timebase-frequency")) {
246 OF_getprop(child, "timebase-frequency", &tbase, sizeof(tbase));
253 OF_getprop(child, "timebase-frequency", &tbase, sizeof(tbase));
262 if (OF_getprop(child, "bus-frequency", (void *)&freq,
270 * Time Base and Decrementer are updated every 8 CCB bus clocks.
271 * HID0[SEL_TBCLK] = 0
273 if (mpc85xx_is_qoriq())
280 panic("Unable to determine timebase frequency!");
286 mpc85xx_smp_first_cpu(platform_t plat, struct cpuref *cpuref)
290 cpuref->cr_cpuid = cpu;
291 cpuref->cr_hwref = cpuref->cr_cpuid;
293 printf("powerpc_smp_first_cpu: cpuid %d\n", cpuref->cr_cpuid);
300 mpc85xx_smp_next_cpu(platform_t plat, struct cpuref *cpuref)
306 cpuref->cr_cpuid = cpu++;
307 cpuref->cr_hwref = cpuref->cr_cpuid;
309 printf("powerpc_smp_next_cpu: cpuid %d\n", cpuref->cr_cpuid);
315 mpc85xx_smp_get_bsp(platform_t plat, struct cpuref *cpuref)
318 cpuref->cr_cpuid = mfspr(SPR_PIR);
319 cpuref->cr_hwref = cpuref->cr_cpuid;
326 mpc85xx_smp_start_cpu_epapr(platform_t plat, struct pcpu *pc)
328 vm_paddr_t rel_pa, bptr;
329 volatile struct cpu_release *rel;
330 vm_offset_t rel_va, rel_page;
334 /* If we're calling this, the node already exists. */
335 node = OF_finddevice("/cpus");
336 for (i = 0, node = OF_child(node); i < pc->pc_cpuid;
337 i++, node = OF_peer(node))
339 if (OF_getencprop(node, "cpu-release-addr", (pcell_t *)&rel_pa,
340 sizeof(rel_pa)) == -1) {
344 rel_page = kva_alloc(PAGE_SIZE);
349 rel_va = rel_page + (rel_pa & PAGE_MASK);
350 pmap_kenter(rel_page, rel_pa & ~PAGE_MASK);
351 rel = (struct cpu_release *)rel_va;
352 bptr = ((vm_paddr_t)(uintptr_t)__boot_page - KERNBASE) + kernload;
353 cpu_flush_dcache(__DEVOLATILE(struct cpu_release *,rel), sizeof(*rel));
354 rel->pir = pc->pc_cpuid; __asm __volatile("sync");
355 rel->entry_h = (bptr >> 32);
356 rel->entry_l = bptr; __asm __volatile("sync");
357 cpu_flush_dcache(__DEVOLATILE(struct cpu_release *,rel), sizeof(*rel));
359 printf("Waking up CPU %d via CPU release page %p\n",
362 pmap_kremove(rel_page);
363 kva_free(rel_page, PAGE_SIZE);
370 mpc85xx_smp_start_cpu(platform_t plat, struct pcpu *pc)
381 if (mpc85xx_is_qoriq()) {
382 reg = ccsr_read4(OCP85XX_COREDISR);
383 cpuid = pc->pc_cpuid;
385 if ((reg & (1 << cpuid)) != 0) {
386 printf("%s: CPU %d is disabled!\n", __func__, pc->pc_cpuid);
392 brr = OCP85XX_EEBPCR;
393 cpuid = pc->pc_cpuid + 24;
395 bp_kernload = kernload;
397 * bp_kernload is in the boot page. Sync the cache because ePAPR
398 * booting has the other core(s) already running.
400 cpu_flush_dcache(&bp_kernload, sizeof(bp_kernload));
403 __asm __volatile("msync; isync");
405 /* First try the ePAPR way. */
406 if (mpc85xx_smp_start_cpu_epapr(plat, pc) == 0) {
411 reg = ccsr_read4(brr);
412 if ((reg & (1 << cpuid)) != 0) {
413 printf("SMP: CPU %d already out of hold-off state!\n",
418 /* Flush caches to have our changes hit DRAM. */
419 cpu_flush_dcache(__boot_page, 4096);
421 bptr = ((vm_paddr_t)(uintptr_t)__boot_page - KERNBASE) + kernload;
422 KASSERT((bptr & 0xfff) == 0,
423 ("%s: boot page is not aligned (%#jx)", __func__, (uintmax_t)bptr));
424 if (mpc85xx_is_qoriq()) {
426 * Read DDR controller configuration to select proper BPTR target ID.
428 * On P5020 bit 29 of DDR1_CS0_CONFIG enables DDR controllers
429 * interleaving. If this bit is set, we have to use
430 * OCP85XX_TGTIF_RAM_INTL as BPTR target ID. On other QorIQ DPAA SoCs,
431 * this bit is reserved and always 0.
434 reg = ccsr_read4(OCP85XX_DDR1_CS0_CONFIG);
436 tgt = OCP85XX_TGTIF_RAM_INTL;
438 tgt = OCP85XX_TGTIF_RAM1;
441 * Set BSTR to the physical address of the boot page
443 ccsr_write4(OCP85XX_BSTRH, bptr >> 32);
444 ccsr_write4(OCP85XX_BSTRL, bptr);
445 ccsr_write4(OCP85XX_BSTAR, OCP85XX_ENA_MASK |
446 (tgt << OCP85XX_TRGT_SHIFT_QORIQ) | (ffsl(PAGE_SIZE) - 2));
448 /* Read back OCP85XX_BSTAR to synchronize write */
449 ccsr_read4(OCP85XX_BSTAR);
452 * Enable and configure time base on new CPU.
455 /* Set TB clock source to platform clock / 32 */
456 reg = ccsr_read4(CCSR_CTBCKSELR);
457 ccsr_write4(CCSR_CTBCKSELR, reg & ~(1 << pc->pc_cpuid));
460 reg = ccsr_read4(CCSR_CTBENR);
461 ccsr_write4(CCSR_CTBENR, reg | (1 << pc->pc_cpuid));
464 * Set BPTR to the physical address of the boot page
466 bptr = (bptr >> 12) | 0x80000000u;
467 ccsr_write4(OCP85XX_BPTR, bptr);
468 __asm __volatile("isync; msync");
472 * Release AP from hold-off state
474 reg = ccsr_read4(brr);
475 ccsr_write4(brr, reg | (1 << cpuid));
476 __asm __volatile("isync; msync");
480 while (!pc->pc_awake && timeout--)
481 DELAY(1000); /* wait 1ms */
484 * Disable boot page translation so that the 4K page at the default
485 * address (= 0xfffff000) isn't permanently remapped and thus not
489 if (mpc85xx_is_qoriq())
490 ccsr_write4(OCP85XX_BSTAR, 0);
492 ccsr_write4(OCP85XX_BPTR, 0);
493 __asm __volatile("isync; msync");
497 panic("SMP: CPU %d didn't wake up.\n", pc->pc_cpuid);
498 return ((pc->pc_awake) ? 0 : EBUSY);
506 mpc85xx_reset(platform_t plat)
510 * Try the dedicated reset register first.
511 * If the SoC doesn't have one, we'll fall
512 * back to using the debug control register.
514 ccsr_write4(OCP85XX_RSTCR, 2);
516 /* Clear DBCR0, disables debug interrupts and events. */
518 __asm __volatile("isync");
520 /* Enable Debug Interrupts in MSR. */
521 mtmsr(mfmsr() | PSL_DE);
523 /* Enable debug interrupts and issue reset. */
524 mtspr(SPR_DBCR0, mfspr(SPR_DBCR0) | DBCR0_IDM | DBCR0_RST_SYSTEM);
526 printf("Reset failed...\n");
532 mpc85xx_idle(platform_t plat, int cpu)
536 if (mpc85xx_is_qoriq()) {
538 * Base binutils doesn't know what the 'wait' instruction is, so
539 * use the opcode encoding here.
541 __asm __volatile("wrteei 1; .long 0x7c00007c");
544 /* Freescale E500 core RM section 6.4.1. */
545 __asm __volatile("msync; mtmsr %0; isync" ::
551 mpc85xx_idle_wakeup(platform_t plat, int cpu)