2 * Copyright 2002 by Peter Grehan. All rights reserved.
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 * 3. The name of the author may not be used to endorse or promote products
13 * derived from this software without specific prior written permission.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
20 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
21 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
22 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
23 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 * Mac-io ATA controller
34 #include <sys/param.h>
35 #include <sys/systm.h>
36 #include <sys/kernel.h>
37 #include <sys/module.h>
39 #include <sys/malloc.h>
41 #include <sys/taskqueue.h>
43 #include <machine/stdarg.h>
44 #include <machine/resource.h>
45 #include <machine/bus.h>
48 #include <dev/ata/ata-all.h>
51 #include <dev/ofw/ofw_bus.h>
53 #include "ata_dbdma.h"
56 * Offset to control registers from base
58 #define ATA_MACIO_ALTOFFSET 0x160
61 * Define the gap between registers
63 #define ATA_MACIO_REGGAP 16
66 * Whether or not to bind to the DBDMA IRQ
68 #define USE_DBDMA_IRQ 0
73 #define ATA_MACIO_TIMINGREG 0x200
75 #define ATA_TIME_TO_TICK(rev,time) howmany(time, (rev == 4) ? 15 : 30)
76 #define PIO_REC_OFFSET 4
79 #define DMA_REC_OFFSET 1
84 int cycle; /* minimum cycle time [ns] */
85 int active; /* minimum command active time [ns] */
88 struct ide_timings pio_timings[5] = {
89 { 600, 180 }, /* PIO 0 */
90 { 390, 150 }, /* PIO 1 */
91 { 240, 105 }, /* PIO 2 */
92 { 180, 90 }, /* PIO 3 */
93 { 120, 75 } /* PIO 4 */
96 static const struct ide_timings dma_timings[3] = {
97 { 480, 240 }, /* WDMA 0 */
98 { 165, 90 }, /* WDMA 1 */
99 { 120, 75 } /* WDMA 2 */
102 static const struct ide_timings udma_timings[5] = {
103 { 120, 180 }, /* UDMA 0 */
104 { 90, 150 }, /* UDMA 1 */
105 { 60, 120 }, /* UDMA 2 */
106 { 45, 90 }, /* UDMA 3 */
107 { 30, 90 } /* UDMA 4 */
111 * Define the macio ata bus attachment.
113 static int ata_macio_probe(device_t dev);
114 static void ata_macio_setmode(device_t parent, device_t dev);
115 static int ata_macio_attach(device_t dev);
116 static int ata_macio_begin_transaction(struct ata_request *request);
118 static device_method_t ata_macio_methods[] = {
119 /* Device interface */
120 DEVMETHOD(device_probe, ata_macio_probe),
121 DEVMETHOD(device_attach, ata_macio_attach),
124 DEVMETHOD(ata_setmode, ata_macio_setmode),
128 struct ata_macio_softc {
129 struct ata_dbdma_channel sc_ch;
133 struct resource *sc_mem;
135 uint32_t udmaconf[2];
136 uint32_t wdmaconf[2];
140 static driver_t ata_macio_driver = {
143 sizeof(struct ata_macio_softc),
146 DRIVER_MODULE(ata, macio, ata_macio_driver, ata_devclass, 0, 0);
147 MODULE_DEPEND(ata, ata, 1, 1, 1);
150 ata_macio_probe(device_t dev)
152 const char *type = ofw_bus_get_type(dev);
153 const char *name = ofw_bus_get_name(dev);
154 struct ata_macio_softc *sc;
155 struct ata_channel *ch;
158 if (strcmp(type, "ata") != 0 &&
159 strcmp(type, "ide") != 0)
162 sc = device_get_softc(dev);
163 bzero(sc, sizeof(struct ata_macio_softc));
164 ch = &sc->sc_ch.sc_ch;
166 if (strcmp(name,"ata-4") == 0) {
168 sc->max_mode = ATA_UDMA4;
171 sc->max_mode = ATA_WDMA2;
175 sc->sc_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
177 if (sc->sc_mem == NULL) {
178 device_printf(dev, "could not allocate memory\n");
183 * Set up the resource vectors
185 for (i = ATA_DATA; i <= ATA_COMMAND; i++) {
186 ch->r_io[i].res = sc->sc_mem;
187 ch->r_io[i].offset = i * ATA_MACIO_REGGAP;
189 ch->r_io[ATA_CONTROL].res = sc->sc_mem;
190 ch->r_io[ATA_CONTROL].offset = ATA_MACIO_ALTOFFSET;
191 ata_default_registers(dev);
194 ch->flags |= ATA_USE_16BIT;
197 return (ata_probe(dev));
201 ata_macio_attach(device_t dev)
203 struct ata_macio_softc *sc = device_get_softc(dev);
207 int dbdma_irq_rid = 1;
208 struct resource *dbdma_irq;
212 /* Init DMA engine */
214 sc->sc_ch.dbdma_rid = 1;
215 sc->sc_ch.dbdma_regs = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
216 &sc->sc_ch.dbdma_rid, RF_ACTIVE);
218 ata_dbdma_dmainit(dev);
220 /* Configure initial timings */
221 timingreg = bus_read_4(sc->sc_mem, ATA_MACIO_TIMINGREG);
223 sc->udmaconf[0] = sc->udmaconf[1] = timingreg & 0x1ff00000;
224 sc->wdmaconf[0] = sc->wdmaconf[1] = timingreg & 0x001ffc00;
225 sc->pioconf[0] = sc->pioconf[1] = timingreg & 0x000003ff;
227 sc->udmaconf[0] = sc->udmaconf[1] = 0;
228 sc->wdmaconf[0] = sc->wdmaconf[1] = timingreg & 0xfffff800;
229 sc->pioconf[0] = sc->pioconf[1] = timingreg & 0x000007ff;
233 /* Bind to DBDMA interrupt as well */
235 if ((dbdma_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ,
236 &dbdma_irq_rid, RF_SHAREABLE | RF_ACTIVE)) != NULL) {
237 bus_setup_intr(dev, dbdma_irq, ATA_INTR_FLAGS, NULL,
238 (driver_intr_t *)ata_interrupt, sc,&cookie);
242 /* Set begin_transaction */
243 sc->sc_ch.sc_ch.hw.begin_transaction = ata_macio_begin_transaction;
245 return ata_attach(dev);
249 ata_macio_setmode(device_t parent, device_t dev)
251 struct ata_device *atadev = device_get_softc(dev);
252 struct ata_macio_softc *sc = device_get_softc(parent);
253 int mode = atadev->mode;
255 int min_cycle = 0, min_active = 0;
256 int cycle_tick = 0, act_tick = 0, inact_tick = 0, half_tick;
258 mode = ata_limit_mode(dev, mode, sc->max_mode);
260 if (ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode))
265 if ((mode & ATA_DMA_MASK) == ATA_UDMA0) {
266 min_cycle = udma_timings[mode & ATA_MODE_MASK].cycle;
267 min_active = udma_timings[mode & ATA_MODE_MASK].active;
269 cycle_tick = ATA_TIME_TO_TICK(sc->rev,min_cycle);
270 act_tick = ATA_TIME_TO_TICK(sc->rev,min_active);
272 /* mask: 0x1ff00000 */
273 sc->udmaconf[atadev->unit] =
274 (cycle_tick << 21) | (act_tick << 25) | 0x100000;
275 } else if ((mode & ATA_DMA_MASK) == ATA_WDMA0) {
276 min_cycle = dma_timings[mode & ATA_MODE_MASK].cycle;
277 min_active = dma_timings[mode & ATA_MODE_MASK].active;
279 cycle_tick = ATA_TIME_TO_TICK(sc->rev,min_cycle);
280 act_tick = ATA_TIME_TO_TICK(sc->rev,min_active);
283 inact_tick = cycle_tick - act_tick;
284 /* mask: 0x001ffc00 */
285 sc->wdmaconf[atadev->unit] =
286 (act_tick << 10) | (inact_tick << 15);
288 inact_tick = cycle_tick - act_tick - DMA_REC_OFFSET;
289 if (inact_tick < DMA_REC_MIN)
290 inact_tick = DMA_REC_MIN;
291 half_tick = 0; /* XXX */
293 /* mask: 0xfffff800 */
294 sc->wdmaconf[atadev->unit] = (half_tick << 21)
295 | (inact_tick << 16) | (act_tick << 11);
299 pio_timings[(mode & ATA_MODE_MASK) - ATA_PIO0].cycle;
301 pio_timings[(mode & ATA_MODE_MASK) - ATA_PIO0].active;
303 cycle_tick = ATA_TIME_TO_TICK(sc->rev,min_cycle);
304 act_tick = ATA_TIME_TO_TICK(sc->rev,min_active);
307 inact_tick = cycle_tick - act_tick;
309 /* mask: 0x000003ff */
310 sc->pioconf[atadev->unit] =
311 (inact_tick << 5) | act_tick;
313 if (act_tick < PIO_ACT_MIN)
314 act_tick = PIO_ACT_MIN;
316 inact_tick = cycle_tick - act_tick - PIO_REC_OFFSET;
317 if (inact_tick < PIO_REC_MIN)
318 inact_tick = PIO_REC_MIN;
320 /* mask: 0x000007ff */
321 sc->pioconf[atadev->unit] =
322 (inact_tick << 5) | act_tick;
328 ata_macio_begin_transaction(struct ata_request *request)
330 struct ata_device *atadev = device_get_softc(request->dev);
331 struct ata_macio_softc *sc = device_get_softc(request->parent);
333 bus_write_4(sc->sc_mem, ATA_MACIO_TIMINGREG,
334 sc->udmaconf[atadev->unit] | sc->wdmaconf[atadev->unit]
335 | sc->pioconf[atadev->unit]);
337 return ata_begin_transaction(request);