2 * Copyright 2002 by Peter Grehan. All rights reserved.
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 * 3. The name of the author may not be used to endorse or promote products
13 * derived from this software without specific prior written permission.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
20 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
21 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
22 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
23 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 #include <sys/cdefs.h>
29 __FBSDID("$FreeBSD$");
32 * Mac-io ATA controller
34 #include <sys/param.h>
35 #include <sys/systm.h>
36 #include <sys/kernel.h>
37 #include <sys/module.h>
39 #include <sys/malloc.h>
41 #include <sys/taskqueue.h>
43 #include <machine/stdarg.h>
44 #include <machine/resource.h>
45 #include <machine/bus.h>
48 #include <dev/ata/ata-all.h>
51 #include <dev/ofw/ofw_bus.h>
53 #include "ata_dbdma.h"
56 * Offset to control registers from base
58 #define ATA_MACIO_ALTOFFSET 0x160
61 * Define the gap between registers
63 #define ATA_MACIO_REGGAP 16
66 * Whether or not to bind to the DBDMA IRQ
68 #define USE_DBDMA_IRQ 0
73 #define ATA_MACIO_TIMINGREG 0x200
75 #define ATA_TIME_TO_TICK(rev,time) howmany(time, (rev == 4) ? 15 : 30)
76 #define PIO_REC_OFFSET 4
79 #define DMA_REC_OFFSET 1
84 int cycle; /* minimum cycle time [ns] */
85 int active; /* minimum command active time [ns] */
88 static const struct ide_timings pio_timings[5] = {
89 { 600, 180 }, /* PIO 0 */
90 { 390, 150 }, /* PIO 1 */
91 { 240, 105 }, /* PIO 2 */
92 { 180, 90 }, /* PIO 3 */
93 { 120, 75 } /* PIO 4 */
96 static const struct ide_timings dma_timings[3] = {
97 { 480, 240 }, /* WDMA 0 */
98 { 165, 90 }, /* WDMA 1 */
99 { 120, 75 } /* WDMA 2 */
102 static const struct ide_timings udma_timings[5] = {
103 { 120, 180 }, /* UDMA 0 */
104 { 90, 150 }, /* UDMA 1 */
105 { 60, 120 }, /* UDMA 2 */
106 { 45, 90 }, /* UDMA 3 */
107 { 30, 90 } /* UDMA 4 */
111 * Define the macio ata bus attachment.
113 static int ata_macio_probe(device_t dev);
114 static int ata_macio_setmode(device_t dev, int target, int mode);
115 static int ata_macio_attach(device_t dev);
116 static int ata_macio_begin_transaction(struct ata_request *request);
117 static int ata_macio_suspend(device_t dev);
118 static int ata_macio_resume(device_t dev);
120 static device_method_t ata_macio_methods[] = {
121 /* Device interface */
122 DEVMETHOD(device_probe, ata_macio_probe),
123 DEVMETHOD(device_attach, ata_macio_attach),
124 DEVMETHOD(device_suspend, ata_macio_suspend),
125 DEVMETHOD(device_resume, ata_macio_resume),
128 DEVMETHOD(ata_setmode, ata_macio_setmode),
132 struct ata_macio_softc {
133 struct ata_dbdma_channel sc_ch;
137 struct resource *sc_mem;
139 uint32_t udmaconf[2];
140 uint32_t wdmaconf[2];
144 static driver_t ata_macio_driver = {
147 sizeof(struct ata_macio_softc),
150 DRIVER_MODULE(ata, macio, ata_macio_driver, ata_devclass, NULL, NULL);
151 MODULE_DEPEND(ata, ata, 1, 1, 1);
154 ata_macio_probe(device_t dev)
156 const char *type = ofw_bus_get_type(dev);
157 const char *name = ofw_bus_get_name(dev);
158 struct ata_macio_softc *sc;
160 if (strcmp(type, "ata") != 0 &&
161 strcmp(type, "ide") != 0)
164 sc = device_get_softc(dev);
165 bzero(sc, sizeof(struct ata_macio_softc));
167 if (strcmp(name,"ata-4") == 0) {
168 device_set_desc(dev,"Apple MacIO Ultra ATA Controller");
170 sc->max_mode = ATA_UDMA4;
172 device_set_desc(dev,"Apple MacIO ATA Controller");
174 sc->max_mode = ATA_WDMA2;
177 return (ata_probe(dev));
181 ata_macio_attach(device_t dev)
183 struct ata_macio_softc *sc = device_get_softc(dev);
185 struct ata_channel *ch;
193 ch = &sc->sc_ch.sc_ch;
194 sc->sc_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
196 if (sc->sc_mem == NULL) {
197 device_printf(dev, "could not allocate memory\n");
202 * Set up the resource vectors
204 for (i = ATA_DATA; i <= ATA_COMMAND; i++) {
205 ch->r_io[i].res = sc->sc_mem;
206 ch->r_io[i].offset = i * ATA_MACIO_REGGAP;
208 ch->r_io[ATA_CONTROL].res = sc->sc_mem;
209 ch->r_io[ATA_CONTROL].offset = ATA_MACIO_ALTOFFSET;
210 ata_default_registers(dev);
213 ch->flags |= ATA_USE_16BIT | ATA_NO_ATAPI_DMA;
217 int dbdma_irq_rid = 1;
218 struct resource *dbdma_irq;
222 /* Init DMA engine */
224 sc->sc_ch.dbdma_rid = 1;
225 sc->sc_ch.dbdma_regs = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
226 &sc->sc_ch.dbdma_rid, RF_ACTIVE);
228 ata_dbdma_dmainit(dev);
230 /* Configure initial timings */
231 timingreg = bus_read_4(sc->sc_mem, ATA_MACIO_TIMINGREG);
233 sc->udmaconf[0] = sc->udmaconf[1] = timingreg & 0x1ff00000;
234 sc->wdmaconf[0] = sc->wdmaconf[1] = timingreg & 0x001ffc00;
235 sc->pioconf[0] = sc->pioconf[1] = timingreg & 0x000003ff;
237 sc->udmaconf[0] = sc->udmaconf[1] = 0;
238 sc->wdmaconf[0] = sc->wdmaconf[1] = timingreg & 0xfffff800;
239 sc->pioconf[0] = sc->pioconf[1] = timingreg & 0x000007ff;
243 /* Bind to DBDMA interrupt as well */
245 if ((dbdma_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ,
246 &dbdma_irq_rid, RF_SHAREABLE | RF_ACTIVE)) != NULL) {
247 bus_setup_intr(dev, dbdma_irq, ATA_INTR_FLAGS, NULL,
248 (driver_intr_t *)ata_interrupt, sc,&cookie);
252 /* Set begin_transaction */
253 sc->sc_ch.sc_ch.hw.begin_transaction = ata_macio_begin_transaction;
255 return ata_attach(dev);
259 ata_macio_setmode(device_t dev, int target, int mode)
261 struct ata_macio_softc *sc = device_get_softc(dev);
263 int min_cycle = 0, min_active = 0;
264 int cycle_tick = 0, act_tick = 0, inact_tick = 0, half_tick;
266 mode = min(mode, sc->max_mode);
268 if ((mode & ATA_DMA_MASK) == ATA_UDMA0) {
269 min_cycle = udma_timings[mode & ATA_MODE_MASK].cycle;
270 min_active = udma_timings[mode & ATA_MODE_MASK].active;
272 cycle_tick = ATA_TIME_TO_TICK(sc->rev,min_cycle);
273 act_tick = ATA_TIME_TO_TICK(sc->rev,min_active);
275 /* mask: 0x1ff00000 */
276 sc->udmaconf[target] =
277 (cycle_tick << 21) | (act_tick << 25) | 0x100000;
278 } else if ((mode & ATA_DMA_MASK) == ATA_WDMA0) {
279 min_cycle = dma_timings[mode & ATA_MODE_MASK].cycle;
280 min_active = dma_timings[mode & ATA_MODE_MASK].active;
282 cycle_tick = ATA_TIME_TO_TICK(sc->rev,min_cycle);
283 act_tick = ATA_TIME_TO_TICK(sc->rev,min_active);
286 inact_tick = cycle_tick - act_tick;
287 /* mask: 0x001ffc00 */
288 sc->wdmaconf[target] =
289 (act_tick << 10) | (inact_tick << 15);
291 inact_tick = cycle_tick - act_tick - DMA_REC_OFFSET;
292 if (inact_tick < DMA_REC_MIN)
293 inact_tick = DMA_REC_MIN;
294 half_tick = 0; /* XXX */
296 /* mask: 0xfffff800 */
297 sc->wdmaconf[target] = (half_tick << 21)
298 | (inact_tick << 16) | (act_tick << 11);
302 pio_timings[(mode & ATA_MODE_MASK) - ATA_PIO0].cycle;
304 pio_timings[(mode & ATA_MODE_MASK) - ATA_PIO0].active;
306 cycle_tick = ATA_TIME_TO_TICK(sc->rev,min_cycle);
307 act_tick = ATA_TIME_TO_TICK(sc->rev,min_active);
310 inact_tick = cycle_tick - act_tick;
312 /* mask: 0x000003ff */
313 sc->pioconf[target] =
314 (inact_tick << 5) | act_tick;
316 if (act_tick < PIO_ACT_MIN)
317 act_tick = PIO_ACT_MIN;
319 inact_tick = cycle_tick - act_tick - PIO_REC_OFFSET;
320 if (inact_tick < PIO_REC_MIN)
321 inact_tick = PIO_REC_MIN;
323 /* mask: 0x000007ff */
324 sc->pioconf[target] =
325 (inact_tick << 5) | act_tick;
333 ata_macio_begin_transaction(struct ata_request *request)
335 struct ata_macio_softc *sc = device_get_softc(request->parent);
337 bus_write_4(sc->sc_mem, ATA_MACIO_TIMINGREG,
338 sc->udmaconf[request->unit] | sc->wdmaconf[request->unit]
339 | sc->pioconf[request->unit]);
341 return ata_begin_transaction(request);
345 ata_macio_suspend(device_t dev)
347 struct ata_dbdma_channel *ch = device_get_softc(dev);
350 if (!ch->sc_ch.attached)
353 error = ata_suspend(dev);
354 dbdma_save_state(ch->dbdma);
360 ata_macio_resume(device_t dev)
362 struct ata_dbdma_channel *ch = device_get_softc(dev);
365 if (!ch->sc_ch.attached)
368 dbdma_restore_state(ch->dbdma);
369 error = ata_resume(dev);