2 * SPDX-License-Identifier: BSD-3-Clause
4 * Copyright (c) 2006 Michael Lorenz
5 * Copyright 2008 by Nathan Whitehorn
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. The name of the author may not be used to endorse or promote products
17 * derived from this software without specific prior written permission.
19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
20 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
21 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
22 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
23 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
24 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
26 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
27 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
33 #include <sys/cdefs.h>
34 __FBSDID("$FreeBSD$");
36 #include <sys/param.h>
37 #include <sys/systm.h>
38 #include <sys/module.h>
41 #include <sys/kernel.h>
42 #include <sys/clock.h>
43 #include <sys/reboot.h>
45 #include <dev/ofw/ofw_bus.h>
46 #include <dev/ofw/openfirm.h>
48 #include <machine/bus.h>
49 #include <machine/intr_machdep.h>
50 #include <machine/md_var.h>
51 #include <machine/pio.h>
52 #include <machine/resource.h>
59 #include <dev/adb/adb.h>
68 static int cuda_probe(device_t);
69 static int cuda_attach(device_t);
70 static int cuda_detach(device_t);
72 static u_int cuda_adb_send(device_t dev, u_char command_byte, int len,
73 u_char *data, u_char poll);
74 static u_int cuda_adb_autopoll(device_t dev, uint16_t mask);
75 static u_int cuda_poll(device_t dev);
76 static void cuda_send_inbound(struct cuda_softc *sc);
77 static void cuda_send_outbound(struct cuda_softc *sc);
78 static void cuda_shutdown(void *xsc, int howto);
83 static int cuda_gettime(device_t dev, struct timespec *ts);
84 static int cuda_settime(device_t dev, struct timespec *ts);
86 static device_method_t cuda_methods[] = {
87 /* Device interface */
88 DEVMETHOD(device_probe, cuda_probe),
89 DEVMETHOD(device_attach, cuda_attach),
90 DEVMETHOD(device_detach, cuda_detach),
91 DEVMETHOD(device_shutdown, bus_generic_shutdown),
92 DEVMETHOD(device_suspend, bus_generic_suspend),
93 DEVMETHOD(device_resume, bus_generic_resume),
95 /* ADB bus interface */
96 DEVMETHOD(adb_hb_send_raw_packet, cuda_adb_send),
97 DEVMETHOD(adb_hb_controller_poll, cuda_poll),
98 DEVMETHOD(adb_hb_set_autopoll_mask, cuda_adb_autopoll),
100 /* Clock interface */
101 DEVMETHOD(clock_gettime, cuda_gettime),
102 DEVMETHOD(clock_settime, cuda_settime),
107 static driver_t cuda_driver = {
110 sizeof(struct cuda_softc),
113 static devclass_t cuda_devclass;
115 DRIVER_MODULE(cuda, macio, cuda_driver, cuda_devclass, 0, 0);
116 DRIVER_MODULE(adb, cuda, adb_driver, adb_devclass, 0, 0);
118 static void cuda_intr(void *arg);
119 static uint8_t cuda_read_reg(struct cuda_softc *sc, u_int offset);
120 static void cuda_write_reg(struct cuda_softc *sc, u_int offset, uint8_t value);
121 static void cuda_idle(struct cuda_softc *);
122 static void cuda_tip(struct cuda_softc *);
123 static void cuda_clear_tip(struct cuda_softc *);
124 static void cuda_in(struct cuda_softc *);
125 static void cuda_out(struct cuda_softc *);
126 static void cuda_toggle_ack(struct cuda_softc *);
127 static void cuda_ack_off(struct cuda_softc *);
128 static int cuda_intr_state(struct cuda_softc *);
131 cuda_probe(device_t dev)
133 const char *type = ofw_bus_get_type(dev);
135 if (strcmp(type, "via-cuda") != 0)
138 device_set_desc(dev, CUDA_DEVSTR);
143 cuda_attach(device_t dev)
145 struct cuda_softc *sc;
149 phandle_t node,child;
151 sc = device_get_softc(dev);
155 sc->sc_memr = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
156 &sc->sc_memrid, RF_ACTIVE);
158 if (sc->sc_memr == NULL) {
159 device_printf(dev, "Could not alloc mem resource!\n");
164 sc->sc_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->sc_irqrid,
166 if (sc->sc_irq == NULL) {
167 device_printf(dev, "could not allocate interrupt\n");
168 bus_release_resource(dev, SYS_RES_MEMORY, sc->sc_memrid,
173 if (bus_setup_intr(dev, sc->sc_irq, INTR_TYPE_MISC | INTR_MPSAFE
174 | INTR_ENTROPY, NULL, cuda_intr, dev, &sc->sc_ih) != 0) {
175 device_printf(dev, "could not setup interrupt\n");
176 bus_release_resource(dev, SYS_RES_MEMORY, sc->sc_memrid,
178 bus_release_resource(dev, SYS_RES_IRQ, sc->sc_irqrid,
183 mtx_init(&sc->sc_mutex,"cuda",NULL,MTX_DEF | MTX_RECURSE);
189 sc->sc_state = CUDA_NOTREADY;
193 STAILQ_INIT(&sc->sc_inq);
194 STAILQ_INIT(&sc->sc_outq);
195 STAILQ_INIT(&sc->sc_freeq);
197 for (i = 0; i < CUDA_MAXPACKETS; i++)
198 STAILQ_INSERT_TAIL(&sc->sc_freeq, &sc->sc_pkts[i], pkt_q);
202 reg = cuda_read_reg(sc, vDirB);
203 reg |= 0x30; /* register B bits 4 and 5: outputs */
204 cuda_write_reg(sc, vDirB, reg);
206 reg = cuda_read_reg(sc, vDirB);
207 reg &= 0xf7; /* register B bit 3: input */
208 cuda_write_reg(sc, vDirB, reg);
210 reg = cuda_read_reg(sc, vACR);
211 reg &= ~vSR_OUT; /* make sure SR is set to IN */
212 cuda_write_reg(sc, vACR, reg);
214 cuda_write_reg(sc, vACR, (cuda_read_reg(sc, vACR) | 0x0c) & ~0x10);
216 sc->sc_state = CUDA_IDLE; /* used by all types of hardware */
218 cuda_write_reg(sc, vIER, 0x84); /* make sure VIA interrupts are on */
220 cuda_idle(sc); /* reset ADB */
224 i = cuda_read_reg(sc, vSR); /* clear interrupt */
225 cuda_write_reg(sc, vIER, 0x04); /* no interrupts while clearing */
226 cuda_idle(sc); /* reset state to idle */
228 cuda_tip(sc); /* signal start of frame */
234 cuda_idle(sc); /* back to idle state */
235 i = cuda_read_reg(sc, vSR); /* clear interrupt */
236 cuda_write_reg(sc, vIER, 0x84); /* ints ok now */
238 /* Initialize child buses (ADB) */
239 node = ofw_bus_get_node(dev);
241 for (child = OF_child(node); child != 0; child = OF_peer(child)) {
244 memset(name, 0, sizeof(name));
245 OF_getprop(child, "name", name, sizeof(name));
248 device_printf(dev, "CUDA child <%s>\n",name);
250 if (strncmp(name, "adb", 4) == 0) {
251 sc->adb_bus = device_add_child(dev,"adb",-1);
255 clock_register(dev, 1000);
256 EVENTHANDLER_REGISTER(shutdown_final, cuda_shutdown, sc,
259 return (bus_generic_attach(dev));
262 static int cuda_detach(device_t dev) {
263 struct cuda_softc *sc;
265 sc = device_get_softc(dev);
267 bus_teardown_intr(dev, sc->sc_irq, sc->sc_ih);
268 bus_release_resource(dev, SYS_RES_IRQ, sc->sc_irqrid, sc->sc_irq);
269 bus_release_resource(dev, SYS_RES_MEMORY, sc->sc_memrid, sc->sc_memr);
270 mtx_destroy(&sc->sc_mutex);
272 return (bus_generic_detach(dev));
276 cuda_read_reg(struct cuda_softc *sc, u_int offset) {
277 return (bus_read_1(sc->sc_memr, offset));
281 cuda_write_reg(struct cuda_softc *sc, u_int offset, uint8_t value) {
282 bus_write_1(sc->sc_memr, offset, value);
286 cuda_idle(struct cuda_softc *sc)
290 reg = cuda_read_reg(sc, vBufB);
291 reg |= (vPB4 | vPB5);
292 cuda_write_reg(sc, vBufB, reg);
296 cuda_tip(struct cuda_softc *sc)
300 reg = cuda_read_reg(sc, vBufB);
302 cuda_write_reg(sc, vBufB, reg);
306 cuda_clear_tip(struct cuda_softc *sc)
310 reg = cuda_read_reg(sc, vBufB);
312 cuda_write_reg(sc, vBufB, reg);
316 cuda_in(struct cuda_softc *sc)
320 reg = cuda_read_reg(sc, vACR);
322 cuda_write_reg(sc, vACR, reg);
326 cuda_out(struct cuda_softc *sc)
330 reg = cuda_read_reg(sc, vACR);
332 cuda_write_reg(sc, vACR, reg);
336 cuda_toggle_ack(struct cuda_softc *sc)
340 reg = cuda_read_reg(sc, vBufB);
342 cuda_write_reg(sc, vBufB, reg);
346 cuda_ack_off(struct cuda_softc *sc)
350 reg = cuda_read_reg(sc, vBufB);
352 cuda_write_reg(sc, vBufB, reg);
356 cuda_intr_state(struct cuda_softc *sc)
358 return ((cuda_read_reg(sc, vBufB) & vPB3) == 0);
362 cuda_send(void *cookie, int poll, int length, uint8_t *msg)
364 struct cuda_softc *sc = cookie;
365 device_t dev = sc->sc_dev;
366 struct cuda_packet *pkt;
368 if (sc->sc_state == CUDA_NOTREADY)
371 mtx_lock(&sc->sc_mutex);
373 pkt = STAILQ_FIRST(&sc->sc_freeq);
375 mtx_unlock(&sc->sc_mutex);
379 pkt->len = length - 1;
381 memcpy(pkt->data, &msg[1], pkt->len);
383 STAILQ_REMOVE_HEAD(&sc->sc_freeq, pkt_q);
384 STAILQ_INSERT_TAIL(&sc->sc_outq, pkt, pkt_q);
387 * If we already are sending a packet, we should bail now that this
388 * one has been added to the queue.
391 if (sc->sc_waiting) {
392 mtx_unlock(&sc->sc_mutex);
396 cuda_send_outbound(sc);
397 mtx_unlock(&sc->sc_mutex);
399 if (sc->sc_polling || poll || cold)
406 cuda_send_outbound(struct cuda_softc *sc)
408 struct cuda_packet *pkt;
410 mtx_assert(&sc->sc_mutex, MA_OWNED);
412 pkt = STAILQ_FIRST(&sc->sc_outq);
416 sc->sc_out_length = pkt->len + 1;
417 memcpy(sc->sc_out, &pkt->type, pkt->len + 1);
420 STAILQ_REMOVE_HEAD(&sc->sc_outq, pkt_q);
421 STAILQ_INSERT_TAIL(&sc->sc_freeq, pkt, pkt_q);
425 cuda_poll(sc->sc_dev);
429 if (sc->sc_state == CUDA_IDLE && !cuda_intr_state(sc)) {
430 sc->sc_state = CUDA_OUT;
432 cuda_write_reg(sc, vSR, sc->sc_out[0]);
439 cuda_send_inbound(struct cuda_softc *sc)
442 struct cuda_packet *pkt;
446 mtx_lock(&sc->sc_mutex);
448 while ((pkt = STAILQ_FIRST(&sc->sc_inq)) != NULL) {
449 STAILQ_REMOVE_HEAD(&sc->sc_inq, pkt_q);
451 mtx_unlock(&sc->sc_mutex);
453 /* check if we have a handler for this message */
457 adb_receive_raw_packet(sc->adb_bus,
458 pkt->data[0],pkt->data[1],
459 pkt->len - 2,&pkt->data[2]);
461 adb_receive_raw_packet(sc->adb_bus,
462 pkt->data[0],pkt->data[1],0,NULL);
466 mtx_lock(&sc->sc_mutex);
467 switch (pkt->data[1]) {
472 memcpy(&sc->sc_rtc, &pkt->data[2],
479 mtx_unlock(&sc->sc_mutex);
483 * CUDA will throw errors if we miss a race between
484 * sending and receiving packets. This is already
485 * handled when we abort packet output to handle
486 * this packet in cuda_intr(). Thus, we ignore
491 device_printf(dev,"unknown CUDA command %d\n",
496 mtx_lock(&sc->sc_mutex);
498 STAILQ_INSERT_TAIL(&sc->sc_freeq, pkt, pkt_q);
501 mtx_unlock(&sc->sc_mutex);
505 cuda_poll(device_t dev)
507 struct cuda_softc *sc = device_get_softc(dev);
509 if (sc->sc_state == CUDA_IDLE && !cuda_intr_state(sc) &&
521 struct cuda_softc *sc;
523 int i, ending, restart_send, process_inbound;
527 sc = device_get_softc(dev);
529 mtx_lock(&sc->sc_mutex);
533 reg = cuda_read_reg(sc, vIFR);
534 if ((reg & vSR_INT) != vSR_INT) {
535 mtx_unlock(&sc->sc_mutex);
539 cuda_write_reg(sc, vIFR, 0x7f); /* Clear interrupt */
542 switch (sc->sc_state) {
545 * This is an unexpected packet, so grab the first (dummy)
546 * byte, set up the proper vars, and tell the chip we are
547 * starting to receive the packet by setting the TIP bit.
549 sc->sc_in[1] = cuda_read_reg(sc, vSR);
551 if (cuda_intr_state(sc) == 0) {
552 /* must have been a fake start */
554 if (sc->sc_waiting) {
557 sc->sc_state = CUDA_OUT;
560 cuda_write_reg(sc, vSR, sc->sc_out[1]);
571 sc->sc_state = CUDA_IN;
575 sc->sc_in[sc->sc_received] = cuda_read_reg(sc, vSR);
578 if (sc->sc_received > 255) {
579 /* bitch only once */
580 if (sc->sc_received == 256) {
581 device_printf(dev,"input overflow\n");
587 /* intr off means this is the last byte (end of frame) */
588 if (cuda_intr_state(sc) == 0) {
594 if (ending == 1) { /* end of message? */
595 struct cuda_packet *pkt;
597 /* reset vars and signal the end of this frame */
600 /* Queue up the packet */
601 pkt = STAILQ_FIRST(&sc->sc_freeq);
603 /* If we have a free packet, process it */
605 pkt->len = sc->sc_received - 2;
606 pkt->type = sc->sc_in[1];
607 memcpy(pkt->data, &sc->sc_in[2], pkt->len);
609 STAILQ_REMOVE_HEAD(&sc->sc_freeq, pkt_q);
610 STAILQ_INSERT_TAIL(&sc->sc_inq, pkt, pkt_q);
615 sc->sc_state = CUDA_IDLE;
619 * If there is something waiting to be sent out,
620 * set everything up and send the first byte.
622 if (sc->sc_waiting == 1) {
623 DELAY(1500); /* required */
625 sc->sc_state = CUDA_OUT;
628 * If the interrupt is on, we were too slow
629 * and the chip has already started to send
630 * something to us, so back out of the write
631 * and start a read cycle.
633 if (cuda_intr_state(sc)) {
637 sc->sc_state = CUDA_IDLE;
644 * If we got here, it's ok to start sending
645 * so load the first byte and tell the chip
649 cuda_write_reg(sc, vSR,
650 sc->sc_out[sc->sc_sent]);
658 i = cuda_read_reg(sc, vSR); /* reset SR-intr in IFR */
661 if (cuda_intr_state(sc)) { /* ADB intr low during write */
662 cuda_in(sc); /* make sure SR is set to IN */
664 sc->sc_sent = 0; /* must start all over */
665 sc->sc_state = CUDA_IDLE; /* new state */
667 sc->sc_waiting = 1; /* must retry when done with
670 goto switch_start; /* process next state right
674 if (sc->sc_out_length == sc->sc_sent) { /* check for done */
675 sc->sc_waiting = 0; /* done writing */
676 sc->sc_state = CUDA_IDLE; /* signal bus is idle */
681 cuda_write_reg(sc, vSR, sc->sc_out[sc->sc_sent]);
682 cuda_toggle_ack(sc); /* signal byte ready to
694 mtx_unlock(&sc->sc_mutex);
697 cuda_send_inbound(sc);
699 mtx_lock(&sc->sc_mutex);
700 /* If we have another packet waiting, set it up */
701 if (!sc->sc_waiting && sc->sc_state == CUDA_IDLE)
702 cuda_send_outbound(sc);
704 mtx_unlock(&sc->sc_mutex);
709 cuda_adb_send(device_t dev, u_char command_byte, int len, u_char *data,
712 struct cuda_softc *sc = device_get_softc(dev);
716 /* construct an ADB command packet and send it */
717 packet[0] = CUDA_ADB;
718 packet[1] = command_byte;
719 for (i = 0; i < len; i++)
720 packet[i + 2] = data[i];
722 cuda_send(sc, poll, len + 2, packet);
728 cuda_adb_autopoll(device_t dev, uint16_t mask) {
729 struct cuda_softc *sc = device_get_softc(dev);
731 uint8_t cmd[] = {CUDA_PSEUDO, CMD_AUTOPOLL, mask != 0};
733 mtx_lock(&sc->sc_mutex);
735 if (cmd[2] == sc->sc_autopoll) {
736 mtx_unlock(&sc->sc_mutex);
740 sc->sc_autopoll = -1;
741 cuda_send(sc, 1, 3, cmd);
743 mtx_unlock(&sc->sc_mutex);
749 cuda_shutdown(void *xsc, int howto)
751 struct cuda_softc *sc = xsc;
752 uint8_t cmd[] = {CUDA_PSEUDO, 0};
754 cmd[1] = (howto & RB_HALT) ? CMD_POWEROFF : CMD_RESET;
755 cuda_poll(sc->sc_dev);
756 cuda_send(sc, 1, 2, cmd);
759 cuda_poll(sc->sc_dev);
762 #define DIFF19041970 2082844800
765 cuda_gettime(device_t dev, struct timespec *ts)
767 struct cuda_softc *sc = device_get_softc(dev);
768 uint8_t cmd[] = {CUDA_PSEUDO, CMD_READ_RTC};
770 mtx_lock(&sc->sc_mutex);
772 cuda_send(sc, 1, 2, cmd);
773 if (sc->sc_rtc == -1)
774 mtx_sleep(&sc->sc_rtc, &sc->sc_mutex, 0, "rtc", 100);
776 ts->tv_sec = sc->sc_rtc - DIFF19041970;
778 mtx_unlock(&sc->sc_mutex);
784 cuda_settime(device_t dev, struct timespec *ts)
786 struct cuda_softc *sc = device_get_softc(dev);
787 uint8_t cmd[] = {CUDA_PSEUDO, CMD_WRITE_RTC, 0, 0, 0, 0};
790 sec = ts->tv_sec + DIFF19041970;
791 memcpy(&cmd[2], &sec, sizeof(sec));
793 mtx_lock(&sc->sc_mutex);
794 cuda_send(sc, 0, 6, cmd);
795 mtx_unlock(&sc->sc_mutex);