sys/powerpc/powermac/cuda.c

   1 /*-
   2  * SPDX-License-Identifier: BSD-3-Clause
   3  *
   4  * Copyright (c) 2006 Michael Lorenz
   5  * Copyright 2008 by Nathan Whitehorn
   6  * All rights reserved.
   7  *
   8  * Redistribution and use in source and binary forms, with or without
   9  * modification, are permitted provided that the following conditions
  10  * are met:
  11  * 1. Redistributions of source code must retain the above copyright
  12  *    notice, this list of conditions and the following disclaimer.
  13  * 2. Redistributions in binary form must reproduce the above copyright
  14  *    notice, this list of conditions and the following disclaimer in the
  15  *    documentation and/or other materials provided with the distribution.
  16  * 3. The name of the author may not be used to endorse or promote products
  17  *    derived from this software without specific prior written permission.
  18  *
  19  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  20  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  21  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  22  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  23  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
  24  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  25  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
  26  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  27  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  28  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  29  * SUCH DAMAGE.
  30  *
  31  */
  32
  33 #include <sys/cdefs.h>
  34 __FBSDID("$FreeBSD$");
  35
  36 #include <sys/param.h>
  37 #include <sys/systm.h>
  38 #include <sys/module.h>
  39 #include <sys/bus.h>
  40 #include <sys/conf.h>
  41 #include <sys/eventhandler.h>
  42 #include <sys/kernel.h>
  43 #include <sys/lock.h>
  44 #include <sys/mutex.h>
  45 #include <sys/clock.h>
  46 #include <sys/reboot.h>
  47
  48 #include <dev/ofw/ofw_bus.h>
  49 #include <dev/ofw/openfirm.h>
  50
  51 #include <machine/bus.h>
  52 #include <machine/intr_machdep.h>
  53 #include <machine/md_var.h>
  54 #include <machine/pio.h>
  55 #include <machine/resource.h>
  56
  57 #include <vm/vm.h>
  58 #include <vm/pmap.h>
  59
  60 #include <sys/rman.h>
  61
  62 #include <dev/adb/adb.h>
  63
  64 #include "clock_if.h"
  65 #include "cudavar.h"
  66 #include "viareg.h"
  67
  68 /*
  69  * MacIO interface
  70  */
  71 static int      cuda_probe(device_t);
  72 static int      cuda_attach(device_t);
  73 static int      cuda_detach(device_t);
  74
  75 static u_int    cuda_adb_send(device_t dev, u_char command_byte, int len,
  76     u_char *data, u_char poll);
  77 static u_int    cuda_adb_autopoll(device_t dev, uint16_t mask);
  78 static u_int    cuda_poll(device_t dev);
  79 static void     cuda_send_inbound(struct cuda_softc *sc);
  80 static void     cuda_send_outbound(struct cuda_softc *sc);
  81 static void     cuda_shutdown(void *xsc, int howto);
  82
  83 /*
  84  * Clock interface
  85  */
  86 static int cuda_gettime(device_t dev, struct timespec *ts);
  87 static int cuda_settime(device_t dev, struct timespec *ts);
  88
  89 static device_method_t  cuda_methods[] = {
  90         /* Device interface */
  91         DEVMETHOD(device_probe,         cuda_probe),
  92         DEVMETHOD(device_attach,        cuda_attach),
  93         DEVMETHOD(device_detach,        cuda_detach),
  94         DEVMETHOD(device_shutdown,      bus_generic_shutdown),
  95         DEVMETHOD(device_suspend,       bus_generic_suspend),
  96         DEVMETHOD(device_resume,        bus_generic_resume),
  97
  98         /* ADB bus interface */
  99         DEVMETHOD(adb_hb_send_raw_packet,       cuda_adb_send),
 100         DEVMETHOD(adb_hb_controller_poll,       cuda_poll),
 101         DEVMETHOD(adb_hb_set_autopoll_mask,     cuda_adb_autopoll),
 102
 103         /* Clock interface */
 104         DEVMETHOD(clock_gettime,        cuda_gettime),
 105         DEVMETHOD(clock_settime,        cuda_settime),
 106
 107         DEVMETHOD_END
 108 };
 109
 110 static driver_t cuda_driver = {
 111         "cuda",
 112         cuda_methods,
 113         sizeof(struct cuda_softc),
 114 };
 115
 116 static devclass_t cuda_devclass;
 117
 118 DRIVER_MODULE(cuda, macio, cuda_driver, cuda_devclass, 0, 0);
 119 DRIVER_MODULE(adb, cuda, adb_driver, adb_devclass, 0, 0);
 120
 121 static void cuda_intr(void *arg);
 122 static uint8_t cuda_read_reg(struct cuda_softc *sc, u_int offset);
 123 static void cuda_write_reg(struct cuda_softc *sc, u_int offset, uint8_t value);
 124 static void cuda_idle(struct cuda_softc *);
 125 static void cuda_tip(struct cuda_softc *);
 126 static void cuda_clear_tip(struct cuda_softc *);
 127 static void cuda_in(struct cuda_softc *);
 128 static void cuda_out(struct cuda_softc *);
 129 static void cuda_toggle_ack(struct cuda_softc *);
 130 static void cuda_ack_off(struct cuda_softc *);
 131 static int cuda_intr_state(struct cuda_softc *);
 132
 133 static int
 134 cuda_probe(device_t dev)
 135 {
 136         const char *type = ofw_bus_get_type(dev);
 137
 138         if (strcmp(type, "via-cuda") != 0)
 139                 return (ENXIO);
 140
 141         device_set_desc(dev, CUDA_DEVSTR);
 142         return (0);
 143 }
 144
 145 static int
 146 cuda_attach(device_t dev)
 147 {
 148         struct cuda_softc *sc;
 149
 150         volatile int i;
 151         uint8_t reg;
 152         phandle_t node,child;
 153
 154         sc = device_get_softc(dev);
 155         sc->sc_dev = dev;
 156
 157         sc->sc_memrid = 0;
 158         sc->sc_memr = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
 159             &sc->sc_memrid, RF_ACTIVE);
 160
 161         if (sc->sc_memr == NULL) {
 162                 device_printf(dev, "Could not alloc mem resource!\n");
 163                 return (ENXIO);
 164         }
 165
 166         sc->sc_irqrid = 0;
 167         sc->sc_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->sc_irqrid,
 168                 RF_ACTIVE);
 169         if (sc->sc_irq == NULL) {
 170                 device_printf(dev, "could not allocate interrupt\n");
 171                 bus_release_resource(dev, SYS_RES_MEMORY, sc->sc_memrid,
 172                     sc->sc_memr);
 173                 return (ENXIO);
 174         }
 175
 176         if (bus_setup_intr(dev, sc->sc_irq, INTR_TYPE_MISC | INTR_MPSAFE
 177             | INTR_ENTROPY, NULL, cuda_intr, dev, &sc->sc_ih) != 0) {
 178                 device_printf(dev, "could not setup interrupt\n");
 179                 bus_release_resource(dev, SYS_RES_MEMORY, sc->sc_memrid,
 180                     sc->sc_memr);
 181                 bus_release_resource(dev, SYS_RES_IRQ, sc->sc_irqrid,
 182                     sc->sc_irq);
 183                 return (ENXIO);
 184         }
 185
 186         mtx_init(&sc->sc_mutex,"cuda",NULL,MTX_DEF | MTX_RECURSE);
 187
 188         sc->sc_sent = 0;
 189         sc->sc_received = 0;
 190         sc->sc_waiting = 0;
 191         sc->sc_polling = 0;
 192         sc->sc_state = CUDA_NOTREADY;
 193         sc->sc_autopoll = 0;
 194         sc->sc_rtc = -1;
 195
 196         STAILQ_INIT(&sc->sc_inq);
 197         STAILQ_INIT(&sc->sc_outq);
 198         STAILQ_INIT(&sc->sc_freeq);
 199
 200         for (i = 0; i < CUDA_MAXPACKETS; i++)
 201                 STAILQ_INSERT_TAIL(&sc->sc_freeq, &sc->sc_pkts[i], pkt_q);
 202
 203         /* Init CUDA */
 204
 205         reg = cuda_read_reg(sc, vDirB);
 206         reg |= 0x30;    /* register B bits 4 and 5: outputs */
 207         cuda_write_reg(sc, vDirB, reg);
 208
 209         reg = cuda_read_reg(sc, vDirB);
 210         reg &= 0xf7;    /* register B bit 3: input */
 211         cuda_write_reg(sc, vDirB, reg);
 212
 213         reg = cuda_read_reg(sc, vACR);
 214         reg &= ~vSR_OUT;        /* make sure SR is set to IN */
 215         cuda_write_reg(sc, vACR, reg);
 216
 217         cuda_write_reg(sc, vACR, (cuda_read_reg(sc, vACR) | 0x0c) & ~0x10);
 218
 219         sc->sc_state = CUDA_IDLE;       /* used by all types of hardware */
 220
 221         cuda_write_reg(sc, vIER, 0x84); /* make sure VIA interrupts are on */
 222
 223         cuda_idle(sc);  /* reset ADB */
 224
 225         /* Reset CUDA */
 226
 227         i = cuda_read_reg(sc, vSR);     /* clear interrupt */
 228         cuda_write_reg(sc, vIER, 0x04); /* no interrupts while clearing */
 229         cuda_idle(sc);  /* reset state to idle */
 230         DELAY(150);
 231         cuda_tip(sc);   /* signal start of frame */
 232         DELAY(150);
 233         cuda_toggle_ack(sc);
 234         DELAY(150);
 235         cuda_clear_tip(sc);
 236         DELAY(150);
 237         cuda_idle(sc);  /* back to idle state */
 238         i = cuda_read_reg(sc, vSR);     /* clear interrupt */
 239         cuda_write_reg(sc, vIER, 0x84); /* ints ok now */
 240
 241         /* Initialize child buses (ADB) */
 242         node = ofw_bus_get_node(dev);
 243
 244         for (child = OF_child(node); child != 0; child = OF_peer(child)) {
 245                 char name[32];
 246
 247                 memset(name, 0, sizeof(name));
 248                 OF_getprop(child, "name", name, sizeof(name));
 249
 250                 if (bootverbose)
 251                         device_printf(dev, "CUDA child <%s>\n",name);
 252
 253                 if (strncmp(name, "adb", 4) == 0) {
 254                         sc->adb_bus = device_add_child(dev,"adb",-1);
 255                 }
 256         }
 257
 258         clock_register(dev, 1000);
 259         EVENTHANDLER_REGISTER(shutdown_final, cuda_shutdown, sc,
 260             SHUTDOWN_PRI_LAST);
 261
 262         return (bus_generic_attach(dev));
 263 }
 264
 265 static int cuda_detach(device_t dev) {
 266         struct cuda_softc *sc;
 267
 268         sc = device_get_softc(dev);
 269
 270         bus_teardown_intr(dev, sc->sc_irq, sc->sc_ih);
 271         bus_release_resource(dev, SYS_RES_IRQ, sc->sc_irqrid, sc->sc_irq);
 272         bus_release_resource(dev, SYS_RES_MEMORY, sc->sc_memrid, sc->sc_memr);
 273         mtx_destroy(&sc->sc_mutex);
 274
 275         return (bus_generic_detach(dev));
 276 }
 277
 278 static uint8_t
 279 cuda_read_reg(struct cuda_softc *sc, u_int offset) {
 280         return (bus_read_1(sc->sc_memr, offset));
 281 }
 282
 283 static void
 284 cuda_write_reg(struct cuda_softc *sc, u_int offset, uint8_t value) {
 285         bus_write_1(sc->sc_memr, offset, value);
 286 }
 287
 288 static void
 289 cuda_idle(struct cuda_softc *sc)
 290 {
 291         uint8_t reg;
 292
 293         reg = cuda_read_reg(sc, vBufB);
 294         reg |= (vPB4 | vPB5);
 295         cuda_write_reg(sc, vBufB, reg);
 296 }
 297
 298 static void
 299 cuda_tip(struct cuda_softc *sc)
 300 {
 301         uint8_t reg;
 302
 303         reg = cuda_read_reg(sc, vBufB);
 304         reg &= ~vPB5;
 305         cuda_write_reg(sc, vBufB, reg);
 306 }
 307
 308 static void
 309 cuda_clear_tip(struct cuda_softc *sc)
 310 {
 311         uint8_t reg;
 312
 313         reg = cuda_read_reg(sc, vBufB);
 314         reg |= vPB5;
 315         cuda_write_reg(sc, vBufB, reg);
 316 }
 317
 318 static void
 319 cuda_in(struct cuda_softc *sc)
 320 {
 321         uint8_t reg;
 322
 323         reg = cuda_read_reg(sc, vACR);
 324         reg &= ~vSR_OUT;
 325         cuda_write_reg(sc, vACR, reg);
 326 }
 327
 328 static void
 329 cuda_out(struct cuda_softc *sc)
 330 {
 331         uint8_t reg;
 332
 333         reg = cuda_read_reg(sc, vACR);
 334         reg |= vSR_OUT;
 335         cuda_write_reg(sc, vACR, reg);
 336 }
 337
 338 static void
 339 cuda_toggle_ack(struct cuda_softc *sc)
 340 {
 341         uint8_t reg;
 342
 343         reg = cuda_read_reg(sc, vBufB);
 344         reg ^= vPB4;
 345         cuda_write_reg(sc, vBufB, reg);
 346 }
 347
 348 static void
 349 cuda_ack_off(struct cuda_softc *sc)
 350 {
 351         uint8_t reg;
 352
 353         reg = cuda_read_reg(sc, vBufB);
 354         reg |= vPB4;
 355         cuda_write_reg(sc, vBufB, reg);
 356 }
 357
 358 static int
 359 cuda_intr_state(struct cuda_softc *sc)
 360 {
 361         return ((cuda_read_reg(sc, vBufB) & vPB3) == 0);
 362 }
 363
 364 static int
 365 cuda_send(void *cookie, int poll, int length, uint8_t *msg)
 366 {
 367         struct cuda_softc *sc = cookie;
 368         device_t dev = sc->sc_dev;
 369         struct cuda_packet *pkt;
 370
 371         if (sc->sc_state == CUDA_NOTREADY)
 372                 return (-1);
 373
 374         mtx_lock(&sc->sc_mutex);
 375
 376         pkt = STAILQ_FIRST(&sc->sc_freeq);
 377         if (pkt == NULL) {
 378                 mtx_unlock(&sc->sc_mutex);
 379                 return (-1);
 380         }
 381
 382         pkt->len = length - 1;
 383         pkt->type = msg[0];
 384         memcpy(pkt->data, &msg[1], pkt->len);
 385
 386         STAILQ_REMOVE_HEAD(&sc->sc_freeq, pkt_q);
 387         STAILQ_INSERT_TAIL(&sc->sc_outq, pkt, pkt_q);
 388
 389         /*
 390          * If we already are sending a packet, we should bail now that this
 391          * one has been added to the queue.
 392          */
 393
 394         if (sc->sc_waiting) {
 395                 mtx_unlock(&sc->sc_mutex);
 396                 return (0);
 397         }
 398
 399         cuda_send_outbound(sc);
 400         mtx_unlock(&sc->sc_mutex);
 401
 402         if (sc->sc_polling || poll || cold)
 403                 cuda_poll(dev);
 404
 405         return (0);
 406 }
 407
 408 static void
 409 cuda_send_outbound(struct cuda_softc *sc)
 410 {
 411         struct cuda_packet *pkt;
 412
 413         mtx_assert(&sc->sc_mutex, MA_OWNED);
 414
 415         pkt = STAILQ_FIRST(&sc->sc_outq);
 416         if (pkt == NULL)
 417                 return;
 418
 419         sc->sc_out_length = pkt->len + 1;
 420         memcpy(sc->sc_out, &pkt->type, pkt->len + 1);
 421         sc->sc_sent = 0;
 422
 423         STAILQ_REMOVE_HEAD(&sc->sc_outq, pkt_q);
 424         STAILQ_INSERT_TAIL(&sc->sc_freeq, pkt, pkt_q);
 425
 426         sc->sc_waiting = 1;
 427
 428         cuda_poll(sc->sc_dev);
 429
 430         DELAY(150);
 431
 432         if (sc->sc_state == CUDA_IDLE && !cuda_intr_state(sc)) {
 433                 sc->sc_state = CUDA_OUT;
 434                 cuda_out(sc);
 435                 cuda_write_reg(sc, vSR, sc->sc_out[0]);
 436                 cuda_ack_off(sc);
 437                 cuda_tip(sc);
 438         }
 439 }
 440
 441 static void
 442 cuda_send_inbound(struct cuda_softc *sc)
 443 {
 444         device_t dev;
 445         struct cuda_packet *pkt;
 446
 447         dev = sc->sc_dev;
 448
 449         mtx_lock(&sc->sc_mutex);
 450
 451         while ((pkt = STAILQ_FIRST(&sc->sc_inq)) != NULL) {
 452                 STAILQ_REMOVE_HEAD(&sc->sc_inq, pkt_q);
 453
 454                 mtx_unlock(&sc->sc_mutex);
 455
 456                 /* check if we have a handler for this message */
 457                 switch (pkt->type) {
 458                    case CUDA_ADB:
 459                         if (pkt->len > 2) {
 460                                 adb_receive_raw_packet(sc->adb_bus,
 461                                     pkt->data[0],pkt->data[1],
 462                                     pkt->len - 2,&pkt->data[2]);
 463                         } else {
 464                                 adb_receive_raw_packet(sc->adb_bus,
 465                                     pkt->data[0],pkt->data[1],0,NULL);
 466                         }
 467                         break;
 468                    case CUDA_PSEUDO:
 469                         mtx_lock(&sc->sc_mutex);
 470                         switch (pkt->data[1]) {
 471                         case CMD_AUTOPOLL:
 472                                 sc->sc_autopoll = 1;
 473                                 break;
 474                         case CMD_READ_RTC:
 475                                 memcpy(&sc->sc_rtc, &pkt->data[2],
 476                                     sizeof(sc->sc_rtc));
 477                                 wakeup(&sc->sc_rtc);
 478                                 break;
 479                         case CMD_WRITE_RTC:
 480                                 break;
 481                         }
 482                         mtx_unlock(&sc->sc_mutex);
 483                         break;
 484                    case CUDA_ERROR:
 485                         /*
 486                          * CUDA will throw errors if we miss a race between
 487                          * sending and receiving packets. This is already
 488                          * handled when we abort packet output to handle
 489                          * this packet in cuda_intr(). Thus, we ignore
 490                          * these messages.
 491                          */
 492                         break;
 493                    default:
 494                         device_printf(dev,"unknown CUDA command %d\n",
 495                             pkt->type);
 496                         break;
 497                 }
 498
 499                 mtx_lock(&sc->sc_mutex);
 500
 501                 STAILQ_INSERT_TAIL(&sc->sc_freeq, pkt, pkt_q);
 502         }
 503
 504         mtx_unlock(&sc->sc_mutex);
 505 }
 506
 507 static u_int
 508 cuda_poll(device_t dev)
 509 {
 510         struct cuda_softc *sc = device_get_softc(dev);
 511
 512         if (sc->sc_state == CUDA_IDLE && !cuda_intr_state(sc) &&
 513             !sc->sc_waiting)
 514                 return (0);
 515
 516         cuda_intr(dev);
 517         return (0);
 518 }
 519
 520 static void
 521 cuda_intr(void *arg)
 522 {
 523         device_t        dev;
 524         struct cuda_softc *sc;
 525         int ending, process_inbound;
 526         uint8_t reg;
 527
 528         dev = (device_t)arg;
 529         sc = device_get_softc(dev);
 530
 531         mtx_lock(&sc->sc_mutex);
 532
 533         process_inbound = 0;
 534         reg = cuda_read_reg(sc, vIFR);
 535         if ((reg & vSR_INT) != vSR_INT) {
 536                 mtx_unlock(&sc->sc_mutex);
 537                 return;
 538         }
 539
 540         cuda_write_reg(sc, vIFR, 0x7f); /* Clear interrupt */
 541
 542 switch_start:
 543         switch (sc->sc_state) {
 544         case CUDA_IDLE:
 545                 /*
 546                  * This is an unexpected packet, so grab the first (dummy)
 547                  * byte, set up the proper vars, and tell the chip we are
 548                  * starting to receive the packet by setting the TIP bit.
 549                  */
 550                 sc->sc_in[1] = cuda_read_reg(sc, vSR);
 551
 552                 if (cuda_intr_state(sc) == 0) {
 553                         /* must have been a fake start */
 554
 555                         if (sc->sc_waiting) {
 556                                 /* start over */
 557                                 DELAY(150);
 558                                 sc->sc_state = CUDA_OUT;
 559                                 sc->sc_sent = 0;
 560                                 cuda_out(sc);
 561                                 cuda_write_reg(sc, vSR, sc->sc_out[1]);
 562                                 cuda_ack_off(sc);
 563                                 cuda_tip(sc);
 564                         }
 565                         break;
 566                 }
 567
 568                 cuda_in(sc);
 569                 cuda_tip(sc);
 570
 571                 sc->sc_received = 1;
 572                 sc->sc_state = CUDA_IN;
 573                 break;
 574
 575         case CUDA_IN:
 576                 sc->sc_in[sc->sc_received] = cuda_read_reg(sc, vSR);
 577                 ending = 0;
 578
 579                 if (sc->sc_received > 255) {
 580                         /* bitch only once */
 581                         if (sc->sc_received == 256) {
 582                                 device_printf(dev,"input overflow\n");
 583                                 ending = 1;
 584                         }
 585                 } else
 586                         sc->sc_received++;
 587
 588                 /* intr off means this is the last byte (end of frame) */
 589                 if (cuda_intr_state(sc) == 0) {
 590                         ending = 1;
 591                 } else {
 592                         cuda_toggle_ack(sc);
 593                 }
 594
 595                 if (ending == 1) {      /* end of message? */
 596                         struct cuda_packet *pkt;
 597
 598                         /* reset vars and signal the end of this frame */
 599                         cuda_idle(sc);
 600
 601                         /* Queue up the packet */
 602                         pkt = STAILQ_FIRST(&sc->sc_freeq);
 603                         if (pkt != NULL) {
 604                                 /* If we have a free packet, process it */
 605
 606                                 pkt->len = sc->sc_received - 2;
 607                                 pkt->type = sc->sc_in[1];
 608                                 memcpy(pkt->data, &sc->sc_in[2], pkt->len);
 609
 610                                 STAILQ_REMOVE_HEAD(&sc->sc_freeq, pkt_q);
 611                                 STAILQ_INSERT_TAIL(&sc->sc_inq, pkt, pkt_q);
 612
 613                                 process_inbound = 1;
 614                         }
 615
 616                         sc->sc_state = CUDA_IDLE;
 617                         sc->sc_received = 0;
 618
 619                         /*
 620                          * If there is something waiting to be sent out,
 621                          * set everything up and send the first byte.
 622                          */
 623                         if (sc->sc_waiting == 1) {
 624                                 DELAY(1500);    /* required */
 625                                 sc->sc_sent = 0;
 626                                 sc->sc_state = CUDA_OUT;
 627
 628                                 /*
 629                                  * If the interrupt is on, we were too slow
 630                                  * and the chip has already started to send
 631                                  * something to us, so back out of the write
 632                                  * and start a read cycle.
 633                                  */
 634                                 if (cuda_intr_state(sc)) {
 635                                         cuda_in(sc);
 636                                         cuda_idle(sc);
 637                                         sc->sc_sent = 0;
 638                                         sc->sc_state = CUDA_IDLE;
 639                                         sc->sc_received = 0;
 640                                         DELAY(150);
 641                                         goto switch_start;
 642                                 }
 643
 644                                 /*
 645                                  * If we got here, it's ok to start sending
 646                                  * so load the first byte and tell the chip
 647                                  * we want to send.
 648                                  */
 649                                 cuda_out(sc);
 650                                 cuda_write_reg(sc, vSR,
 651                                     sc->sc_out[sc->sc_sent]);
 652                                 cuda_ack_off(sc);
 653                                 cuda_tip(sc);
 654                         }
 655                 }
 656                 break;
 657
 658         case CUDA_OUT:
 659                 cuda_read_reg(sc, vSR); /* reset SR-intr in IFR */
 660
 661                 sc->sc_sent++;
 662                 if (cuda_intr_state(sc)) {      /* ADB intr low during write */
 663                         cuda_in(sc);    /* make sure SR is set to IN */
 664                         cuda_idle(sc);
 665                         sc->sc_sent = 0;        /* must start all over */
 666                         sc->sc_state = CUDA_IDLE;       /* new state */
 667                         sc->sc_received = 0;
 668                         sc->sc_waiting = 1;     /* must retry when done with
 669                                                  * read */
 670                         DELAY(150);
 671                         goto switch_start;      /* process next state right
 672                                                  * now */
 673                         break;
 674                 }
 675                 if (sc->sc_out_length == sc->sc_sent) { /* check for done */
 676                         sc->sc_waiting = 0;     /* done writing */
 677                         sc->sc_state = CUDA_IDLE;       /* signal bus is idle */
 678                         cuda_in(sc);
 679                         cuda_idle(sc);
 680                 } else {
 681                         /* send next byte */
 682                         cuda_write_reg(sc, vSR, sc->sc_out[sc->sc_sent]);
 683                         cuda_toggle_ack(sc);    /* signal byte ready to
 684                                                          * shift */
 685                 }
 686                 break;
 687
 688         case CUDA_NOTREADY:
 689                 break;
 690
 691         default:
 692                 break;
 693         }
 694
 695         mtx_unlock(&sc->sc_mutex);
 696
 697         if (process_inbound)
 698                 cuda_send_inbound(sc);
 699
 700         mtx_lock(&sc->sc_mutex);
 701         /* If we have another packet waiting, set it up */
 702         if (!sc->sc_waiting && sc->sc_state == CUDA_IDLE)
 703                 cuda_send_outbound(sc);
 704
 705         mtx_unlock(&sc->sc_mutex);
 706
 707 }
 708
 709 static u_int
 710 cuda_adb_send(device_t dev, u_char command_byte, int len, u_char *data,
 711     u_char poll)
 712 {
 713         struct cuda_softc *sc = device_get_softc(dev);
 714         uint8_t packet[16];
 715         int i;
 716
 717         /* construct an ADB command packet and send it */
 718         packet[0] = CUDA_ADB;
 719         packet[1] = command_byte;
 720         for (i = 0; i < len; i++)
 721                 packet[i + 2] = data[i];
 722
 723         cuda_send(sc, poll, len + 2, packet);
 724
 725         return (0);
 726 }
 727
 728 static u_int
 729 cuda_adb_autopoll(device_t dev, uint16_t mask) {
 730         struct cuda_softc *sc = device_get_softc(dev);
 731
 732         uint8_t cmd[] = {CUDA_PSEUDO, CMD_AUTOPOLL, mask != 0};
 733
 734         mtx_lock(&sc->sc_mutex);
 735
 736         if (cmd[2] == sc->sc_autopoll) {
 737                 mtx_unlock(&sc->sc_mutex);
 738                 return (0);
 739         }
 740
 741         sc->sc_autopoll = -1;
 742         cuda_send(sc, 1, 3, cmd);
 743
 744         mtx_unlock(&sc->sc_mutex);
 745
 746         return (0);
 747 }
 748
 749 static void
 750 cuda_shutdown(void *xsc, int howto)
 751 {
 752         struct cuda_softc *sc = xsc;
 753         uint8_t cmd[] = {CUDA_PSEUDO, 0};
 754
 755         cmd[1] = (howto & RB_HALT) ? CMD_POWEROFF : CMD_RESET;
 756         cuda_poll(sc->sc_dev);
 757         cuda_send(sc, 1, 2, cmd);
 758
 759         while (1)
 760                 cuda_poll(sc->sc_dev);
 761 }
 762
 763 #define DIFF19041970    2082844800
 764
 765 static int
 766 cuda_gettime(device_t dev, struct timespec *ts)
 767 {
 768         struct cuda_softc *sc = device_get_softc(dev);
 769         uint8_t cmd[] = {CUDA_PSEUDO, CMD_READ_RTC};
 770
 771         mtx_lock(&sc->sc_mutex);
 772         sc->sc_rtc = -1;
 773         cuda_send(sc, 1, 2, cmd);
 774         if (sc->sc_rtc == -1)
 775                 mtx_sleep(&sc->sc_rtc, &sc->sc_mutex, 0, "rtc", 100);
 776
 777         ts->tv_sec = sc->sc_rtc - DIFF19041970;
 778         ts->tv_nsec = 0;
 779         mtx_unlock(&sc->sc_mutex);
 780
 781         return (0);
 782 }
 783
 784 static int
 785 cuda_settime(device_t dev, struct timespec *ts)
 786 {
 787         struct cuda_softc *sc = device_get_softc(dev);
 788         uint8_t cmd[] = {CUDA_PSEUDO, CMD_WRITE_RTC, 0, 0, 0, 0};
 789         uint32_t sec;
 790
 791         sec = ts->tv_sec + DIFF19041970;
 792         memcpy(&cmd[2], &sec, sizeof(sec));
 793
 794         mtx_lock(&sc->sc_mutex);
 795         cuda_send(sc, 0, 6, cmd);
 796         mtx_unlock(&sc->sc_mutex);
 797
 798         return (0);
 799 }