2 * SPDX-License-Identifier: BSD-3-Clause
4 * Copyright (c) 2006 Michael Lorenz
5 * Copyright 2008 by Nathan Whitehorn
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. The name of the author may not be used to endorse or promote products
17 * derived from this software without specific prior written permission.
19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
20 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
21 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
22 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
23 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
24 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
26 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
27 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
33 #include <sys/cdefs.h>
34 __FBSDID("$FreeBSD$");
36 #include <sys/param.h>
37 #include <sys/systm.h>
38 #include <sys/module.h>
41 #include <sys/kernel.h>
42 #include <sys/clock.h>
43 #include <sys/reboot.h>
45 #include <dev/ofw/ofw_bus.h>
46 #include <dev/ofw/openfirm.h>
48 #include <machine/bus.h>
49 #include <machine/intr_machdep.h>
50 #include <machine/md_var.h>
51 #include <machine/pio.h>
52 #include <machine/resource.h>
59 #include <dev/adb/adb.h>
68 static int cuda_probe(device_t);
69 static int cuda_attach(device_t);
70 static int cuda_detach(device_t);
72 static u_int cuda_adb_send(device_t dev, u_char command_byte, int len,
73 u_char *data, u_char poll);
74 static u_int cuda_adb_autopoll(device_t dev, uint16_t mask);
75 static u_int cuda_poll(device_t dev);
76 static void cuda_send_inbound(struct cuda_softc *sc);
77 static void cuda_send_outbound(struct cuda_softc *sc);
78 static void cuda_shutdown(void *xsc, int howto);
83 static int cuda_gettime(device_t dev, struct timespec *ts);
84 static int cuda_settime(device_t dev, struct timespec *ts);
86 static device_method_t cuda_methods[] = {
87 /* Device interface */
88 DEVMETHOD(device_probe, cuda_probe),
89 DEVMETHOD(device_attach, cuda_attach),
90 DEVMETHOD(device_detach, cuda_detach),
91 DEVMETHOD(device_shutdown, bus_generic_shutdown),
92 DEVMETHOD(device_suspend, bus_generic_suspend),
93 DEVMETHOD(device_resume, bus_generic_resume),
95 /* ADB bus interface */
96 DEVMETHOD(adb_hb_send_raw_packet, cuda_adb_send),
97 DEVMETHOD(adb_hb_controller_poll, cuda_poll),
98 DEVMETHOD(adb_hb_set_autopoll_mask, cuda_adb_autopoll),
100 /* Clock interface */
101 DEVMETHOD(clock_gettime, cuda_gettime),
102 DEVMETHOD(clock_settime, cuda_settime),
107 static driver_t cuda_driver = {
110 sizeof(struct cuda_softc),
113 static devclass_t cuda_devclass;
115 DRIVER_MODULE(cuda, macio, cuda_driver, cuda_devclass, 0, 0);
116 DRIVER_MODULE(adb, cuda, adb_driver, adb_devclass, 0, 0);
118 static void cuda_intr(void *arg);
119 static uint8_t cuda_read_reg(struct cuda_softc *sc, u_int offset);
120 static void cuda_write_reg(struct cuda_softc *sc, u_int offset, uint8_t value);
121 static void cuda_idle(struct cuda_softc *);
122 static void cuda_tip(struct cuda_softc *);
123 static void cuda_clear_tip(struct cuda_softc *);
124 static void cuda_in(struct cuda_softc *);
125 static void cuda_out(struct cuda_softc *);
126 static void cuda_toggle_ack(struct cuda_softc *);
127 static void cuda_ack_off(struct cuda_softc *);
128 static int cuda_intr_state(struct cuda_softc *);
131 cuda_probe(device_t dev)
133 const char *type = ofw_bus_get_type(dev);
135 if (strcmp(type, "via-cuda") != 0)
138 device_set_desc(dev, CUDA_DEVSTR);
143 cuda_attach(device_t dev)
145 struct cuda_softc *sc;
149 phandle_t node,child;
151 sc = device_get_softc(dev);
155 sc->sc_memr = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
156 &sc->sc_memrid, RF_ACTIVE);
158 if (sc->sc_memr == NULL) {
159 device_printf(dev, "Could not alloc mem resource!\n");
164 sc->sc_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->sc_irqrid,
166 if (sc->sc_irq == NULL) {
167 device_printf(dev, "could not allocate interrupt\n");
171 if (bus_setup_intr(dev, sc->sc_irq, INTR_TYPE_MISC | INTR_MPSAFE
172 | INTR_ENTROPY, NULL, cuda_intr, dev, &sc->sc_ih) != 0) {
173 device_printf(dev, "could not setup interrupt\n");
174 bus_release_resource(dev, SYS_RES_IRQ, sc->sc_irqrid,
179 mtx_init(&sc->sc_mutex,"cuda",NULL,MTX_DEF | MTX_RECURSE);
185 sc->sc_state = CUDA_NOTREADY;
189 STAILQ_INIT(&sc->sc_inq);
190 STAILQ_INIT(&sc->sc_outq);
191 STAILQ_INIT(&sc->sc_freeq);
193 for (i = 0; i < CUDA_MAXPACKETS; i++)
194 STAILQ_INSERT_TAIL(&sc->sc_freeq, &sc->sc_pkts[i], pkt_q);
198 reg = cuda_read_reg(sc, vDirB);
199 reg |= 0x30; /* register B bits 4 and 5: outputs */
200 cuda_write_reg(sc, vDirB, reg);
202 reg = cuda_read_reg(sc, vDirB);
203 reg &= 0xf7; /* register B bit 3: input */
204 cuda_write_reg(sc, vDirB, reg);
206 reg = cuda_read_reg(sc, vACR);
207 reg &= ~vSR_OUT; /* make sure SR is set to IN */
208 cuda_write_reg(sc, vACR, reg);
210 cuda_write_reg(sc, vACR, (cuda_read_reg(sc, vACR) | 0x0c) & ~0x10);
212 sc->sc_state = CUDA_IDLE; /* used by all types of hardware */
214 cuda_write_reg(sc, vIER, 0x84); /* make sure VIA interrupts are on */
216 cuda_idle(sc); /* reset ADB */
220 i = cuda_read_reg(sc, vSR); /* clear interrupt */
221 cuda_write_reg(sc, vIER, 0x04); /* no interrupts while clearing */
222 cuda_idle(sc); /* reset state to idle */
224 cuda_tip(sc); /* signal start of frame */
230 cuda_idle(sc); /* back to idle state */
231 i = cuda_read_reg(sc, vSR); /* clear interrupt */
232 cuda_write_reg(sc, vIER, 0x84); /* ints ok now */
234 /* Initialize child buses (ADB) */
235 node = ofw_bus_get_node(dev);
237 for (child = OF_child(node); child != 0; child = OF_peer(child)) {
240 memset(name, 0, sizeof(name));
241 OF_getprop(child, "name", name, sizeof(name));
244 device_printf(dev, "CUDA child <%s>\n",name);
246 if (strncmp(name, "adb", 4) == 0) {
247 sc->adb_bus = device_add_child(dev,"adb",-1);
251 clock_register(dev, 1000);
252 EVENTHANDLER_REGISTER(shutdown_final, cuda_shutdown, sc,
255 return (bus_generic_attach(dev));
258 static int cuda_detach(device_t dev) {
259 struct cuda_softc *sc;
261 sc = device_get_softc(dev);
263 bus_teardown_intr(dev, sc->sc_irq, sc->sc_ih);
264 bus_release_resource(dev, SYS_RES_IRQ, sc->sc_irqrid, sc->sc_irq);
265 bus_release_resource(dev, SYS_RES_MEMORY, sc->sc_memrid, sc->sc_memr);
266 mtx_destroy(&sc->sc_mutex);
268 return (bus_generic_detach(dev));
272 cuda_read_reg(struct cuda_softc *sc, u_int offset) {
273 return (bus_read_1(sc->sc_memr, offset));
277 cuda_write_reg(struct cuda_softc *sc, u_int offset, uint8_t value) {
278 bus_write_1(sc->sc_memr, offset, value);
282 cuda_idle(struct cuda_softc *sc)
286 reg = cuda_read_reg(sc, vBufB);
287 reg |= (vPB4 | vPB5);
288 cuda_write_reg(sc, vBufB, reg);
292 cuda_tip(struct cuda_softc *sc)
296 reg = cuda_read_reg(sc, vBufB);
298 cuda_write_reg(sc, vBufB, reg);
302 cuda_clear_tip(struct cuda_softc *sc)
306 reg = cuda_read_reg(sc, vBufB);
308 cuda_write_reg(sc, vBufB, reg);
312 cuda_in(struct cuda_softc *sc)
316 reg = cuda_read_reg(sc, vACR);
318 cuda_write_reg(sc, vACR, reg);
322 cuda_out(struct cuda_softc *sc)
326 reg = cuda_read_reg(sc, vACR);
328 cuda_write_reg(sc, vACR, reg);
332 cuda_toggle_ack(struct cuda_softc *sc)
336 reg = cuda_read_reg(sc, vBufB);
338 cuda_write_reg(sc, vBufB, reg);
342 cuda_ack_off(struct cuda_softc *sc)
346 reg = cuda_read_reg(sc, vBufB);
348 cuda_write_reg(sc, vBufB, reg);
352 cuda_intr_state(struct cuda_softc *sc)
354 return ((cuda_read_reg(sc, vBufB) & vPB3) == 0);
358 cuda_send(void *cookie, int poll, int length, uint8_t *msg)
360 struct cuda_softc *sc = cookie;
361 device_t dev = sc->sc_dev;
362 struct cuda_packet *pkt;
364 if (sc->sc_state == CUDA_NOTREADY)
367 mtx_lock(&sc->sc_mutex);
369 pkt = STAILQ_FIRST(&sc->sc_freeq);
371 mtx_unlock(&sc->sc_mutex);
375 pkt->len = length - 1;
377 memcpy(pkt->data, &msg[1], pkt->len);
379 STAILQ_REMOVE_HEAD(&sc->sc_freeq, pkt_q);
380 STAILQ_INSERT_TAIL(&sc->sc_outq, pkt, pkt_q);
383 * If we already are sending a packet, we should bail now that this
384 * one has been added to the queue.
387 if (sc->sc_waiting) {
388 mtx_unlock(&sc->sc_mutex);
392 cuda_send_outbound(sc);
393 mtx_unlock(&sc->sc_mutex);
395 if (sc->sc_polling || poll || cold)
402 cuda_send_outbound(struct cuda_softc *sc)
404 struct cuda_packet *pkt;
406 mtx_assert(&sc->sc_mutex, MA_OWNED);
408 pkt = STAILQ_FIRST(&sc->sc_outq);
412 sc->sc_out_length = pkt->len + 1;
413 memcpy(sc->sc_out, &pkt->type, pkt->len + 1);
416 STAILQ_REMOVE_HEAD(&sc->sc_outq, pkt_q);
417 STAILQ_INSERT_TAIL(&sc->sc_freeq, pkt, pkt_q);
421 cuda_poll(sc->sc_dev);
425 if (sc->sc_state == CUDA_IDLE && !cuda_intr_state(sc)) {
426 sc->sc_state = CUDA_OUT;
428 cuda_write_reg(sc, vSR, sc->sc_out[0]);
435 cuda_send_inbound(struct cuda_softc *sc)
438 struct cuda_packet *pkt;
442 mtx_lock(&sc->sc_mutex);
444 while ((pkt = STAILQ_FIRST(&sc->sc_inq)) != NULL) {
445 STAILQ_REMOVE_HEAD(&sc->sc_inq, pkt_q);
447 mtx_unlock(&sc->sc_mutex);
449 /* check if we have a handler for this message */
453 adb_receive_raw_packet(sc->adb_bus,
454 pkt->data[0],pkt->data[1],
455 pkt->len - 2,&pkt->data[2]);
457 adb_receive_raw_packet(sc->adb_bus,
458 pkt->data[0],pkt->data[1],0,NULL);
462 mtx_lock(&sc->sc_mutex);
463 switch (pkt->data[1]) {
468 memcpy(&sc->sc_rtc, &pkt->data[2],
475 mtx_unlock(&sc->sc_mutex);
479 * CUDA will throw errors if we miss a race between
480 * sending and receiving packets. This is already
481 * handled when we abort packet output to handle
482 * this packet in cuda_intr(). Thus, we ignore
487 device_printf(dev,"unknown CUDA command %d\n",
492 mtx_lock(&sc->sc_mutex);
494 STAILQ_INSERT_TAIL(&sc->sc_freeq, pkt, pkt_q);
497 mtx_unlock(&sc->sc_mutex);
501 cuda_poll(device_t dev)
503 struct cuda_softc *sc = device_get_softc(dev);
505 if (sc->sc_state == CUDA_IDLE && !cuda_intr_state(sc) &&
517 struct cuda_softc *sc;
519 int i, ending, restart_send, process_inbound;
523 sc = device_get_softc(dev);
525 mtx_lock(&sc->sc_mutex);
529 reg = cuda_read_reg(sc, vIFR);
530 if ((reg & vSR_INT) != vSR_INT) {
531 mtx_unlock(&sc->sc_mutex);
535 cuda_write_reg(sc, vIFR, 0x7f); /* Clear interrupt */
538 switch (sc->sc_state) {
541 * This is an unexpected packet, so grab the first (dummy)
542 * byte, set up the proper vars, and tell the chip we are
543 * starting to receive the packet by setting the TIP bit.
545 sc->sc_in[1] = cuda_read_reg(sc, vSR);
547 if (cuda_intr_state(sc) == 0) {
548 /* must have been a fake start */
550 if (sc->sc_waiting) {
553 sc->sc_state = CUDA_OUT;
556 cuda_write_reg(sc, vSR, sc->sc_out[1]);
567 sc->sc_state = CUDA_IN;
571 sc->sc_in[sc->sc_received] = cuda_read_reg(sc, vSR);
574 if (sc->sc_received > 255) {
575 /* bitch only once */
576 if (sc->sc_received == 256) {
577 device_printf(dev,"input overflow\n");
583 /* intr off means this is the last byte (end of frame) */
584 if (cuda_intr_state(sc) == 0) {
590 if (ending == 1) { /* end of message? */
591 struct cuda_packet *pkt;
593 /* reset vars and signal the end of this frame */
596 /* Queue up the packet */
597 pkt = STAILQ_FIRST(&sc->sc_freeq);
599 /* If we have a free packet, process it */
601 pkt->len = sc->sc_received - 2;
602 pkt->type = sc->sc_in[1];
603 memcpy(pkt->data, &sc->sc_in[2], pkt->len);
605 STAILQ_REMOVE_HEAD(&sc->sc_freeq, pkt_q);
606 STAILQ_INSERT_TAIL(&sc->sc_inq, pkt, pkt_q);
611 sc->sc_state = CUDA_IDLE;
615 * If there is something waiting to be sent out,
616 * set everything up and send the first byte.
618 if (sc->sc_waiting == 1) {
619 DELAY(1500); /* required */
621 sc->sc_state = CUDA_OUT;
624 * If the interrupt is on, we were too slow
625 * and the chip has already started to send
626 * something to us, so back out of the write
627 * and start a read cycle.
629 if (cuda_intr_state(sc)) {
633 sc->sc_state = CUDA_IDLE;
640 * If we got here, it's ok to start sending
641 * so load the first byte and tell the chip
645 cuda_write_reg(sc, vSR,
646 sc->sc_out[sc->sc_sent]);
654 i = cuda_read_reg(sc, vSR); /* reset SR-intr in IFR */
657 if (cuda_intr_state(sc)) { /* ADB intr low during write */
658 cuda_in(sc); /* make sure SR is set to IN */
660 sc->sc_sent = 0; /* must start all over */
661 sc->sc_state = CUDA_IDLE; /* new state */
663 sc->sc_waiting = 1; /* must retry when done with
666 goto switch_start; /* process next state right
670 if (sc->sc_out_length == sc->sc_sent) { /* check for done */
671 sc->sc_waiting = 0; /* done writing */
672 sc->sc_state = CUDA_IDLE; /* signal bus is idle */
677 cuda_write_reg(sc, vSR, sc->sc_out[sc->sc_sent]);
678 cuda_toggle_ack(sc); /* signal byte ready to
690 mtx_unlock(&sc->sc_mutex);
693 cuda_send_inbound(sc);
695 mtx_lock(&sc->sc_mutex);
696 /* If we have another packet waiting, set it up */
697 if (!sc->sc_waiting && sc->sc_state == CUDA_IDLE)
698 cuda_send_outbound(sc);
700 mtx_unlock(&sc->sc_mutex);
705 cuda_adb_send(device_t dev, u_char command_byte, int len, u_char *data,
708 struct cuda_softc *sc = device_get_softc(dev);
712 /* construct an ADB command packet and send it */
713 packet[0] = CUDA_ADB;
714 packet[1] = command_byte;
715 for (i = 0; i < len; i++)
716 packet[i + 2] = data[i];
718 cuda_send(sc, poll, len + 2, packet);
724 cuda_adb_autopoll(device_t dev, uint16_t mask) {
725 struct cuda_softc *sc = device_get_softc(dev);
727 uint8_t cmd[] = {CUDA_PSEUDO, CMD_AUTOPOLL, mask != 0};
729 mtx_lock(&sc->sc_mutex);
731 if (cmd[2] == sc->sc_autopoll) {
732 mtx_unlock(&sc->sc_mutex);
736 sc->sc_autopoll = -1;
737 cuda_send(sc, 1, 3, cmd);
739 mtx_unlock(&sc->sc_mutex);
745 cuda_shutdown(void *xsc, int howto)
747 struct cuda_softc *sc = xsc;
748 uint8_t cmd[] = {CUDA_PSEUDO, 0};
750 cmd[1] = (howto & RB_HALT) ? CMD_POWEROFF : CMD_RESET;
751 cuda_poll(sc->sc_dev);
752 cuda_send(sc, 1, 2, cmd);
755 cuda_poll(sc->sc_dev);
758 #define DIFF19041970 2082844800
761 cuda_gettime(device_t dev, struct timespec *ts)
763 struct cuda_softc *sc = device_get_softc(dev);
764 uint8_t cmd[] = {CUDA_PSEUDO, CMD_READ_RTC};
766 mtx_lock(&sc->sc_mutex);
768 cuda_send(sc, 1, 2, cmd);
769 if (sc->sc_rtc == -1)
770 mtx_sleep(&sc->sc_rtc, &sc->sc_mutex, 0, "rtc", 100);
772 ts->tv_sec = sc->sc_rtc - DIFF19041970;
774 mtx_unlock(&sc->sc_mutex);
780 cuda_settime(device_t dev, struct timespec *ts)
782 struct cuda_softc *sc = device_get_softc(dev);
783 uint8_t cmd[] = {CUDA_PSEUDO, CMD_WRITE_RTC, 0, 0, 0, 0};
786 sec = ts->tv_sec + DIFF19041970;
787 memcpy(&cmd[2], &sec, sizeof(sec));
789 mtx_lock(&sc->sc_mutex);
790 cuda_send(sc, 0, 6, cmd);
791 mtx_unlock(&sc->sc_mutex);