2 * Copyright (c) 2008 Nathan Whitehorn
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
30 #include <sys/param.h>
31 #include <sys/systm.h>
32 #include <sys/kernel.h>
33 #include <sys/malloc.h>
34 #include <sys/module.h>
35 #include <sys/endian.h>
37 #include <machine/bus.h>
38 #include <machine/dbdma.h>
43 static MALLOC_DEFINE(M_DBDMA, "dbdma", "DBDMA Command List");
45 static uint32_t dbdma_read_reg(dbdma_channel_t *, u_int);
46 static void dbdma_write_reg(dbdma_channel_t *, u_int, uint32_t);
47 static void dbdma_phys_callback(void *, bus_dma_segment_t *, int, int);
50 dbdma_phys_callback(void *chan, bus_dma_segment_t *segs, int nsegs, int error)
52 dbdma_channel_t *channel = (dbdma_channel_t *)(chan);
54 channel->sc_slots_pa = segs[0].ds_addr;
55 dbdma_write_reg(channel, CHAN_CMDPTR, channel->sc_slots_pa);
59 dbdma_allocate_channel(struct resource *dbdma_regs, u_int offset,
60 bus_dma_tag_t parent_dma, int slots, dbdma_channel_t **chan)
63 dbdma_channel_t *channel;
65 channel = *chan = malloc(sizeof(struct dbdma_channel), M_DBDMA,
68 channel->sc_regs = dbdma_regs;
69 channel->sc_off = offset;
72 channel->sc_slots_pa = 0;
74 error = bus_dma_tag_create(parent_dma, 16, 0, BUS_SPACE_MAXADDR_32BIT,
75 BUS_SPACE_MAXADDR, NULL, NULL, PAGE_SIZE, 1, PAGE_SIZE, 0, NULL,
76 NULL, &(channel->sc_dmatag));
78 error = bus_dmamem_alloc(channel->sc_dmatag,
79 (void **)&channel->sc_slots, BUS_DMA_WAITOK | BUS_DMA_ZERO,
82 error = bus_dmamap_load(channel->sc_dmatag, channel->sc_dmamap,
83 channel->sc_slots, PAGE_SIZE, dbdma_phys_callback, channel, 0);
85 dbdma_write_reg(channel, CHAN_CMDPTR_HI, 0);
87 channel->sc_nslots = slots;
93 dbdma_resize_channel(dbdma_channel_t *chan, int newslots)
96 if (newslots > (PAGE_SIZE / sizeof(struct dbdma_command)))
99 chan->sc_nslots = newslots;
104 dbdma_free_channel(dbdma_channel_t *chan)
109 bus_dmamem_free(chan->sc_dmatag, chan->sc_slots, chan->sc_dmamap);
110 bus_dma_tag_destroy(chan->sc_dmatag);
118 dbdma_get_cmd_status(dbdma_channel_t *chan, int slot)
121 bus_dmamap_sync(chan->sc_dmatag, chan->sc_dmamap, BUS_DMASYNC_POSTREAD);
124 * I really did mean to swap resCount and xferStatus here, to
125 * account for the quad-word little endian fields.
127 return (le16toh(chan->sc_slots[slot].resCount));
131 dbdma_clear_cmd_status(dbdma_channel_t *chan, int slot)
133 /* See endian note above */
134 chan->sc_slots[slot].resCount = 0;
138 dbdma_get_residuals(dbdma_channel_t *chan, int slot)
141 bus_dmamap_sync(chan->sc_dmatag, chan->sc_dmamap, BUS_DMASYNC_POSTREAD);
143 return (le16toh(chan->sc_slots[slot].xferStatus));
147 dbdma_reset(dbdma_channel_t *chan)
151 dbdma_set_current_cmd(chan, 0);
156 dbdma_run(dbdma_channel_t *chan)
158 uint32_t control_reg;
160 control_reg = DBDMA_STATUS_RUN | DBDMA_STATUS_PAUSE |
161 DBDMA_STATUS_WAKE | DBDMA_STATUS_DEAD;
162 control_reg <<= DBDMA_REG_MASK_SHIFT;
164 control_reg |= DBDMA_STATUS_RUN;
165 dbdma_write_reg(chan, CHAN_CONTROL_REG, control_reg);
169 dbdma_pause(dbdma_channel_t *chan)
171 uint32_t control_reg;
173 control_reg = DBDMA_STATUS_PAUSE;
174 control_reg <<= DBDMA_REG_MASK_SHIFT;
176 control_reg |= DBDMA_STATUS_PAUSE;
177 dbdma_write_reg(chan, CHAN_CONTROL_REG, control_reg);
181 dbdma_wake(dbdma_channel_t *chan)
183 uint32_t control_reg;
185 control_reg = DBDMA_STATUS_WAKE | DBDMA_STATUS_PAUSE |
186 DBDMA_STATUS_RUN | DBDMA_STATUS_DEAD;
187 control_reg <<= DBDMA_REG_MASK_SHIFT;
189 control_reg |= DBDMA_STATUS_WAKE | DBDMA_STATUS_RUN;
190 dbdma_write_reg(chan, CHAN_CONTROL_REG, control_reg);
194 dbdma_stop(dbdma_channel_t *chan)
196 uint32_t control_reg;
198 control_reg = DBDMA_STATUS_RUN;
199 control_reg <<= DBDMA_REG_MASK_SHIFT;
201 dbdma_write_reg(chan, CHAN_CONTROL_REG, control_reg);
203 while (dbdma_read_reg(chan, CHAN_STATUS_REG) & DBDMA_STATUS_ACTIVE)
208 dbdma_set_current_cmd(dbdma_channel_t *chan, int slot)
212 cmd = chan->sc_slots_pa + slot * sizeof(struct dbdma_command);
213 dbdma_write_reg(chan, CHAN_CMDPTR, cmd);
217 dbdma_get_chan_status(dbdma_channel_t *chan)
221 status_reg = dbdma_read_reg(chan, CHAN_STATUS_REG);
222 return (status_reg & 0x0000ffff);
226 dbdma_get_device_status(dbdma_channel_t *chan)
228 return (dbdma_get_chan_status(chan) & 0x00ff);
232 dbdma_set_device_status(dbdma_channel_t *chan, uint8_t mask, uint8_t value)
234 uint32_t control_reg;
237 control_reg <<= DBDMA_REG_MASK_SHIFT;
238 control_reg |= value;
240 dbdma_write_reg(chan, CHAN_CONTROL_REG, control_reg);
244 dbdma_set_interrupt_selector(dbdma_channel_t *chan, uint8_t mask, uint8_t val)
246 uint32_t intr_select;
249 intr_select <<= DBDMA_REG_MASK_SHIFT;
252 dbdma_write_reg(chan, CHAN_INTR_SELECT, intr_select);
256 dbdma_set_branch_selector(dbdma_channel_t *chan, uint8_t mask, uint8_t val)
261 br_select <<= DBDMA_REG_MASK_SHIFT;
264 dbdma_write_reg(chan, CHAN_BRANCH_SELECT, br_select);
268 dbdma_set_wait_selector(dbdma_channel_t *chan, uint8_t mask, uint8_t val)
270 uint32_t wait_select;
273 wait_select <<= DBDMA_REG_MASK_SHIFT;
275 dbdma_write_reg(chan, CHAN_WAIT_SELECT, wait_select);
279 dbdma_insert_command(dbdma_channel_t *chan, int slot, int command, int stream,
280 bus_addr_t data, size_t count, uint8_t interrupt, uint8_t branch,
281 uint8_t wait, uint32_t branch_slot)
283 struct dbdma_command cmd;
288 cmd.intr = interrupt;
292 cmd.reqCount = count;
293 cmd.address = (uint32_t)(data);
294 if (command != DBDMA_STORE_QUAD && command != DBDMA_LOAD_QUAD)
295 cmd.cmdDep = chan->sc_slots_pa +
296 branch_slot * sizeof(struct dbdma_command);
298 cmd.cmdDep = branch_slot;
304 * Move quadwords to little-endian. God only knows why
305 * Apple thought this was a good idea.
307 flip = (uint32_t *)(&cmd);
308 flip[0] = htole32(flip[0]);
309 flip[1] = htole32(flip[1]);
310 flip[2] = htole32(flip[2]);
312 chan->sc_slots[slot] = cmd;
316 dbdma_insert_stop(dbdma_channel_t *chan, int slot)
319 dbdma_insert_command(chan, slot, DBDMA_STOP, 0, 0, 0, DBDMA_NEVER,
320 DBDMA_NEVER, DBDMA_NEVER, 0);
324 dbdma_insert_nop(dbdma_channel_t *chan, int slot)
327 dbdma_insert_command(chan, slot, DBDMA_NOP, 0, 0, 0, DBDMA_NEVER,
328 DBDMA_NEVER, DBDMA_NEVER, 0);
332 dbdma_insert_branch(dbdma_channel_t *chan, int slot, int to_slot)
335 dbdma_insert_command(chan, slot, DBDMA_NOP, 0, 0, 0, DBDMA_NEVER,
336 DBDMA_ALWAYS, DBDMA_NEVER, to_slot);
340 dbdma_sync_commands(dbdma_channel_t *chan, bus_dmasync_op_t op)
343 bus_dmamap_sync(chan->sc_dmatag, chan->sc_dmamap, op);
347 dbdma_read_reg(dbdma_channel_t *chan, u_int offset)
350 return (bus_read_4(chan->sc_regs, chan->sc_off + offset));
354 dbdma_write_reg(dbdma_channel_t *chan, u_int offset, uint32_t val)
357 bus_write_4(chan->sc_regs, chan->sc_off + offset, val);