2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 2008 Nathan Whitehorn
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 #include <sys/cdefs.h>
30 __FBSDID("$FreeBSD$");
32 #include <sys/param.h>
33 #include <sys/systm.h>
34 #include <sys/kernel.h>
35 #include <sys/malloc.h>
36 #include <sys/module.h>
37 #include <sys/endian.h>
39 #include <machine/bus.h>
40 #include <machine/dbdma.h>
45 static MALLOC_DEFINE(M_DBDMA, "dbdma", "DBDMA Command List");
47 static uint32_t dbdma_read_reg(dbdma_channel_t *, u_int);
48 static void dbdma_write_reg(dbdma_channel_t *, u_int, uint32_t);
49 static void dbdma_phys_callback(void *, bus_dma_segment_t *, int, int);
52 dbdma_phys_callback(void *chan, bus_dma_segment_t *segs, int nsegs, int error)
54 dbdma_channel_t *channel = (dbdma_channel_t *)(chan);
56 channel->sc_slots_pa = segs[0].ds_addr;
57 dbdma_write_reg(channel, CHAN_CMDPTR, channel->sc_slots_pa);
61 dbdma_allocate_channel(struct resource *dbdma_regs, u_int offset,
62 bus_dma_tag_t parent_dma, int slots, dbdma_channel_t **chan)
65 dbdma_channel_t *channel;
67 channel = *chan = malloc(sizeof(struct dbdma_channel), M_DBDMA,
70 channel->sc_regs = dbdma_regs;
71 channel->sc_off = offset;
74 channel->sc_slots_pa = 0;
76 error = bus_dma_tag_create(parent_dma, 16, 0, BUS_SPACE_MAXADDR_32BIT,
77 BUS_SPACE_MAXADDR, NULL, NULL, PAGE_SIZE, 1, PAGE_SIZE, 0, NULL,
78 NULL, &(channel->sc_dmatag));
80 error = bus_dmamem_alloc(channel->sc_dmatag,
81 (void **)&channel->sc_slots, BUS_DMA_WAITOK | BUS_DMA_ZERO,
84 error = bus_dmamap_load(channel->sc_dmatag, channel->sc_dmamap,
85 channel->sc_slots, PAGE_SIZE, dbdma_phys_callback, channel, 0);
87 dbdma_write_reg(channel, CHAN_CMDPTR_HI, 0);
89 channel->sc_nslots = slots;
95 dbdma_resize_channel(dbdma_channel_t *chan, int newslots)
98 if (newslots > (PAGE_SIZE / sizeof(struct dbdma_command)))
101 chan->sc_nslots = newslots;
106 dbdma_free_channel(dbdma_channel_t *chan)
111 bus_dmamem_free(chan->sc_dmatag, chan->sc_slots, chan->sc_dmamap);
112 bus_dma_tag_destroy(chan->sc_dmatag);
120 dbdma_get_cmd_status(dbdma_channel_t *chan, int slot)
123 bus_dmamap_sync(chan->sc_dmatag, chan->sc_dmamap, BUS_DMASYNC_POSTREAD);
126 * I really did mean to swap resCount and xferStatus here, to
127 * account for the quad-word little endian fields.
129 return (le16toh(chan->sc_slots[slot].resCount));
133 dbdma_clear_cmd_status(dbdma_channel_t *chan, int slot)
135 /* See endian note above */
136 chan->sc_slots[slot].resCount = 0;
140 dbdma_get_residuals(dbdma_channel_t *chan, int slot)
143 bus_dmamap_sync(chan->sc_dmatag, chan->sc_dmamap, BUS_DMASYNC_POSTREAD);
145 return (le16toh(chan->sc_slots[slot].xferStatus));
149 dbdma_reset(dbdma_channel_t *chan)
153 dbdma_set_current_cmd(chan, 0);
158 dbdma_run(dbdma_channel_t *chan)
160 uint32_t control_reg;
162 control_reg = DBDMA_STATUS_RUN | DBDMA_STATUS_PAUSE |
163 DBDMA_STATUS_WAKE | DBDMA_STATUS_DEAD;
164 control_reg <<= DBDMA_REG_MASK_SHIFT;
166 control_reg |= DBDMA_STATUS_RUN;
167 dbdma_write_reg(chan, CHAN_CONTROL_REG, control_reg);
171 dbdma_pause(dbdma_channel_t *chan)
173 uint32_t control_reg;
175 control_reg = DBDMA_STATUS_PAUSE;
176 control_reg <<= DBDMA_REG_MASK_SHIFT;
178 control_reg |= DBDMA_STATUS_PAUSE;
179 dbdma_write_reg(chan, CHAN_CONTROL_REG, control_reg);
183 dbdma_wake(dbdma_channel_t *chan)
185 uint32_t control_reg;
187 control_reg = DBDMA_STATUS_WAKE | DBDMA_STATUS_PAUSE |
188 DBDMA_STATUS_RUN | DBDMA_STATUS_DEAD;
189 control_reg <<= DBDMA_REG_MASK_SHIFT;
191 control_reg |= DBDMA_STATUS_WAKE | DBDMA_STATUS_RUN;
192 dbdma_write_reg(chan, CHAN_CONTROL_REG, control_reg);
196 dbdma_stop(dbdma_channel_t *chan)
198 uint32_t control_reg;
200 control_reg = DBDMA_STATUS_RUN;
201 control_reg <<= DBDMA_REG_MASK_SHIFT;
203 dbdma_write_reg(chan, CHAN_CONTROL_REG, control_reg);
205 while (dbdma_read_reg(chan, CHAN_STATUS_REG) & DBDMA_STATUS_ACTIVE)
210 dbdma_set_current_cmd(dbdma_channel_t *chan, int slot)
214 cmd = chan->sc_slots_pa + slot * sizeof(struct dbdma_command);
215 dbdma_write_reg(chan, CHAN_CMDPTR, cmd);
219 dbdma_get_chan_status(dbdma_channel_t *chan)
223 status_reg = dbdma_read_reg(chan, CHAN_STATUS_REG);
224 return (status_reg & 0x0000ffff);
228 dbdma_get_device_status(dbdma_channel_t *chan)
230 return (dbdma_get_chan_status(chan) & 0x00ff);
234 dbdma_set_device_status(dbdma_channel_t *chan, uint8_t mask, uint8_t value)
236 uint32_t control_reg;
239 control_reg <<= DBDMA_REG_MASK_SHIFT;
240 control_reg |= value;
242 dbdma_write_reg(chan, CHAN_CONTROL_REG, control_reg);
246 dbdma_set_interrupt_selector(dbdma_channel_t *chan, uint8_t mask, uint8_t val)
248 uint32_t intr_select;
251 intr_select <<= DBDMA_REG_MASK_SHIFT;
254 dbdma_write_reg(chan, CHAN_INTR_SELECT, intr_select);
258 dbdma_set_branch_selector(dbdma_channel_t *chan, uint8_t mask, uint8_t val)
263 br_select <<= DBDMA_REG_MASK_SHIFT;
266 dbdma_write_reg(chan, CHAN_BRANCH_SELECT, br_select);
270 dbdma_set_wait_selector(dbdma_channel_t *chan, uint8_t mask, uint8_t val)
272 uint32_t wait_select;
275 wait_select <<= DBDMA_REG_MASK_SHIFT;
277 dbdma_write_reg(chan, CHAN_WAIT_SELECT, wait_select);
281 dbdma_insert_command(dbdma_channel_t *chan, int slot, int command, int stream,
282 bus_addr_t data, size_t count, uint8_t interrupt, uint8_t branch,
283 uint8_t wait, uint32_t branch_slot)
285 struct dbdma_command cmd;
290 cmd.intr = interrupt;
294 cmd.reqCount = count;
295 cmd.address = (uint32_t)(data);
296 if (command != DBDMA_STORE_QUAD && command != DBDMA_LOAD_QUAD)
297 cmd.cmdDep = chan->sc_slots_pa +
298 branch_slot * sizeof(struct dbdma_command);
300 cmd.cmdDep = branch_slot;
306 * Move quadwords to little-endian. God only knows why
307 * Apple thought this was a good idea.
309 flip = (uint32_t *)(&cmd);
310 flip[0] = htole32(flip[0]);
311 flip[1] = htole32(flip[1]);
312 flip[2] = htole32(flip[2]);
314 chan->sc_slots[slot] = cmd;
318 dbdma_insert_stop(dbdma_channel_t *chan, int slot)
321 dbdma_insert_command(chan, slot, DBDMA_STOP, 0, 0, 0, DBDMA_NEVER,
322 DBDMA_NEVER, DBDMA_NEVER, 0);
326 dbdma_insert_nop(dbdma_channel_t *chan, int slot)
329 dbdma_insert_command(chan, slot, DBDMA_NOP, 0, 0, 0, DBDMA_NEVER,
330 DBDMA_NEVER, DBDMA_NEVER, 0);
334 dbdma_insert_branch(dbdma_channel_t *chan, int slot, int to_slot)
337 dbdma_insert_command(chan, slot, DBDMA_NOP, 0, 0, 0, DBDMA_NEVER,
338 DBDMA_ALWAYS, DBDMA_NEVER, to_slot);
342 dbdma_sync_commands(dbdma_channel_t *chan, bus_dmasync_op_t op)
345 bus_dmamap_sync(chan->sc_dmatag, chan->sc_dmamap, op);
349 dbdma_save_state(dbdma_channel_t *chan)
352 chan->sc_saved_regs[0] = dbdma_read_reg(chan, CHAN_CMDPTR);
353 chan->sc_saved_regs[1] = dbdma_read_reg(chan, CHAN_CMDPTR_HI);
354 chan->sc_saved_regs[2] = dbdma_read_reg(chan, CHAN_INTR_SELECT);
355 chan->sc_saved_regs[3] = dbdma_read_reg(chan, CHAN_BRANCH_SELECT);
356 chan->sc_saved_regs[4] = dbdma_read_reg(chan, CHAN_WAIT_SELECT);
362 dbdma_restore_state(dbdma_channel_t *chan)
366 dbdma_write_reg(chan, CHAN_CMDPTR, chan->sc_saved_regs[0]);
367 dbdma_write_reg(chan, CHAN_CMDPTR_HI, chan->sc_saved_regs[1]);
368 dbdma_write_reg(chan, CHAN_INTR_SELECT, chan->sc_saved_regs[2]);
369 dbdma_write_reg(chan, CHAN_BRANCH_SELECT, chan->sc_saved_regs[3]);
370 dbdma_write_reg(chan, CHAN_WAIT_SELECT, chan->sc_saved_regs[4]);
374 dbdma_read_reg(dbdma_channel_t *chan, u_int offset)
377 return (bus_read_4(chan->sc_regs, chan->sc_off + offset));
381 dbdma_write_reg(dbdma_channel_t *chan, u_int offset, uint32_t val)
384 bus_write_4(chan->sc_regs, chan->sc_off + offset, val);