2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2008 Nathan Whitehorn
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8 * modification, are permitted provided that the following conditions
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31 #ifndef _POWERPC_POWERMAC_DBDMAVAR_H_
32 #define _POWERPC_POWERMAC_DBDMAVAR_H_
34 struct dbdma_command {
35 uint8_t cmd:4; /* DBDMA command */
38 uint8_t key:3; /* Stream number, or 6 for KEY_SYSTEM */
41 /* Interrupt, branch, and wait flags */
46 uint16_t reqCount; /* Bytes to transfer */
48 uint32_t address; /* 32-bit system physical address */
49 uint32_t cmdDep; /* Branch address or quad word to load/store */
51 uint16_t xferStatus; /* Contents of channel status after completion */
52 uint16_t resCount; /* Number of residual bytes outstanding */
55 struct dbdma_channel {
56 struct resource *sc_regs;
59 struct dbdma_command *sc_slots;
61 bus_addr_t sc_slots_pa;
63 bus_dma_tag_t sc_dmatag;
64 bus_dmamap_t sc_dmamap;
65 uint32_t sc_saved_regs[5];
70 DBDMA registers are found at 0x8000 + n*0x100 in the macio register space,
71 and are laid out as follows within each block:
73 Address: Description: Length (bytes):
74 0x000 Channel Control 4
75 0x004 Channel Status 4
76 0x00C Command Phys Addr 4
77 0x010 Interrupt Select 4
82 #define CHAN_CONTROL_REG 0x00
83 #define CHAN_STATUS_REG 0x04
84 #define CHAN_CMDPTR_HI 0x08
85 #define CHAN_CMDPTR 0x0C
86 #define CHAN_INTR_SELECT 0x10
87 #define CHAN_BRANCH_SELECT 0x14
88 #define CHAN_WAIT_SELECT 0x18
90 /* Channel control is the write channel to channel status, the upper 16 bits
91 are a mask of which bytes to change */
93 #define DBDMA_REG_MASK_SHIFT 16
95 /* Status bits 0-7 are device dependent status bits */
98 The Interrupt/Branch/Wait Select triggers the corresponding condition bits
99 in the event that (select.mask & device dependent status) == select.value
101 They are defined a follows:
108 #endif /* _POWERPC_POWERMAC_DBDMAVAR_H_ */