2 * SPDX-License-Identifier: BSD-3-Clause
4 * Copyright 2003 by Peter Grehan. All rights reserved.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
22 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
23 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
24 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
25 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32 #ifndef _POWERPC_POWERMAC_HROWPICVAR_H_
33 #define _POWERPC_POWERMAC_HROWPICVAR_H_
35 #define HROWPIC_IRQMAX 64
36 #define HROWPIC_IRQ_REGNUM 32 /* irqs per register */
37 #define HROWPIC_IRQ_SHIFT 5 /* high or low irq word */
38 #define HROWPIC_IRQ_MASK ((HROWPIC_IRQMAX-1) >> 1) /* irq bit pos in word */
41 * Register offsets within bank. There are two identical banks,
42 * separated by 16 bytes. Interrupts 0->31 are processed in the
43 * second bank, and 32->63 in the first bank.
45 #define HPIC_STATUS 0x00 /* active interrupt sources */
46 #define HPIC_ENABLE 0x04 /* interrupt asserts ppc EXTINT */
47 #define HPIC_CLEAR 0x08 /* clear int source */
48 #define HPIC_TRIGGER 0x0c /* edge/level int trigger */
50 #define HPIC_PRIMARY 1 /* primary register bank */
51 #define HPIC_SECONDARY 0 /* secondary register bank */
54 * Convert an interrupt into a prim/sec bank number
56 #define HPIC_INT_TO_BANK(x) \
57 (((x) >> HROWPIC_IRQ_SHIFT) ^ 1)
60 * Convert an interrupt into the bit number within a bank register
62 #define HPIC_INT_TO_REGBIT(x) \
63 ((x) & HROWPIC_IRQ_MASK)
65 #define HPIC_1ST_OFFSET 0x10 /* offset to primary reg bank */
67 struct hrowpic_softc {
68 device_t sc_dev; /* macio device */
69 struct resource *sc_rres; /* macio bus resource */
70 bus_space_tag_t sc_bt; /* macio bus tag/handle */
71 bus_space_handle_t sc_bh;
73 uint32_t sc_softreg[2]; /* ENABLE reg copy */
74 u_int sc_vector[HROWPIC_IRQMAX];
77 #endif /* _POWERPC_POWERMAC_HROWPICVAR_H_ */