2 * Copyright (C) 2002 Benno Rice.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY Benno Rice ``AS IS'' AND ANY EXPRESS OR
15 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
16 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
17 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
18 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
19 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
20 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
21 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
22 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
23 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 #include <sys/cdefs.h>
27 __FBSDID("$FreeBSD$");
29 #include <sys/param.h>
30 #include <sys/systm.h>
31 #include <sys/module.h>
34 #include <sys/kernel.h>
37 #include <dev/ofw/openfirm.h>
38 #include <dev/ofw/ofw_pci.h>
39 #include <dev/ofw/ofw_bus.h>
40 #include <dev/ofw/ofw_bus_subr.h>
41 #include <dev/ofw/ofwpci.h>
43 #include <dev/pci/pcivar.h>
44 #include <dev/pci/pcireg.h>
46 #include <machine/bus.h>
47 #include <machine/intr_machdep.h>
48 #include <machine/md_var.h>
49 #include <machine/pio.h>
50 #include <machine/resource.h>
52 #include <powerpc/powermac/uninorthvar.h>
59 #define UNINORTH_DEBUG 0
64 static int uninorth_probe(device_t);
65 static int uninorth_attach(device_t);
70 static u_int32_t uninorth_read_config(device_t, u_int, u_int, u_int,
72 static void uninorth_write_config(device_t, u_int, u_int, u_int,
73 u_int, u_int32_t, int);
78 static int uninorth_enable_config(struct uninorth_softc *, u_int,
84 static device_method_t uninorth_methods[] = {
85 /* Device interface */
86 DEVMETHOD(device_probe, uninorth_probe),
87 DEVMETHOD(device_attach, uninorth_attach),
90 DEVMETHOD(pcib_read_config, uninorth_read_config),
91 DEVMETHOD(pcib_write_config, uninorth_write_config),
96 static devclass_t uninorth_devclass;
98 DEFINE_CLASS_1(pcib, uninorth_driver, uninorth_methods,
99 sizeof(struct uninorth_softc), ofw_pci_driver);
100 DRIVER_MODULE(uninorth, ofwbus, uninorth_driver, uninorth_devclass, 0, 0);
103 uninorth_probe(device_t dev)
105 const char *type, *compatible;
107 type = ofw_bus_get_type(dev);
108 compatible = ofw_bus_get_compat(dev);
110 if (type == NULL || compatible == NULL)
113 if (strcmp(type, "pci") != 0)
116 if (strcmp(compatible, "uni-north") == 0) {
117 device_set_desc(dev, "Apple UniNorth Host-PCI bridge");
119 } else if (strcmp(compatible, "u3-agp") == 0) {
120 device_set_desc(dev, "Apple U3 Host-AGP bridge");
122 } else if (strcmp(compatible, "u4-pcie") == 0) {
123 device_set_desc(dev, "IBM CPC945 PCI Express Root");
131 uninorth_attach(device_t dev)
133 struct uninorth_softc *sc;
134 const char *compatible;
140 node = ofw_bus_get_node(dev);
141 sc = device_get_softc(dev);
143 if (OF_getprop(node, "reg", reg, sizeof(reg)) < 8)
147 compatible = ofw_bus_get_compat(dev);
148 if (strcmp(compatible, "u3-agp") == 0)
150 if (strcmp(compatible, "u4-pcie") == 0)
154 OF_getprop(OF_parent(node), "#address-cells", &acells, sizeof(acells));
162 sc->sc_addr = (vm_offset_t)pmap_mapdev(regbase + 0x800000, PAGE_SIZE);
163 sc->sc_data = (vm_offset_t)pmap_mapdev(regbase + 0xc00000, PAGE_SIZE);
165 return (ofw_pci_attach(dev));
169 uninorth_read_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg,
172 struct uninorth_softc *sc;
175 sc = device_get_softc(dev);
176 caoff = sc->sc_data + (reg & 0x07);
178 if (uninorth_enable_config(sc, bus, slot, func, reg) != 0) {
181 return (in8rb(caoff));
184 return (in16rb(caoff));
187 return (in32rb(caoff));
196 uninorth_write_config(device_t dev, u_int bus, u_int slot, u_int func,
197 u_int reg, u_int32_t val, int width)
199 struct uninorth_softc *sc;
202 sc = device_get_softc(dev);
203 caoff = sc->sc_data + (reg & 0x07);
205 if (uninorth_enable_config(sc, bus, slot, func, reg)) {
221 uninorth_enable_config(struct uninorth_softc *sc, u_int bus, u_int slot,
222 u_int func, u_int reg)
227 if (resource_int_value(device_get_name(sc->pci_sc.sc_dev),
228 device_get_unit(sc->pci_sc.sc_dev), "skipslot", &pass) == 0) {
234 * Issue type 0 configuration space accesses for the root bus.
236 * NOTE: On U4, issue only type 1 accesses. There is a secret
237 * PCI Express <-> PCI Express bridge not present in the device tree,
238 * and we need to route all of our configuration space through it.
240 if (sc->pci_sc.sc_bus == bus && sc->sc_ver < 4) {
242 * No slots less than 11 on the primary bus on U3 and lower
247 cfgval = (1 << slot) | (func << 8) | (reg & 0xfc);
249 cfgval = (bus << 16) | (slot << 11) | (func << 8) |
253 /* Set extended register bits on U4 */
255 cfgval |= (reg >> 8) << 28;
258 out32rb(sc->sc_addr, cfgval);
259 } while (in32rb(sc->sc_addr) != cfgval);