2 * Copyright (C) 2002 Benno Rice.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY Benno Rice ``AS IS'' AND ANY EXPRESS OR
15 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
16 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
17 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
18 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
19 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
20 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
21 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
22 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
23 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 #include <sys/param.h>
29 #include <sys/systm.h>
30 #include <sys/module.h>
33 #include <sys/kernel.h>
35 #include <dev/ofw/openfirm.h>
36 #include <dev/ofw/ofw_pci.h>
37 #include <dev/ofw/ofw_bus.h>
38 #include <dev/ofw/ofw_bus_subr.h>
40 #include <dev/pci/pcivar.h>
41 #include <dev/pci/pcireg.h>
43 #include <machine/bus.h>
44 #include <machine/intr_machdep.h>
45 #include <machine/md_var.h>
46 #include <machine/pio.h>
47 #include <machine/resource.h>
51 #include <powerpc/powermac/uninorthvar.h>
58 #define UNINORTH_DEBUG 0
63 static int uninorth_probe(device_t);
64 static int uninorth_attach(device_t);
69 static int uninorth_read_ivar(device_t, device_t, int,
71 static struct resource * uninorth_alloc_resource(device_t bus,
72 device_t child, int type, int *rid, u_long start,
73 u_long end, u_long count, u_int flags);
74 static int uninorth_activate_resource(device_t bus, device_t child,
75 int type, int rid, struct resource *res);
80 static int uninorth_maxslots(device_t);
81 static u_int32_t uninorth_read_config(device_t, u_int, u_int, u_int,
83 static void uninorth_write_config(device_t, u_int, u_int, u_int,
84 u_int, u_int32_t, int);
85 static int uninorth_route_interrupt(device_t, device_t, int);
91 static phandle_t uninorth_get_node(device_t bus, device_t dev);
96 static int uninorth_enable_config(struct uninorth_softc *, u_int,
102 static device_method_t uninorth_methods[] = {
103 /* Device interface */
104 DEVMETHOD(device_probe, uninorth_probe),
105 DEVMETHOD(device_attach, uninorth_attach),
108 DEVMETHOD(bus_print_child, bus_generic_print_child),
109 DEVMETHOD(bus_read_ivar, uninorth_read_ivar),
110 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr),
111 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr),
112 DEVMETHOD(bus_alloc_resource, uninorth_alloc_resource),
113 DEVMETHOD(bus_activate_resource, uninorth_activate_resource),
116 DEVMETHOD(pcib_maxslots, uninorth_maxslots),
117 DEVMETHOD(pcib_read_config, uninorth_read_config),
118 DEVMETHOD(pcib_write_config, uninorth_write_config),
119 DEVMETHOD(pcib_route_interrupt, uninorth_route_interrupt),
121 /* ofw_bus interface */
122 DEVMETHOD(ofw_bus_get_node, uninorth_get_node),
127 static driver_t uninorth_driver = {
130 sizeof(struct uninorth_softc)
133 static devclass_t uninorth_devclass;
135 DRIVER_MODULE(uninorth, nexus, uninorth_driver, uninorth_devclass, 0, 0);
138 uninorth_probe(device_t dev)
140 const char *type, *compatible;
142 type = ofw_bus_get_type(dev);
143 compatible = ofw_bus_get_compat(dev);
145 if (type == NULL || compatible == NULL)
148 if (strcmp(type, "pci") != 0)
151 if (strcmp(compatible, "uni-north") == 0) {
152 device_set_desc(dev, "Apple UniNorth Host-PCI bridge");
154 } else if (strcmp(compatible, "u3-agp") == 0) {
155 device_set_desc(dev, "Apple U3 Host-AGP bridge");
157 } else if (strcmp(compatible, "u4-pcie") == 0) {
158 device_set_desc(dev, "IBM CPC945 PCI Express Root");
166 uninorth_attach(device_t dev)
168 struct uninorth_softc *sc;
169 const char *compatible;
171 u_int32_t reg[3], busrange[2];
172 struct uninorth_range *rp, *io, *mem[2];
175 node = ofw_bus_get_node(dev);
176 sc = device_get_softc(dev);
178 if (OF_getprop(node, "reg", reg, sizeof(reg)) < 8)
181 if (OF_getprop(node, "bus-range", busrange, sizeof(busrange)) != 8)
185 compatible = ofw_bus_get_compat(dev);
186 if (strcmp(compatible, "u3-agp") == 0)
188 if (strcmp(compatible, "u4-pcie") == 0)
193 if (sc->sc_ver >= 3) {
194 sc->sc_addr = (vm_offset_t)pmap_mapdev(reg[1] + 0x800000, PAGE_SIZE);
195 sc->sc_data = (vm_offset_t)pmap_mapdev(reg[1] + 0xc00000, PAGE_SIZE);
197 sc->sc_addr = (vm_offset_t)pmap_mapdev(reg[0] + 0x800000, PAGE_SIZE);
198 sc->sc_data = (vm_offset_t)pmap_mapdev(reg[0] + 0xc00000, PAGE_SIZE);
200 sc->sc_bus = busrange[0];
202 bzero(sc->sc_range, sizeof(sc->sc_range));
203 if (sc->sc_ver >= 3) {
205 * On Apple U3 systems, we have an otherwise standard
206 * Uninorth controller driving AGP. The one difference
207 * is that it uses a new PCI ranges format, so do the
211 struct uninorth_range64 range64[6];
212 bzero(range64, sizeof(range64));
214 sc->sc_nrange = OF_getprop(node, "ranges", range64,
216 for (i = 0; range64[i].pci_hi != 0; i++) {
217 sc->sc_range[i].pci_hi = range64[i].pci_hi;
218 sc->sc_range[i].pci_mid = range64[i].pci_mid;
219 sc->sc_range[i].pci_lo = range64[i].pci_lo;
220 sc->sc_range[i].host = range64[i].host_lo;
221 sc->sc_range[i].size_hi = range64[i].size_hi;
222 sc->sc_range[i].size_lo = range64[i].size_lo;
225 sc->sc_nrange = OF_getprop(node, "ranges", sc->sc_range,
226 sizeof(sc->sc_range));
229 if (sc->sc_nrange == -1) {
230 device_printf(dev, "could not get ranges\n");
234 sc->sc_range[6].pci_hi = 0;
238 for (rp = sc->sc_range; rp->pci_hi != 0; rp++) {
239 switch (rp->pci_hi & OFW_PCI_PHYS_HI_SPACEMASK) {
240 case OFW_PCI_PHYS_HI_SPACE_CONFIG:
242 case OFW_PCI_PHYS_HI_SPACE_IO:
245 case OFW_PCI_PHYS_HI_SPACE_MEM32:
249 case OFW_PCI_PHYS_HI_SPACE_MEM64:
255 device_printf(dev, "can't find io range\n");
258 sc->sc_io_rman.rm_type = RMAN_ARRAY;
259 sc->sc_io_rman.rm_descr = "UniNorth PCI I/O Ports";
260 sc->sc_iostart = io->host;
261 if (rman_init(&sc->sc_io_rman) != 0 ||
262 rman_manage_region(&sc->sc_io_rman, io->pci_lo,
263 io->pci_lo + io->size_lo - 1) != 0) {
264 panic("uninorth_attach: failed to set up I/O rman");
268 device_printf(dev, "can't find mem ranges\n");
271 sc->sc_mem_rman.rm_type = RMAN_ARRAY;
272 sc->sc_mem_rman.rm_descr = "UniNorth PCI Memory";
273 error = rman_init(&sc->sc_mem_rman);
275 device_printf(dev, "rman_init() failed. error = %d\n", error);
278 for (i = 0; i < nmem; i++) {
279 error = rman_manage_region(&sc->sc_mem_rman, mem[i]->pci_lo,
280 mem[i]->pci_lo + mem[i]->size_lo - 1);
283 "rman_manage_region() failed. error = %d\n", error);
288 ofw_bus_setup_iinfo(node, &sc->sc_pci_iinfo, sizeof(cell_t));
290 device_add_child(dev, "pci", device_get_unit(dev));
291 return (bus_generic_attach(dev));
295 uninorth_maxslots(device_t dev)
298 return (PCI_SLOTMAX);
302 uninorth_read_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg,
305 struct uninorth_softc *sc;
308 sc = device_get_softc(dev);
309 caoff = sc->sc_data + (reg & 0x07);
311 if (uninorth_enable_config(sc, bus, slot, func, reg) != 0) {
314 return (in8rb(caoff));
317 return (in16rb(caoff));
320 return (in32rb(caoff));
329 uninorth_write_config(device_t dev, u_int bus, u_int slot, u_int func,
330 u_int reg, u_int32_t val, int width)
332 struct uninorth_softc *sc;
335 sc = device_get_softc(dev);
336 caoff = sc->sc_data + (reg & 0x07);
338 if (uninorth_enable_config(sc, bus, slot, func, reg)) {
354 uninorth_route_interrupt(device_t bus, device_t dev, int pin)
356 struct uninorth_softc *sc;
357 struct ofw_pci_register reg;
358 uint32_t pintr, mintr;
359 uint8_t maskbuf[sizeof(reg) + sizeof(pintr)];
361 sc = device_get_softc(bus);
363 if (ofw_bus_lookup_imap(ofw_bus_get_node(dev), &sc->sc_pci_iinfo, ®,
364 sizeof(reg), &pintr, sizeof(pintr), &mintr, sizeof(mintr),
368 /* Maybe it's a real interrupt, not an intpin */
372 device_printf(bus, "could not route pin %d for device %d.%d\n",
373 pin, pci_get_slot(dev), pci_get_function(dev));
374 return (PCI_INVALID_IRQ);
378 uninorth_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
380 struct uninorth_softc *sc;
382 sc = device_get_softc(dev);
385 case PCIB_IVAR_DOMAIN:
386 *result = device_get_unit(dev);
389 *result = sc->sc_bus;
396 static struct resource *
397 uninorth_alloc_resource(device_t bus, device_t child, int type, int *rid,
398 u_long start, u_long end, u_long count, u_int flags)
400 struct uninorth_softc *sc;
405 needactivate = flags & RF_ACTIVE;
408 sc = device_get_softc(bus);
412 rm = &sc->sc_mem_rman;
416 rm = &sc->sc_io_rman;
420 return (bus_alloc_resource(bus, type, rid, start, end, count,
424 device_printf(bus, "unknown resource request from %s\n",
425 device_get_nameunit(child));
429 rv = rman_reserve_resource(rm, start, end, count, flags, child);
431 device_printf(bus, "failed to reserve resource for %s\n",
432 device_get_nameunit(child));
436 rman_set_rid(rv, *rid);
439 if (bus_activate_resource(child, type, *rid, rv) != 0) {
441 "failed to activate resource for %s\n",
442 device_get_nameunit(child));
443 rman_release_resource(rv);
452 uninorth_activate_resource(device_t bus, device_t child, int type, int rid,
453 struct resource *res)
456 struct uninorth_softc *sc;
458 sc = device_get_softc(bus);
460 if (type == SYS_RES_IRQ)
461 return (bus_activate_resource(bus, type, rid, res));
463 if (type == SYS_RES_MEMORY || type == SYS_RES_IOPORT) {
466 start = (vm_offset_t)rman_get_start(res);
468 * For i/o-ports, convert the start address to the
469 * uninorth PCI i/o window
471 if (type == SYS_RES_IOPORT)
472 start += sc->sc_iostart;
475 printf("uninorth mapdev: start %zx, len %ld\n", start,
478 p = pmap_mapdev(start, (vm_size_t)rman_get_size(res));
481 rman_set_virtual(res, p);
482 rman_set_bustag(res, &bs_le_tag);
483 rman_set_bushandle(res, (u_long)p);
486 return (rman_activate_resource(res));
490 uninorth_enable_config(struct uninorth_softc *sc, u_int bus, u_int slot,
491 u_int func, u_int reg)
496 if (resource_int_value(device_get_name(sc->sc_dev),
497 device_get_unit(sc->sc_dev), "skipslot", &pass) == 0) {
503 * Issue type 0 configuration space accesses for the root bus.
505 * NOTE: On U4, issue only type 1 accesses. There is a secret
506 * PCI Express <-> PCI Express bridge not present in the device tree,
507 * and we need to route all of our configuration space through it.
509 if (sc->sc_bus == bus && sc->sc_ver < 4) {
511 * No slots less than 11 on the primary bus on U3 and lower
516 cfgval = (1 << slot) | (func << 8) | (reg & 0xfc);
518 cfgval = (bus << 16) | (slot << 11) | (func << 8) |
522 /* Set extended register bits on U4 */
524 cfgval |= (reg >> 8) << 28;
527 out32rb(sc->sc_addr, cfgval);
528 } while (in32rb(sc->sc_addr) != cfgval);
534 uninorth_get_node(device_t bus, device_t dev)
536 struct uninorth_softc *sc;
538 sc = device_get_softc(bus);
539 /* We only have one child, the PCI bus, which needs our own node. */