sys/powerpc/powernv/opal_i2c.c

   1 /*-
   2  * Copyright (c) 2017-2018 QCM Technologies.
   3  * Copyright (c) 2017-2018 Semihalf.
   4  * All rights reserved.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions
   8  * are met:
   9  * 1. Redistributions of source code must retain the above copyright
  10  *    notice, this list of conditions and the following disclaimer.
  11  * 2. Redistributions in binary form must reproduce the above copyright
  12  *    notice, this list of conditions and the following disclaimer in the
  13  *    documentation and/or other materials provided with the distribution.
  14  *
  15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  16  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  17  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  18  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  19  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  20  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  21  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  22  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  23  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  24  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  25  * SUCH DAMAGE.
  26  *
  27  * $FreeBSD$
  28  */
  29
  30 #include "opt_platform.h"
  31
  32 #include <sys/cdefs.h>
  33 __FBSDID("$FreeBSD$");
  34
  35 #include <sys/param.h>
  36 #include <sys/endian.h>
  37 #include <sys/systm.h>
  38 #include <sys/bus.h>
  39 #include <sys/conf.h>
  40 #include <sys/kernel.h>
  41 #include <sys/lock.h>
  42 #include <sys/mbuf.h>
  43 #include <sys/malloc.h>
  44 #include <sys/module.h>
  45 #include <sys/mutex.h>
  46 #include <sys/rman.h>
  47 #include <machine/bus.h>
  48
  49 #include <vm/vm.h>
  50 #include <vm/pmap.h>
  51
  52 #include <dev/iicbus/iiconf.h>
  53 #include <dev/iicbus/iicbus.h>
  54 #include "iicbus_if.h"
  55
  56 #include "opal.h"
  57
  58 #ifdef FDT
  59 #include <dev/ofw/ofw_bus.h>
  60 #include <dev/ofw/ofw_bus_subr.h>
  61 #endif
  62
  63 struct opal_i2c_softc
  64 {
  65         device_t dev;
  66         device_t iicbus;
  67         uint32_t opal_id;
  68         struct mtx sc_mtx;
  69 };
  70
  71 /* OPAL I2C request */
  72 struct opal_i2c_request {
  73         uint8_t type;
  74 #define OPAL_I2C_RAW_READ       0
  75 #define OPAL_I2C_RAW_WRITE      1
  76 #define OPAL_I2C_SM_READ        2
  77 #define OPAL_I2C_SM_WRITE       3
  78         uint8_t flags;
  79         uint8_t subaddr_sz;             /* Max 4 */
  80         uint8_t reserved;
  81         uint16_t addr;                  /* 7 or 10 bit address */
  82         uint16_t reserved2;
  83         uint32_t subaddr;               /* Sub-address if any */
  84         uint32_t size;                  /* Data size */
  85         uint64_t buffer_pa;             /* Buffer real address */
  86 };
  87
  88 static int opal_i2c_attach(device_t);
  89 static int opal_i2c_callback(device_t, int, caddr_t);
  90 static int opal_i2c_probe(device_t);
  91 static int opal_i2c_transfer(device_t, struct iic_msg *, uint32_t);
  92 static int i2c_opal_send_request(uint32_t, struct opal_i2c_request *);
  93 static phandle_t opal_i2c_get_node(device_t bus, device_t dev);
  94
  95 static device_method_t opal_i2c_methods[] = {
  96         /* Device interface */
  97         DEVMETHOD(device_probe,         opal_i2c_probe),
  98         DEVMETHOD(device_attach,        opal_i2c_attach),
  99
 100         /* iicbus interface */
 101         DEVMETHOD(iicbus_callback,      opal_i2c_callback),
 102         DEVMETHOD(iicbus_transfer,      opal_i2c_transfer),
 103         DEVMETHOD(ofw_bus_get_node,     opal_i2c_get_node),
 104         DEVMETHOD_END
 105 };
 106
 107 #define I2C_LOCK(_sc)           mtx_lock(&(_sc)->sc_mtx)
 108 #define I2C_UNLOCK(_sc)         mtx_unlock(&(_sc)->sc_mtx)
 109 #define I2C_LOCK_INIT(_sc) \
 110         mtx_init(&_sc->sc_mtx, device_get_nameunit(_sc->dev), \
 111             "i2c", MTX_DEF)
 112
 113 static driver_t opal_i2c_driver = {
 114         "iichb",
 115         opal_i2c_methods,
 116         sizeof(struct opal_i2c_softc),
 117 };
 118
 119 static int
 120 opal_i2c_probe(device_t dev)
 121 {
 122
 123         if (!(ofw_bus_is_compatible(dev, "ibm,opal-i2c")))
 124                 return (ENXIO);
 125
 126         device_set_desc(dev, "opal-i2c");
 127
 128         return (0);
 129 }
 130
 131 static int
 132 opal_i2c_attach(device_t dev)
 133 {
 134         struct opal_i2c_softc *sc;
 135         int len;
 136
 137         sc = device_get_softc(dev);
 138         sc->dev = dev;
 139
 140         len = OF_getproplen(ofw_bus_get_node(dev), "ibm,opal-id");
 141         if (len <= 0)
 142                 return (EINVAL);
 143         OF_getencprop(ofw_bus_get_node(dev), "ibm,opal-id", &sc->opal_id, len);
 144
 145         if ((sc->iicbus = device_add_child(dev, "iicbus", -1)) == NULL) {
 146                 device_printf(dev, "could not allocate iicbus instance\n");
 147                 return (EINVAL);
 148         }
 149
 150         I2C_LOCK_INIT(sc);
 151
 152         return (bus_generic_attach(dev));
 153 }
 154
 155 static int
 156 opal_get_async_rc(struct opal_msg msg)
 157 {
 158         if (msg.msg_type != OPAL_MSG_ASYNC_COMP)
 159                 return OPAL_PARAMETER;
 160         else
 161                 return htobe64(msg.params[1]);
 162 }
 163
 164 static int
 165 i2c_opal_send_request(uint32_t bus_id, struct opal_i2c_request *req)
 166 {
 167         struct opal_msg msg;
 168         uint64_t token;
 169         int rc;
 170
 171         token = opal_alloc_async_token();
 172
 173         memset(&msg, 0, sizeof(msg));
 174
 175         rc = opal_call(OPAL_I2C_REQUEST, token, bus_id,
 176             vtophys(req));
 177         if (rc != OPAL_ASYNC_COMPLETION)
 178                 goto out;
 179
 180         rc = opal_wait_completion(&msg, sizeof(msg), token);
 181
 182         if (rc != OPAL_SUCCESS)
 183                 goto out;
 184
 185         rc = opal_get_async_rc(msg);
 186
 187 out:
 188         opal_free_async_token(token);
 189
 190         return (rc);
 191 }
 192
 193 static int
 194 opal_i2c_transfer(device_t dev, struct iic_msg *msgs, uint32_t nmsgs)
 195 {
 196         struct opal_i2c_softc *sc;
 197         int i, err = 0;
 198         struct opal_i2c_request req;
 199
 200         sc = device_get_softc(dev);
 201
 202         memset(&req, 0, sizeof(req));
 203
 204         I2C_LOCK(sc);
 205         for (i = 0; i < nmsgs; i++) {
 206                 req.type = (msgs[i].flags & IIC_M_RD) ?
 207                     OPAL_I2C_RAW_READ : OPAL_I2C_RAW_WRITE;
 208                 req.addr = htobe16(msgs[i].slave >> 1);
 209                 req.size = htobe32(msgs[i].len);
 210                 req.buffer_pa = htobe64(pmap_kextract((uint64_t)msgs[i].buf));
 211
 212                 err = i2c_opal_send_request(sc->opal_id, &req);
 213         }
 214         I2C_UNLOCK(sc);
 215
 216         return (err);
 217 }
 218
 219 static int
 220 opal_i2c_callback(device_t dev, int index, caddr_t data)
 221 {
 222         int error = 0;
 223
 224         switch (index) {
 225         case IIC_REQUEST_BUS:
 226                 break;
 227
 228         case IIC_RELEASE_BUS:
 229                 break;
 230
 231         default:
 232                 error = EINVAL;
 233         }
 234
 235         return (error);
 236 }
 237
 238 static phandle_t
 239 opal_i2c_get_node(device_t bus, device_t dev)
 240 {
 241
 242         /* Share controller node with iibus device. */
 243         return (ofw_bus_get_node(bus));
 244 }
 245
 246 DRIVER_MODULE(opal_i2c, opal_i2cm, opal_i2c_driver, NULL, NULL);
 247 DRIVER_MODULE(iicbus, opal_i2c, iicbus_driver, NULL, NULL);
 248 MODULE_DEPEND(opal_i2c, iicbus, 1, 1, 1);