2 * Copyright (c) 2015-2016 Nathan Whitehorn
3 * Copyright (c) 2017-2018 Semihalf
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 #include <sys/cdefs.h>
29 __FBSDID("$FreeBSD$");
30 #include <sys/param.h>
31 #include <sys/systm.h>
32 #include <sys/module.h>
35 #include <sys/kernel.h>
36 #include <sys/pciio.h>
37 #include <sys/endian.h>
41 #include <dev/ofw/openfirm.h>
42 #include <dev/ofw/ofw_pci.h>
43 #include <dev/ofw/ofw_bus.h>
44 #include <dev/ofw/ofw_bus_subr.h>
45 #include <dev/ofw/ofwpci.h>
47 #include <dev/pci/pcivar.h>
48 #include <dev/pci/pcireg.h>
50 #include <machine/bus.h>
51 #include <machine/intr_machdep.h>
52 #include <machine/md_var.h>
62 #define OPAL_PCI_TCE_MAX_ENTRIES (1024*1024UL)
63 #define OPAL_PCI_TCE_DEFAULT_SEG_SIZE (16*1024*1024UL)
64 #define OPAL_PCI_TCE_R (1UL << 0)
65 #define OPAL_PCI_TCE_W (1UL << 1)
66 #define PHB3_TCE_KILL_INVAL_ALL (1UL << 63)
71 static int opalpci_probe(device_t);
72 static int opalpci_attach(device_t);
77 static uint32_t opalpci_read_config(device_t, u_int, u_int, u_int,
79 static void opalpci_write_config(device_t, u_int, u_int, u_int,
80 u_int, u_int32_t, int);
81 static int opalpci_alloc_msi(device_t dev, device_t child,
82 int count, int maxcount, int *irqs);
83 static int opalpci_release_msi(device_t dev, device_t child,
84 int count, int *irqs);
85 static int opalpci_alloc_msix(device_t dev, device_t child,
87 static int opalpci_release_msix(device_t dev, device_t child,
89 static int opalpci_map_msi(device_t dev, device_t child,
90 int irq, uint64_t *addr, uint32_t *data);
91 static int opalpci_route_interrupt(device_t bus, device_t dev, int pin);
96 static void opalpic_pic_enable(device_t dev, u_int irq, u_int vector, void **);
97 static void opalpic_pic_eoi(device_t dev, u_int irq, void *);
100 static bus_dma_tag_t opalpci_get_dma_tag(device_t dev, device_t child);
105 #define OPAL_M32_WINDOW_TYPE 1
106 #define OPAL_M64_WINDOW_TYPE 2
107 #define OPAL_IO_WINDOW_TYPE 3
109 #define OPAL_RESET_PHB_COMPLETE 1
110 #define OPAL_RESET_PCI_IODA_TABLE 6
112 #define OPAL_DISABLE_M64 0
113 #define OPAL_ENABLE_M64_SPLIT 1
114 #define OPAL_ENABLE_M64_NON_SPLIT 2
116 #define OPAL_EEH_ACTION_CLEAR_FREEZE_MMIO 1
117 #define OPAL_EEH_ACTION_CLEAR_FREEZE_DMA 2
118 #define OPAL_EEH_ACTION_CLEAR_FREEZE_ALL 3
120 #define OPAL_EEH_STOPPED_NOT_FROZEN 0
125 #define OPAL_PCI_DEFAULT_PE 1
127 #define OPAL_PCI_BUS_SPACE_LOWADDR_32BIT 0x7FFFFFFFUL
132 static device_method_t opalpci_methods[] = {
133 /* Device interface */
134 DEVMETHOD(device_probe, opalpci_probe),
135 DEVMETHOD(device_attach, opalpci_attach),
138 DEVMETHOD(pcib_read_config, opalpci_read_config),
139 DEVMETHOD(pcib_write_config, opalpci_write_config),
141 DEVMETHOD(pcib_alloc_msi, opalpci_alloc_msi),
142 DEVMETHOD(pcib_release_msi, opalpci_release_msi),
143 DEVMETHOD(pcib_alloc_msix, opalpci_alloc_msix),
144 DEVMETHOD(pcib_release_msix, opalpci_release_msix),
145 DEVMETHOD(pcib_map_msi, opalpci_map_msi),
146 DEVMETHOD(pcib_route_interrupt, opalpci_route_interrupt),
148 /* PIC interface for MSIs */
149 DEVMETHOD(pic_enable, opalpic_pic_enable),
150 DEVMETHOD(pic_eoi, opalpic_pic_eoi),
153 DEVMETHOD(bus_get_dma_tag, opalpci_get_dma_tag),
154 DEVMETHOD(bus_get_cpus, ofw_pcibus_get_cpus),
155 DEVMETHOD(bus_get_domain, ofw_pcibus_get_domain),
160 struct opalpci_softc {
161 struct ofw_pci_softc ofw_sc;
164 int msi_base; /* Base XIVE number */
165 int base_msi_irq; /* Base IRQ assigned by FreeBSD to this PIC */
166 uint64_t *tce; /* TCE table for 1:1 mapping */
167 struct resource *r_reg;
170 static devclass_t opalpci_devclass;
171 DEFINE_CLASS_1(pcib, opalpci_driver, opalpci_methods,
172 sizeof(struct opalpci_softc), ofw_pci_driver);
173 EARLY_DRIVER_MODULE(opalpci, ofwbus, opalpci_driver, opalpci_devclass, 0, 0,
177 opalpci_probe(device_t dev)
181 if (opal_check() != 0)
184 type = ofw_bus_get_type(dev);
186 if (type == NULL || (strcmp(type, "pci") != 0 &&
187 strcmp(type, "pciex") != 0))
190 if (!OF_hasprop(ofw_bus_get_node(dev), "ibm,opal-phbid"))
193 device_set_desc(dev, "OPAL Host-PCI bridge");
194 return (BUS_PROBE_GENERIC);
198 pci_phb3_tce_invalidate_entire(struct opalpci_softc *sc)
202 bus_write_8(sc->r_reg, 0x210, PHB3_TCE_KILL_INVAL_ALL);
206 /* Simple function to round to a power of 2 */
208 round_pow2(uint64_t val)
211 return (1 << (flsl(val + (val - 1)) - 1));
215 * Starting with skiboot 5.10 PCIe nodes have a new property,
216 * "ibm,supported-tce-sizes", to denote the TCE sizes available. This allows us
217 * to avoid hard-coding the maximum TCE size allowed, and instead provide a sane
218 * default (however, the "sane" default, which works for all targets, is 64k,
219 * limiting us to 64GB if we have 1M entries.
222 max_tce_size(device_t dev)
225 cell_t sizes[64]; /* Property is a list of bit-widths, up to 64-bits */
228 node = ofw_bus_get_node(dev);
230 count = OF_getencprop(node, "ibm,supported-tce-sizes",
231 sizes, sizeof(sizes));
232 if (count < (int) sizeof(cell_t))
233 return OPAL_PCI_TCE_DEFAULT_SEG_SIZE;
235 count /= sizeof(cell_t);
237 return (1ULL << sizes[count - 1]);
241 opalpci_attach(device_t dev)
243 struct opalpci_softc *sc;
244 cell_t id[2], m64ranges[2], m64window[6], npe;
250 uint64_t tce_tbl_size;
254 sc = device_get_softc(dev);
255 node = ofw_bus_get_node(dev);
257 switch (OF_getproplen(node, "ibm,opal-phbid")) {
259 OF_getencprop(node, "ibm,opal-phbid", id, 8);
260 sc->phb_id = ((uint64_t)id[0] << 32) | id[1];
263 OF_getencprop(node, "ibm,opal-phbid", id, 4);
267 device_printf(dev, "PHB ID property had wrong length (%zd)\n",
268 OF_getproplen(node, "ibm,opal-phbid"));
273 device_printf(dev, "OPAL ID %#lx\n", sc->phb_id);
276 sc->r_reg = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
277 &rid, RF_ACTIVE | RF_SHAREABLE);
278 if (sc->r_reg == NULL) {
279 device_printf(dev, "Failed to allocate PHB[%jd] registers\n",
280 (uintmax_t)sc->phb_id);
286 * Reset PCI IODA table
288 err = opal_call(OPAL_PCI_RESET, sc->phb_id, OPAL_RESET_PCI_IODA_TABLE,
291 device_printf(dev, "IODA table reset failed: %d\n", err);
294 err = opal_call(OPAL_PCI_RESET, sc->phb_id, OPAL_RESET_PHB_COMPLETE,
297 device_printf(dev, "PHB reset failed: %d\n", err);
301 while ((err = opal_call(OPAL_PCI_POLL, sc->phb_id)) > 0) {
302 DELAY(1000*(err + 1)); /* Returns expected delay in ms */
306 device_printf(dev, "WARNING: PHB IODA reset poll failed: %d\n", err);
308 err = opal_call(OPAL_PCI_RESET, sc->phb_id, OPAL_RESET_PHB_COMPLETE,
311 device_printf(dev, "PHB reset failed: %d\n", err);
315 while ((err = opal_call(OPAL_PCI_POLL, sc->phb_id)) > 0) {
316 DELAY(1000*(err + 1)); /* Returns expected delay in ms */
322 * Map all devices on the bus to partitionable endpoint one until
323 * such time as we start wanting to do things like bhyve.
325 err = opal_call(OPAL_PCI_SET_PE, sc->phb_id, OPAL_PCI_DEFAULT_PE,
326 0, OPAL_PCI_BUS_ANY, OPAL_IGNORE_RID_DEVICE_NUMBER,
327 OPAL_IGNORE_RID_FUNC_NUMBER, OPAL_MAP_PE);
329 device_printf(dev, "PE mapping failed: %d\n", err);
334 * Turn on MMIO, mapped to PE 1
336 if (OF_getencprop(node, "ibm,opal-num-pes", &npe, 4) != 4)
338 for (i = 0; i < npe; i++) {
339 err = opal_call(OPAL_PCI_MAP_PE_MMIO_WINDOW, sc->phb_id,
340 OPAL_PCI_DEFAULT_PE, OPAL_M32_WINDOW_TYPE, 0, i);
342 device_printf(dev, "MMIO %d map failed: %d\n", i, err);
345 if (OF_getencprop(node, "ibm,opal-available-m64-ranges",
346 m64ranges, sizeof(m64ranges)) == sizeof(m64ranges))
347 m64bar = m64ranges[0];
351 /* XXX: multiple M64 windows? */
352 if (OF_getencprop(node, "ibm,opal-m64-window",
353 m64window, sizeof(m64window)) == sizeof(m64window)) {
354 opal_call(OPAL_PCI_PHB_MMIO_ENABLE, sc->phb_id,
355 OPAL_M64_WINDOW_TYPE, m64bar, 0);
356 opal_call(OPAL_PCI_SET_PHB_MEM_WINDOW, sc->phb_id,
357 OPAL_M64_WINDOW_TYPE, m64bar /* index */,
358 ((uint64_t)m64window[2] << 32) | m64window[3], 0,
359 ((uint64_t)m64window[4] << 32) | m64window[5]);
360 opal_call(OPAL_PCI_MAP_PE_MMIO_WINDOW, sc->phb_id,
361 OPAL_PCI_DEFAULT_PE, OPAL_M64_WINDOW_TYPE,
362 m64bar /* index */, 0);
363 opal_call(OPAL_PCI_PHB_MMIO_ENABLE, sc->phb_id,
364 OPAL_M64_WINDOW_TYPE, m64bar, OPAL_ENABLE_M64_NON_SPLIT);
368 * Enable IOMMU for PE1 - map everything 1:1 using
369 * segments of max_tce_size size
371 tce_size = max_tce_size(dev);
372 maxmem = roundup2(powerpc_ptob(Maxmem), tce_size);
373 entries = round_pow2(maxmem / tce_size);
374 tce_tbl_size = MAX(entries * sizeof(uint64_t), 4096);
375 if (entries > OPAL_PCI_TCE_MAX_ENTRIES)
376 panic("POWERNV supports only %jdGB of memory space\n",
377 (uintmax_t)((OPAL_PCI_TCE_MAX_ENTRIES * tce_size) >> 30));
379 device_printf(dev, "Mapping 0-%#jx for DMA\n", (uintmax_t)maxmem);
380 sc->tce = contigmalloc(tce_tbl_size,
381 M_DEVBUF, M_NOWAIT | M_ZERO, 0,
382 BUS_SPACE_MAXADDR, tce_tbl_size, 0);
384 panic("Failed to allocate TCE memory for PHB %jd\n",
385 (uintmax_t)sc->phb_id);
387 for (i = 0; i < entries; i++)
388 sc->tce[i] = htobe64((i * tce_size) | OPAL_PCI_TCE_R | OPAL_PCI_TCE_W);
390 /* Map TCE for every PE. It seems necessary for Power8 */
391 for (i = 0; i < npe; i++) {
392 err = opal_call(OPAL_PCI_MAP_PE_DMA_WINDOW, sc->phb_id,
394 1, pmap_kextract((uint64_t)&sc->tce[0]),
395 tce_tbl_size, tce_size);
397 device_printf(dev, "DMA IOMMU mapping failed: %d\n", err);
401 err = opal_call(OPAL_PCI_MAP_PE_DMA_WINDOW_REAL, sc->phb_id,
403 (1UL << 59), maxmem);
405 device_printf(dev, "DMA 64b bypass mapping failed: %d\n", err);
411 * Invalidate all previous TCE entries.
413 if (ofw_bus_is_compatible(dev, "power8-pciex"))
414 pci_phb3_tce_invalidate_entire(sc);
416 opal_call(OPAL_PCI_TCE_KILL, sc->phb_id, OPAL_PCI_TCE_KILL_ALL,
417 OPAL_PCI_DEFAULT_PE, 0, 0, 0);
423 if (OF_getproplen(node, "ibm,opal-msi-ranges") > 0) {
424 cell_t msi_ranges[2];
425 OF_getencprop(node, "ibm,opal-msi-ranges",
426 msi_ranges, sizeof(msi_ranges));
427 sc->msi_base = msi_ranges[0];
429 sc->msi_vmem = vmem_create("OPAL MSI", msi_ranges[0],
430 msi_ranges[1], 1, 0, M_BESTFIT | M_WAITOK);
432 sc->base_msi_irq = powerpc_register_pic(dev,
433 OF_xref_from_node(node),
434 msi_ranges[0] + msi_ranges[1], 0, FALSE);
437 device_printf(dev, "Supports %d MSIs starting at %d\n",
438 msi_ranges[1], msi_ranges[0]);
441 /* Create the parent DMA tag */
443 * Constrain it to POWER8 PHB (ioda2) for now. It seems to mess up on
446 if (ofw_bus_is_compatible(dev, "ibm,ioda2-phb")) {
447 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */
448 1, 0, /* alignment, bounds */
449 OPAL_PCI_BUS_SPACE_LOWADDR_32BIT, /* lowaddr */
450 BUS_SPACE_MAXADDR_32BIT, /* highaddr */
451 NULL, NULL, /* filter, filterarg */
452 BUS_SPACE_MAXSIZE, /* maxsize */
453 BUS_SPACE_UNRESTRICTED, /* nsegments */
454 BUS_SPACE_MAXSIZE, /* maxsegsize */
456 NULL, NULL, /* lockfunc, lockarg */
457 &sc->ofw_sc.sc_dmat);
459 device_printf(dev, "Failed to create DMA tag\n");
465 * General OFW PCI attach
467 err = ofw_pci_init(dev);
472 * Unfreeze non-config-space PCI operations. Let this fail silently
473 * if e.g. there is no current freeze.
475 opal_call(OPAL_PCI_EEH_FREEZE_CLEAR, sc->phb_id, OPAL_PCI_DEFAULT_PE,
476 OPAL_EEH_ACTION_CLEAR_FREEZE_ALL);
479 * OPAL stores 64-bit BARs in a special property rather than "ranges"
481 if (OF_getencprop(node, "ibm,opal-m64-window",
482 m64window, sizeof(m64window)) == sizeof(m64window)) {
483 struct ofw_pci_range *rp;
485 sc->ofw_sc.sc_nrange++;
486 sc->ofw_sc.sc_range = realloc(sc->ofw_sc.sc_range,
487 sc->ofw_sc.sc_nrange * sizeof(sc->ofw_sc.sc_range[0]),
489 rp = &sc->ofw_sc.sc_range[sc->ofw_sc.sc_nrange-1];
490 rp->pci_hi = OFW_PCI_PHYS_HI_SPACE_MEM64 |
491 OFW_PCI_PHYS_HI_PREFETCHABLE;
492 rp->pci = ((uint64_t)m64window[0] << 32) | m64window[1];
493 rp->host = ((uint64_t)m64window[2] << 32) | m64window[3];
494 rp->size = ((uint64_t)m64window[4] << 32) | m64window[5];
495 rman_manage_region(&sc->ofw_sc.sc_mem_rman, rp->pci,
496 rp->pci + rp->size - 1);
499 return (ofw_pci_attach(dev));
503 opalpci_read_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg,
506 struct opalpci_softc *sc;
507 uint64_t config_addr;
508 uint8_t byte, eeh_state;
514 sc = device_get_softc(dev);
516 config_addr = (bus << 8) | ((slot & 0x1f) << 3) | (func & 0x7);
520 error = opal_call(OPAL_PCI_CONFIG_READ_BYTE, sc->phb_id,
521 config_addr, reg, vtophys(&byte));
525 error = opal_call(OPAL_PCI_CONFIG_READ_HALF_WORD, sc->phb_id,
526 config_addr, reg, vtophys(&half));
527 word = be16toh(half);
530 error = opal_call(OPAL_PCI_CONFIG_READ_WORD, sc->phb_id,
531 config_addr, reg, vtophys(&word));
532 word = be32toh(word);
535 error = OPAL_SUCCESS;
541 * Poking config state for non-existant devices can make
542 * the host bridge hang up. Clear any errors.
545 if (error != OPAL_SUCCESS ||
546 (word == ((1UL << (8 * width)) - 1))) {
547 if (error != OPAL_HARDWARE) {
548 opal_call(OPAL_PCI_EEH_FREEZE_STATUS, sc->phb_id,
549 OPAL_PCI_DEFAULT_PE, vtophys(&eeh_state),
550 vtophys(&err_type), NULL);
551 err_type = be16toh(err_type); /* XXX unused */
552 if (eeh_state != OPAL_EEH_STOPPED_NOT_FROZEN)
553 opal_call(OPAL_PCI_EEH_FREEZE_CLEAR,
554 sc->phb_id, OPAL_PCI_DEFAULT_PE,
555 OPAL_EEH_ACTION_CLEAR_FREEZE_ALL);
557 if (error != OPAL_SUCCESS)
565 opalpci_write_config(device_t dev, u_int bus, u_int slot, u_int func,
566 u_int reg, uint32_t val, int width)
568 struct opalpci_softc *sc;
569 uint64_t config_addr;
570 int error = OPAL_SUCCESS;
572 sc = device_get_softc(dev);
574 config_addr = (bus << 8) | ((slot & 0x1f) << 3) | (func & 0x7);
578 error = opal_call(OPAL_PCI_CONFIG_WRITE_BYTE, sc->phb_id,
579 config_addr, reg, val);
582 error = opal_call(OPAL_PCI_CONFIG_WRITE_HALF_WORD, sc->phb_id,
583 config_addr, reg, val);
586 error = opal_call(OPAL_PCI_CONFIG_WRITE_WORD, sc->phb_id,
587 config_addr, reg, val);
591 if (error != OPAL_SUCCESS) {
593 * Poking config state for non-existant devices can make
594 * the host bridge hang up. Clear any errors.
596 if (error != OPAL_HARDWARE) {
597 opal_call(OPAL_PCI_EEH_FREEZE_CLEAR,
598 sc->phb_id, OPAL_PCI_DEFAULT_PE,
599 OPAL_EEH_ACTION_CLEAR_FREEZE_ALL);
605 opalpci_route_interrupt(device_t bus, device_t dev, int pin)
612 opalpci_alloc_msi(device_t dev, device_t child, int count, int maxcount,
615 struct opalpci_softc *sc;
620 sc = device_get_softc(dev);
621 if (sc->msi_vmem == NULL)
624 err = vmem_xalloc(sc->msi_vmem, count, powerof2(count), 0, 0,
625 VMEM_ADDR_MIN, VMEM_ADDR_MAX, M_BESTFIT | M_WAITOK, &start);
630 xref = OF_xref_from_node(ofw_bus_get_node(dev));
631 for (i = 0; i < count; i++)
632 irqs[i] = MAP_IRQ(xref, start + i);
638 opalpci_release_msi(device_t dev, device_t child, int count, int *irqs)
640 struct opalpci_softc *sc;
642 sc = device_get_softc(dev);
643 if (sc->msi_vmem == NULL)
646 vmem_xfree(sc->msi_vmem, irqs[0] - sc->base_msi_irq, count);
651 opalpci_alloc_msix(device_t dev, device_t child, int *irq)
653 return (opalpci_alloc_msi(dev, child, 1, 1, irq));
657 opalpci_release_msix(device_t dev, device_t child, int irq)
659 return (opalpci_release_msi(dev, child, 1, &irq));
663 opalpci_map_msi(device_t dev, device_t child, int irq, uint64_t *addr,
666 struct opalpci_softc *sc;
667 struct pci_devinfo *dinfo;
670 sc = device_get_softc(dev);
671 if (sc->msi_vmem == NULL)
674 xive = irq - sc->base_msi_irq - sc->msi_base;
675 opal_call(OPAL_PCI_SET_XIVE_PE, sc->phb_id, OPAL_PCI_DEFAULT_PE, xive);
677 dinfo = device_get_ivars(child);
678 if (dinfo->cfg.msi.msi_alloc > 0 &&
679 (dinfo->cfg.msi.msi_ctrl & PCIM_MSICTRL_64BIT) == 0) {
681 err = opal_call(OPAL_GET_MSI_32, sc->phb_id,
682 OPAL_PCI_DEFAULT_PE, xive, 1, vtophys(&msi32),
684 *addr = be32toh(msi32);
686 err = opal_call(OPAL_GET_MSI_64, sc->phb_id,
687 OPAL_PCI_DEFAULT_PE, xive, 1, vtophys(addr), vtophys(data));
688 *addr = be64toh(*addr);
690 *data = be32toh(*data);
692 if (bootverbose && err != 0)
693 device_printf(child, "OPAL MSI mapping error: %d\n", err);
695 return ((err == 0) ? 0 : ENXIO);
699 opalpic_pic_enable(device_t dev, u_int irq, u_int vector, void **priv)
701 struct opalpci_softc *sc = device_get_softc(dev);
703 PIC_ENABLE(root_pic, irq, vector, priv);
704 opal_call(OPAL_PCI_MSI_EOI, sc->phb_id, irq, priv);
707 static void opalpic_pic_eoi(device_t dev, u_int irq, void *priv)
709 struct opalpci_softc *sc;
711 sc = device_get_softc(dev);
712 opal_call(OPAL_PCI_MSI_EOI, sc->phb_id, irq);
714 PIC_EOI(root_pic, irq, priv);
718 opalpci_get_dma_tag(device_t dev, device_t child)
720 struct opalpci_softc *sc;
722 sc = device_get_softc(dev);
723 return (sc->ofw_sc.sc_dmat);