2 * Copyright (c) 2015 Nathan Whitehorn
3 * Copyright (c) 2017-2018 Semihalf
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
21 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
25 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 #include <sys/param.h>
29 #include <sys/systm.h>
30 #include <sys/kernel.h>
38 #include <machine/bus.h>
39 #include <machine/cpu.h>
40 #include <machine/hid.h>
41 #include <machine/platformvar.h>
42 #include <machine/pmap.h>
43 #include <machine/rtas.h>
44 #include <machine/smp.h>
45 #include <machine/spr.h>
46 #include <machine/trap.h>
48 #include <dev/ofw/openfirm.h>
49 #include <dev/ofw/ofw_bus.h>
50 #include <dev/ofw/ofw_bus_subr.h>
51 #include <machine/ofw_machdep.h>
52 #include <powerpc/aim/mmu_oea64.h>
54 #include "platform_if.h"
61 void (*powernv_smp_ap_extra_init)(void);
63 static int powernv_probe(platform_t);
64 static int powernv_attach(platform_t);
65 void powernv_mem_regions(platform_t, struct mem_region *phys, int *physsz,
66 struct mem_region *avail, int *availsz);
67 static void powernv_numa_mem_regions(platform_t plat, struct numa_mem_region *phys, int *physsz);
68 static u_long powernv_timebase_freq(platform_t, struct cpuref *cpuref);
69 static int powernv_smp_first_cpu(platform_t, struct cpuref *cpuref);
70 static int powernv_smp_next_cpu(platform_t, struct cpuref *cpuref);
71 static int powernv_smp_get_bsp(platform_t, struct cpuref *cpuref);
72 static void powernv_smp_ap_init(platform_t);
74 static int powernv_smp_start_cpu(platform_t, struct pcpu *cpu);
75 static void powernv_smp_probe_threads(platform_t);
76 static struct cpu_group *powernv_smp_topo(platform_t plat);
78 static void powernv_reset(platform_t);
79 static void powernv_cpu_idle(sbintime_t sbt);
80 static int powernv_cpuref_init(void);
81 static int powernv_node_numa_domain(platform_t platform, phandle_t node);
83 static platform_method_t powernv_methods[] = {
84 PLATFORMMETHOD(platform_probe, powernv_probe),
85 PLATFORMMETHOD(platform_attach, powernv_attach),
86 PLATFORMMETHOD(platform_mem_regions, powernv_mem_regions),
87 PLATFORMMETHOD(platform_numa_mem_regions, powernv_numa_mem_regions),
88 PLATFORMMETHOD(platform_timebase_freq, powernv_timebase_freq),
90 PLATFORMMETHOD(platform_smp_ap_init, powernv_smp_ap_init),
91 PLATFORMMETHOD(platform_smp_first_cpu, powernv_smp_first_cpu),
92 PLATFORMMETHOD(platform_smp_next_cpu, powernv_smp_next_cpu),
93 PLATFORMMETHOD(platform_smp_get_bsp, powernv_smp_get_bsp),
95 PLATFORMMETHOD(platform_smp_start_cpu, powernv_smp_start_cpu),
96 PLATFORMMETHOD(platform_smp_probe_threads, powernv_smp_probe_threads),
97 PLATFORMMETHOD(platform_smp_topo, powernv_smp_topo),
99 PLATFORMMETHOD(platform_node_numa_domain, powernv_node_numa_domain),
101 PLATFORMMETHOD(platform_reset, powernv_reset),
105 static platform_def_t powernv_platform = {
111 static struct cpuref platform_cpuref[MAXCPU];
112 static int platform_cpuref_cnt;
113 static int platform_cpuref_valid;
114 static int platform_associativity;
116 PLATFORM_DEF(powernv_platform);
118 static uint64_t powernv_boot_pir;
121 powernv_probe(platform_t plat)
123 if (opal_check() == 0)
124 return (BUS_PROBE_SPECIFIC);
130 powernv_attach(platform_t plat)
132 uint32_t nptlp, shift = 0, slb_encoding = 0;
133 int32_t lp_size, lp_encoding;
135 pcell_t refpoints[3];
143 /* Ping OPAL again just to make sure */
146 #if BYTE_ORDER == LITTLE_ENDIAN
147 opal_call(OPAL_REINIT_CPUS, 2 /* Little endian */);
149 opal_call(OPAL_REINIT_CPUS, 1 /* Big endian */);
151 opal = OF_finddevice("/ibm,opal");
153 platform_associativity = 4; /* Skiboot default. */
154 if (OF_getencprop(opal, "ibm,associativity-reference-points", refpoints,
155 sizeof(refpoints)) > 0) {
156 platform_associativity = refpoints[0];
159 if (cpu_idle_hook == NULL)
160 cpu_idle_hook = powernv_cpu_idle;
162 powernv_boot_pir = mfspr(SPR_PIR);
164 /* LPID must not be altered when PSL_DR or PSL_IR is set */
166 mtmsr(msr & ~(PSL_DR | PSL_IR));
168 /* Direct interrupts to SRR instead of HSRR and reset LPCR otherwise */
172 if (cpu_features2 & PPC_FEATURE2_ARCH_3_00)
175 #if BYTE_ORDER == LITTLE_ENDIAN
179 mtspr(SPR_LPCR, lpcr);
184 powernv_cpuref_init();
186 /* Set SLB count from device tree */
190 res = OF_getprop(cpu, "name", buf, sizeof(buf));
191 if (res > 0 && strcmp(buf, "cpus") == 0)
200 res = OF_getprop(cpu, "device_type", buf, sizeof(buf));
201 if (res > 0 && strcmp(buf, "cpu") == 0)
208 res = OF_getencprop(cpu, "ibm,slb-size", &prop, sizeof(prop));
213 * Scan the large page size property for PAPR compatible machines.
214 * See PAPR D.5 Changes to Section 5.1.4, 'CPU Node Properties'
215 * for the encoding of the property.
218 len = OF_getproplen(cpu, "ibm,segment-page-sizes");
221 * We have to use a variable length array on the stack
222 * since we have very limited stack space.
224 pcell_t arr[len/sizeof(cell_t)];
225 res = OF_getencprop(cpu, "ibm,segment-page-sizes", arr,
232 slb_encoding = arr[idx + 1];
233 nptlp = arr[idx + 2];
236 while (len > 0 && nptlp) {
238 lp_encoding = arr[idx+1];
239 if (slb_encoding == SLBV_L && lp_encoding == 0)
242 if (slb_encoding == SLB_PGSZ_4K_4K &&
243 lp_encoding == LP_4K_16M)
244 moea64_has_lp_4k_16m = true;
250 if (has_lp && moea64_has_lp_4k_16m)
255 panic("Standard large pages (SLB[L] = 1, PTE[LP] = 0) "
256 "not supported by this system.");
258 moea64_large_page_shift = shift;
259 moea64_large_page_size = 1ULL << lp_size;
267 powernv_mem_regions(platform_t plat, struct mem_region *phys, int *physsz,
268 struct mem_region *avail, int *availsz)
271 ofw_mem_regions(phys, physsz, avail, availsz);
275 powernv_numa_mem_regions(platform_t plat, struct numa_mem_region *phys, int *physsz)
278 ofw_numa_mem_regions(phys, physsz);
282 powernv_timebase_freq(platform_t plat, struct cpuref *cpuref)
285 phandle_t cpu, dev, root;
290 dev = OF_child(root);
292 res = OF_getprop(dev, "name", buf, sizeof(buf));
293 if (res > 0 && strcmp(buf, "cpus") == 0)
298 for (cpu = OF_child(dev); cpu != 0; cpu = OF_peer(cpu)) {
299 res = OF_getprop(cpu, "device_type", buf, sizeof(buf));
300 if (res > 0 && strcmp(buf, "cpu") == 0)
306 OF_getencprop(cpu, "timebase-frequency", &ticks, sizeof(ticks));
309 panic("Unable to determine timebase frequency!");
316 powernv_cpuref_init(void)
320 int a, res, tmp_cpuref_cnt;
321 static struct cpuref tmp_cpuref[MAXCPU];
322 cell_t interrupt_servers[32];
325 if (platform_cpuref_valid)
331 res = OF_getprop(dev, "name", buf, sizeof(buf));
332 if (res > 0 && strcmp(buf, "cpus") == 0)
339 for (cpu = OF_child(dev); cpu != 0; cpu = OF_peer(cpu)) {
340 res = OF_getprop(cpu, "device_type", buf, sizeof(buf));
341 if (res > 0 && strcmp(buf, "cpu") == 0) {
342 if (!ofw_bus_node_status_okay(cpu))
344 res = OF_getproplen(cpu, "ibm,ppc-interrupt-server#s");
346 OF_getencprop(cpu, "ibm,ppc-interrupt-server#s",
347 interrupt_servers, res);
349 for (a = 0; a < res/sizeof(cell_t); a++) {
350 tmp_cpuref[tmp_cpuref_cnt].cr_hwref = interrupt_servers[a];
351 tmp_cpuref[tmp_cpuref_cnt].cr_cpuid = tmp_cpuref_cnt;
352 tmp_cpuref[tmp_cpuref_cnt].cr_domain =
353 powernv_node_numa_domain(NULL, cpu);
354 if (interrupt_servers[a] == (uint32_t)powernv_boot_pir)
355 bsp = tmp_cpuref_cnt;
363 /* Map IDs, so BSP has CPUID 0 regardless of hwref */
364 for (a = bsp; a < tmp_cpuref_cnt; a++) {
365 platform_cpuref[platform_cpuref_cnt].cr_hwref = tmp_cpuref[a].cr_hwref;
366 platform_cpuref[platform_cpuref_cnt].cr_cpuid = platform_cpuref_cnt;
367 platform_cpuref[platform_cpuref_cnt].cr_domain = tmp_cpuref[a].cr_domain;
368 platform_cpuref_cnt++;
370 for (a = 0; a < bsp; a++) {
371 platform_cpuref[platform_cpuref_cnt].cr_hwref = tmp_cpuref[a].cr_hwref;
372 platform_cpuref[platform_cpuref_cnt].cr_cpuid = platform_cpuref_cnt;
373 platform_cpuref[platform_cpuref_cnt].cr_domain = tmp_cpuref[a].cr_domain;
374 platform_cpuref_cnt++;
377 platform_cpuref_valid = 1;
383 powernv_smp_first_cpu(platform_t plat, struct cpuref *cpuref)
385 if (platform_cpuref_valid == 0)
388 cpuref->cr_cpuid = 0;
389 cpuref->cr_hwref = platform_cpuref[0].cr_hwref;
390 cpuref->cr_domain = platform_cpuref[0].cr_domain;
396 powernv_smp_next_cpu(platform_t plat, struct cpuref *cpuref)
400 if (platform_cpuref_valid == 0)
403 id = cpuref->cr_cpuid + 1;
404 if (id >= platform_cpuref_cnt)
407 cpuref->cr_cpuid = platform_cpuref[id].cr_cpuid;
408 cpuref->cr_hwref = platform_cpuref[id].cr_hwref;
409 cpuref->cr_domain = platform_cpuref[id].cr_domain;
415 powernv_smp_get_bsp(platform_t plat, struct cpuref *cpuref)
418 cpuref->cr_cpuid = platform_cpuref[0].cr_cpuid;
419 cpuref->cr_hwref = platform_cpuref[0].cr_hwref;
420 cpuref->cr_domain = platform_cpuref[0].cr_domain;
426 powernv_smp_start_cpu(platform_t plat, struct pcpu *pc)
433 result = opal_call(OPAL_START_CPU, pc->pc_hwref, EXC_RST);
434 if (result != OPAL_SUCCESS) {
435 printf("OPAL error (%d): unable to start AP %d\n",
436 result, (int)pc->pc_hwref);
444 powernv_smp_probe_threads(platform_t plat)
447 phandle_t cpu, dev, root;
452 dev = OF_child(root);
454 res = OF_getprop(dev, "name", buf, sizeof(buf));
455 if (res > 0 && strcmp(buf, "cpus") == 0)
461 for (cpu = OF_child(dev); cpu != 0; cpu = OF_peer(cpu)) {
462 res = OF_getprop(cpu, "device_type", buf, sizeof(buf));
463 if (res <= 0 || strcmp(buf, "cpu") != 0)
466 res = OF_getproplen(cpu, "ibm,ppc-interrupt-server#s");
469 nthreads = res / sizeof(cell_t);
475 smp_threads_per_core = nthreads;
476 if (mp_ncpus % nthreads == 0)
477 mp_ncores = mp_ncpus / nthreads;
480 static struct cpu_group *
481 cpu_group_init(struct cpu_group *group, struct cpu_group *parent,
482 const cpuset_t *cpus, int children, int level, int flags)
484 struct cpu_group *child;
486 child = children != 0 ? smp_topo_alloc(children) : NULL;
488 group->cg_parent = parent;
489 group->cg_child = child;
490 CPU_COPY(cpus, &group->cg_mask);
491 group->cg_count = CPU_COUNT(cpus);
492 group->cg_children = children;
493 group->cg_level = level;
494 group->cg_flags = flags;
499 static struct cpu_group *
500 powernv_smp_topo(platform_t plat)
502 struct cpu_group *core, *dom, *root;
503 cpuset_t corecpus, domcpus;
504 int cpuid, i, j, k, ncores;
506 if (mp_ncpus % smp_threads_per_core != 0) {
507 printf("%s: irregular SMP topology (%d threads, %d per core)\n",
508 __func__, mp_ncpus, smp_threads_per_core);
509 return (smp_topo_none());
512 root = smp_topo_alloc(1);
513 dom = cpu_group_init(root, NULL, &all_cpus, vm_ndomains, CG_SHARE_NONE,
517 * Redundant layers will be collapsed by the caller so we don't need a
518 * special case for a single domain.
520 for (i = 0; i < vm_ndomains; i++, dom++) {
521 CPU_COPY(&cpuset_domain[i], &domcpus);
522 ncores = CPU_COUNT(&domcpus) / smp_threads_per_core;
523 KASSERT(CPU_COUNT(&domcpus) % smp_threads_per_core == 0,
524 ("%s: domain %d core count not divisible by thread count",
527 core = cpu_group_init(dom, root, &domcpus, ncores, CG_SHARE_L3,
529 for (j = 0; j < ncores; j++, core++) {
531 * Assume that consecutive CPU IDs correspond to sibling
535 for (k = 0; k < smp_threads_per_core; k++) {
536 cpuid = CPU_FFS(&domcpus) - 1;
537 CPU_CLR(cpuid, &domcpus);
538 CPU_SET(cpuid, &corecpus);
540 (void)cpu_group_init(core, dom, &corecpus, 0,
541 CG_SHARE_L1, CG_FLAG_SMT);
551 powernv_reset(platform_t platform)
554 opal_call(OPAL_CEC_REBOOT);
558 powernv_smp_ap_init(platform_t platform)
561 if (powernv_smp_ap_extra_init != NULL)
562 powernv_smp_ap_extra_init();
566 powernv_cpu_idle(sbintime_t sbt)
571 powernv_node_numa_domain(platform_t platform, phandle_t node)
573 /* XXX: Is locking necessary in here? */
574 static int numa_domains[MAXMEMDOM];
575 static int numa_max_domain;
576 cell_t associativity[5];
583 TUNABLE_INT_FETCH("vm.numa.disabled", &i);
587 res = OF_getencprop(node, "ibm,associativity",
588 associativity, sizeof(associativity));
591 * If this node doesn't have associativity, or if there are not
592 * enough elements in it, check its parent.
594 if (res < (int)(sizeof(cell_t) * (platform_associativity + 1))) {
595 node = OF_parent(node);
596 /* If already at the root, use default domain. */
599 return (powernv_node_numa_domain(platform, node));
602 for (i = 0; i < numa_max_domain; i++) {
603 if (numa_domains[i] == associativity[platform_associativity])
607 numa_domains[numa_max_domain++] =
608 associativity[platform_associativity];
615 /* Set up the Nest MMU on POWER9 relatively early, but after pmap is setup. */
617 powernv_setup_nmmu(void *unused)
619 if (opal_check() != 0)
621 opal_call(OPAL_NMMU_SET_PTCR, -1, mfspr(SPR_PTCR));
624 SYSINIT(powernv_setup_nmmu, SI_SUB_CPU, SI_ORDER_ANY, powernv_setup_nmmu, NULL);