2 * Copyright (c) 2015 Nathan Whitehorn
3 * Copyright (c) 2017-2018 Semihalf
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
21 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
25 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 #include <sys/cdefs.h>
29 __FBSDID("$FreeBSD$");
31 #include <sys/param.h>
32 #include <sys/systm.h>
33 #include <sys/kernel.h>
41 #include <machine/bus.h>
42 #include <machine/cpu.h>
43 #include <machine/hid.h>
44 #include <machine/platformvar.h>
45 #include <machine/pmap.h>
46 #include <machine/rtas.h>
47 #include <machine/smp.h>
48 #include <machine/spr.h>
49 #include <machine/trap.h>
51 #include <dev/ofw/openfirm.h>
52 #include <machine/ofw_machdep.h>
53 #include <powerpc/aim/mmu_oea64.h>
55 #include "platform_if.h"
62 void (*powernv_smp_ap_extra_init)(void);
64 static int powernv_probe(platform_t);
65 static int powernv_attach(platform_t);
66 void powernv_mem_regions(platform_t, struct mem_region *phys, int *physsz,
67 struct mem_region *avail, int *availsz);
68 static u_long powernv_timebase_freq(platform_t, struct cpuref *cpuref);
69 static int powernv_smp_first_cpu(platform_t, struct cpuref *cpuref);
70 static int powernv_smp_next_cpu(platform_t, struct cpuref *cpuref);
71 static int powernv_smp_get_bsp(platform_t, struct cpuref *cpuref);
72 static void powernv_smp_ap_init(platform_t);
74 static int powernv_smp_start_cpu(platform_t, struct pcpu *cpu);
75 static void powernv_smp_probe_threads(platform_t);
76 static struct cpu_group *powernv_smp_topo(platform_t plat);
78 static void powernv_reset(platform_t);
79 static void powernv_cpu_idle(sbintime_t sbt);
80 static int powernv_cpuref_init(void);
82 static platform_method_t powernv_methods[] = {
83 PLATFORMMETHOD(platform_probe, powernv_probe),
84 PLATFORMMETHOD(platform_attach, powernv_attach),
85 PLATFORMMETHOD(platform_mem_regions, powernv_mem_regions),
86 PLATFORMMETHOD(platform_timebase_freq, powernv_timebase_freq),
88 PLATFORMMETHOD(platform_smp_ap_init, powernv_smp_ap_init),
89 PLATFORMMETHOD(platform_smp_first_cpu, powernv_smp_first_cpu),
90 PLATFORMMETHOD(platform_smp_next_cpu, powernv_smp_next_cpu),
91 PLATFORMMETHOD(platform_smp_get_bsp, powernv_smp_get_bsp),
93 PLATFORMMETHOD(platform_smp_start_cpu, powernv_smp_start_cpu),
94 PLATFORMMETHOD(platform_smp_probe_threads, powernv_smp_probe_threads),
95 PLATFORMMETHOD(platform_smp_topo, powernv_smp_topo),
98 PLATFORMMETHOD(platform_reset, powernv_reset),
103 static platform_def_t powernv_platform = {
109 static struct cpuref platform_cpuref[MAXCPU];
110 static int platform_cpuref_cnt;
111 static int platform_cpuref_valid;
113 PLATFORM_DEF(powernv_platform);
115 static uint64_t powernv_boot_pir;
118 powernv_probe(platform_t plat)
120 if (opal_check() == 0)
121 return (BUS_PROBE_SPECIFIC);
127 powernv_attach(platform_t plat)
129 uint32_t nptlp, shift = 0, slb_encoding = 0;
130 int32_t lp_size, lp_encoding;
137 /* Ping OPAL again just to make sure */
140 #if BYTE_ORDER == LITTLE_ENDIAN
141 opal_call(OPAL_REINIT_CPUS, 2 /* Little endian */);
143 opal_call(OPAL_REINIT_CPUS, 1 /* Big endian */);
146 if (cpu_idle_hook == NULL)
147 cpu_idle_hook = powernv_cpu_idle;
149 powernv_boot_pir = mfspr(SPR_PIR);
151 /* LPID must not be altered when PSL_DR or PSL_IR is set */
153 mtmsr(msr & ~(PSL_DR | PSL_IR));
155 /* Direct interrupts to SRR instead of HSRR and reset LPCR otherwise */
159 if (cpu_features2 & PPC_FEATURE2_ARCH_3_00)
162 mtspr(SPR_LPCR, lpcr);
167 powernv_cpuref_init();
169 /* Set SLB count from device tree */
173 res = OF_getprop(cpu, "name", buf, sizeof(buf));
174 if (res > 0 && strcmp(buf, "cpus") == 0)
183 res = OF_getprop(cpu, "device_type", buf, sizeof(buf));
184 if (res > 0 && strcmp(buf, "cpu") == 0)
191 res = OF_getencprop(cpu, "ibm,slb-size", &prop, sizeof(prop));
196 * Scan the large page size property for PAPR compatible machines.
197 * See PAPR D.5 Changes to Section 5.1.4, 'CPU Node Properties'
198 * for the encoding of the property.
201 len = OF_getproplen(cpu, "ibm,segment-page-sizes");
204 * We have to use a variable length array on the stack
205 * since we have very limited stack space.
207 pcell_t arr[len/sizeof(cell_t)];
208 res = OF_getencprop(cpu, "ibm,segment-page-sizes", arr,
214 slb_encoding = arr[idx + 1];
215 nptlp = arr[idx + 2];
218 while (len > 0 && nptlp) {
220 lp_encoding = arr[idx+1];
221 if (slb_encoding == SLBV_L && lp_encoding == 0)
228 if (nptlp && slb_encoding == SLBV_L && lp_encoding == 0)
233 panic("Standard large pages (SLB[L] = 1, PTE[LP] = 0) "
234 "not supported by this system.");
236 moea64_large_page_shift = shift;
237 moea64_large_page_size = 1ULL << lp_size;
246 powernv_mem_regions(platform_t plat, struct mem_region *phys, int *physsz,
247 struct mem_region *avail, int *availsz)
250 ofw_mem_regions(phys, physsz, avail, availsz);
254 powernv_timebase_freq(platform_t plat, struct cpuref *cpuref)
257 phandle_t cpu, dev, root;
262 dev = OF_child(root);
264 res = OF_getprop(dev, "name", buf, sizeof(buf));
265 if (res > 0 && strcmp(buf, "cpus") == 0)
270 for (cpu = OF_child(dev); cpu != 0; cpu = OF_peer(cpu)) {
271 res = OF_getprop(cpu, "device_type", buf, sizeof(buf));
272 if (res > 0 && strcmp(buf, "cpu") == 0)
278 OF_getencprop(cpu, "timebase-frequency", &ticks, sizeof(ticks));
281 panic("Unable to determine timebase frequency!");
288 powernv_cpuref_init(void)
292 int a, res, tmp_cpuref_cnt;
293 static struct cpuref tmp_cpuref[MAXCPU];
294 cell_t interrupt_servers[32];
297 if (platform_cpuref_valid)
303 res = OF_getprop(dev, "name", buf, sizeof(buf));
304 if (res > 0 && strcmp(buf, "cpus") == 0)
311 for (cpu = OF_child(dev); cpu != 0; cpu = OF_peer(cpu)) {
312 res = OF_getprop(cpu, "device_type", buf, sizeof(buf));
313 if (res > 0 && strcmp(buf, "cpu") == 0) {
314 res = OF_getproplen(cpu, "ibm,ppc-interrupt-server#s");
318 OF_getencprop(cpu, "ibm,ppc-interrupt-server#s",
319 interrupt_servers, res);
321 for (a = 0; a < res/sizeof(cell_t); a++) {
322 tmp_cpuref[tmp_cpuref_cnt].cr_hwref = interrupt_servers[a];
323 tmp_cpuref[tmp_cpuref_cnt].cr_cpuid = tmp_cpuref_cnt;
325 if (interrupt_servers[a] == (uint32_t)powernv_boot_pir)
326 bsp = tmp_cpuref_cnt;
334 /* Map IDs, so BSP has CPUID 0 regardless of hwref */
335 for (a = bsp; a < tmp_cpuref_cnt; a++) {
336 platform_cpuref[platform_cpuref_cnt].cr_hwref = tmp_cpuref[a].cr_hwref;
337 platform_cpuref[platform_cpuref_cnt].cr_cpuid = platform_cpuref_cnt;
338 platform_cpuref_cnt++;
340 for (a = 0; a < bsp; a++) {
341 platform_cpuref[platform_cpuref_cnt].cr_hwref = tmp_cpuref[a].cr_hwref;
342 platform_cpuref[platform_cpuref_cnt].cr_cpuid = platform_cpuref_cnt;
343 platform_cpuref_cnt++;
346 platform_cpuref_valid = 1;
352 powernv_smp_first_cpu(platform_t plat, struct cpuref *cpuref)
354 if (platform_cpuref_valid == 0)
357 cpuref->cr_cpuid = 0;
358 cpuref->cr_hwref = platform_cpuref[0].cr_hwref;
364 powernv_smp_next_cpu(platform_t plat, struct cpuref *cpuref)
368 if (platform_cpuref_valid == 0)
371 id = cpuref->cr_cpuid + 1;
372 if (id >= platform_cpuref_cnt)
375 cpuref->cr_cpuid = platform_cpuref[id].cr_cpuid;
376 cpuref->cr_hwref = platform_cpuref[id].cr_hwref;
382 powernv_smp_get_bsp(platform_t plat, struct cpuref *cpuref)
385 cpuref->cr_cpuid = platform_cpuref[0].cr_cpuid;
386 cpuref->cr_hwref = platform_cpuref[0].cr_hwref;
392 powernv_smp_start_cpu(platform_t plat, struct pcpu *pc)
399 result = opal_call(OPAL_START_CPU, pc->pc_hwref, EXC_RST);
400 if (result != OPAL_SUCCESS) {
401 printf("OPAL error (%d): unable to start AP %d\n",
402 result, (int)pc->pc_hwref);
410 powernv_smp_probe_threads(platform_t plat)
413 phandle_t cpu, dev, root;
418 dev = OF_child(root);
420 res = OF_getprop(dev, "name", buf, sizeof(buf));
421 if (res > 0 && strcmp(buf, "cpus") == 0)
427 for (cpu = OF_child(dev); cpu != 0; cpu = OF_peer(cpu)) {
428 res = OF_getprop(cpu, "device_type", buf, sizeof(buf));
429 if (res <= 0 || strcmp(buf, "cpu") != 0)
432 res = OF_getproplen(cpu, "ibm,ppc-interrupt-server#s");
435 nthreads = res / sizeof(cell_t);
441 smp_threads_per_core = nthreads;
442 if (mp_ncpus % nthreads == 0)
443 mp_ncores = mp_ncpus / nthreads;
446 static struct cpu_group *
447 powernv_smp_topo(platform_t plat)
449 if (mp_ncpus % smp_threads_per_core != 0) {
450 printf("WARNING: Irregular SMP topology. Performance may be "
451 "suboptimal (%d threads, %d on first core)\n",
452 mp_ncpus, smp_threads_per_core);
453 return (smp_topo_none());
456 /* Don't do anything fancier for non-threaded SMP */
457 if (smp_threads_per_core == 1)
458 return (smp_topo_none());
460 return (smp_topo_1level(CG_SHARE_L1, smp_threads_per_core,
467 powernv_reset(platform_t platform)
470 opal_call(OPAL_CEC_REBOOT);
474 powernv_smp_ap_init(platform_t platform)
477 if (powernv_smp_ap_extra_init != NULL)
478 powernv_smp_ap_extra_init();
482 powernv_cpu_idle(sbintime_t sbt)