2 * Copyright (c) 2015 Nathan Whitehorn
3 * Copyright (c) 2017-2018 Semihalf
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
21 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
25 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 #include <sys/cdefs.h>
29 __FBSDID("$FreeBSD$");
31 #include <sys/param.h>
32 #include <sys/systm.h>
33 #include <sys/kernel.h>
41 #include <machine/bus.h>
42 #include <machine/cpu.h>
43 #include <machine/hid.h>
44 #include <machine/platformvar.h>
45 #include <machine/pmap.h>
46 #include <machine/rtas.h>
47 #include <machine/smp.h>
48 #include <machine/spr.h>
49 #include <machine/trap.h>
51 #include <dev/ofw/openfirm.h>
52 #include <machine/ofw_machdep.h>
53 #include <powerpc/aim/mmu_oea64.h>
55 #include "platform_if.h"
62 extern void xicp_smp_cpu_startup(void);
63 static int powernv_probe(platform_t);
64 static int powernv_attach(platform_t);
65 void powernv_mem_regions(platform_t, struct mem_region *phys, int *physsz,
66 struct mem_region *avail, int *availsz);
67 static u_long powernv_timebase_freq(platform_t, struct cpuref *cpuref);
68 static int powernv_smp_first_cpu(platform_t, struct cpuref *cpuref);
69 static int powernv_smp_next_cpu(platform_t, struct cpuref *cpuref);
70 static int powernv_smp_get_bsp(platform_t, struct cpuref *cpuref);
71 static void powernv_smp_ap_init(platform_t);
73 static int powernv_smp_start_cpu(platform_t, struct pcpu *cpu);
74 static void powernv_smp_probe_threads(platform_t);
75 static struct cpu_group *powernv_smp_topo(platform_t plat);
77 static void powernv_reset(platform_t);
78 static void powernv_cpu_idle(sbintime_t sbt);
79 static int powernv_cpuref_init(void);
81 static platform_method_t powernv_methods[] = {
82 PLATFORMMETHOD(platform_probe, powernv_probe),
83 PLATFORMMETHOD(platform_attach, powernv_attach),
84 PLATFORMMETHOD(platform_mem_regions, powernv_mem_regions),
85 PLATFORMMETHOD(platform_timebase_freq, powernv_timebase_freq),
87 PLATFORMMETHOD(platform_smp_ap_init, powernv_smp_ap_init),
88 PLATFORMMETHOD(platform_smp_first_cpu, powernv_smp_first_cpu),
89 PLATFORMMETHOD(platform_smp_next_cpu, powernv_smp_next_cpu),
90 PLATFORMMETHOD(platform_smp_get_bsp, powernv_smp_get_bsp),
92 PLATFORMMETHOD(platform_smp_start_cpu, powernv_smp_start_cpu),
93 PLATFORMMETHOD(platform_smp_probe_threads, powernv_smp_probe_threads),
94 PLATFORMMETHOD(platform_smp_topo, powernv_smp_topo),
97 PLATFORMMETHOD(platform_reset, powernv_reset),
102 static platform_def_t powernv_platform = {
108 static struct cpuref platform_cpuref[MAXCPU];
109 static int platform_cpuref_cnt;
110 static int platform_cpuref_valid;
112 PLATFORM_DEF(powernv_platform);
114 static uint64_t powernv_boot_pir;
117 powernv_probe(platform_t plat)
119 if (opal_check() == 0)
120 return (BUS_PROBE_SPECIFIC);
126 powernv_attach(platform_t plat)
128 uint32_t nptlp, shift = 0, slb_encoding = 0;
129 int32_t lp_size, lp_encoding;
136 /* Ping OPAL again just to make sure */
139 #if BYTE_ORDER == LITTLE_ENDIAN
140 opal_call(OPAL_REINIT_CPUS, 2 /* Little endian */);
142 opal_call(OPAL_REINIT_CPUS, 1 /* Big endian */);
145 if (cpu_idle_hook == NULL)
146 cpu_idle_hook = powernv_cpu_idle;
148 powernv_boot_pir = mfspr(SPR_PIR);
150 /* LPID must not be altered when PSL_DR or PSL_IR is set */
152 mtmsr(msr & ~(PSL_DR | PSL_IR));
154 /* Direct interrupts to SRR instead of HSRR and reset LPCR otherwise */
158 if (cpu_features2 & PPC_FEATURE2_ARCH_3_00)
161 mtspr(SPR_LPCR, lpcr);
166 powernv_cpuref_init();
168 /* Set SLB count from device tree */
172 res = OF_getprop(cpu, "name", buf, sizeof(buf));
173 if (res > 0 && strcmp(buf, "cpus") == 0)
182 res = OF_getprop(cpu, "device_type", buf, sizeof(buf));
183 if (res > 0 && strcmp(buf, "cpu") == 0)
190 res = OF_getencprop(cpu, "ibm,slb-size", &prop, sizeof(prop));
195 * Scan the large page size property for PAPR compatible machines.
196 * See PAPR D.5 Changes to Section 5.1.4, 'CPU Node Properties'
197 * for the encoding of the property.
200 len = OF_getproplen(cpu, "ibm,segment-page-sizes");
203 * We have to use a variable length array on the stack
204 * since we have very limited stack space.
206 pcell_t arr[len/sizeof(cell_t)];
207 res = OF_getencprop(cpu, "ibm,segment-page-sizes", arr,
213 slb_encoding = arr[idx + 1];
214 nptlp = arr[idx + 2];
217 while (len > 0 && nptlp) {
219 lp_encoding = arr[idx+1];
220 if (slb_encoding == SLBV_L && lp_encoding == 0)
227 if (nptlp && slb_encoding == SLBV_L && lp_encoding == 0)
232 panic("Standard large pages (SLB[L] = 1, PTE[LP] = 0) "
233 "not supported by this system.");
235 moea64_large_page_shift = shift;
236 moea64_large_page_size = 1ULL << lp_size;
245 powernv_mem_regions(platform_t plat, struct mem_region *phys, int *physsz,
246 struct mem_region *avail, int *availsz)
249 ofw_mem_regions(phys, physsz, avail, availsz);
253 powernv_timebase_freq(platform_t plat, struct cpuref *cpuref)
256 phandle_t cpu, dev, root;
261 dev = OF_child(root);
263 res = OF_getprop(dev, "name", buf, sizeof(buf));
264 if (res > 0 && strcmp(buf, "cpus") == 0)
269 for (cpu = OF_child(dev); cpu != 0; cpu = OF_peer(cpu)) {
270 res = OF_getprop(cpu, "device_type", buf, sizeof(buf));
271 if (res > 0 && strcmp(buf, "cpu") == 0)
277 OF_getencprop(cpu, "timebase-frequency", &ticks, sizeof(ticks));
280 panic("Unable to determine timebase frequency!");
287 powernv_cpuref_init(void)
291 int a, res, tmp_cpuref_cnt;
292 static struct cpuref tmp_cpuref[MAXCPU];
293 cell_t interrupt_servers[32];
296 if (platform_cpuref_valid)
302 res = OF_getprop(dev, "name", buf, sizeof(buf));
303 if (res > 0 && strcmp(buf, "cpus") == 0)
310 for (cpu = OF_child(dev); cpu != 0; cpu = OF_peer(cpu)) {
311 res = OF_getprop(cpu, "device_type", buf, sizeof(buf));
312 if (res > 0 && strcmp(buf, "cpu") == 0) {
313 res = OF_getproplen(cpu, "ibm,ppc-interrupt-server#s");
317 OF_getencprop(cpu, "ibm,ppc-interrupt-server#s",
318 interrupt_servers, res);
320 for (a = 0; a < res/sizeof(cell_t); a++) {
321 tmp_cpuref[tmp_cpuref_cnt].cr_hwref = interrupt_servers[a];
322 tmp_cpuref[tmp_cpuref_cnt].cr_cpuid = tmp_cpuref_cnt;
324 if (interrupt_servers[a] == (uint32_t)powernv_boot_pir)
325 bsp = tmp_cpuref_cnt;
333 /* Map IDs, so BSP has CPUID 0 regardless of hwref */
334 for (a = bsp; a < tmp_cpuref_cnt; a++) {
335 platform_cpuref[platform_cpuref_cnt].cr_hwref = tmp_cpuref[a].cr_hwref;
336 platform_cpuref[platform_cpuref_cnt].cr_cpuid = platform_cpuref_cnt;
337 platform_cpuref_cnt++;
339 for (a = 0; a < bsp; a++) {
340 platform_cpuref[platform_cpuref_cnt].cr_hwref = tmp_cpuref[a].cr_hwref;
341 platform_cpuref[platform_cpuref_cnt].cr_cpuid = platform_cpuref_cnt;
342 platform_cpuref_cnt++;
345 platform_cpuref_valid = 1;
351 powernv_smp_first_cpu(platform_t plat, struct cpuref *cpuref)
353 if (platform_cpuref_valid == 0)
356 cpuref->cr_cpuid = 0;
357 cpuref->cr_hwref = platform_cpuref[0].cr_hwref;
363 powernv_smp_next_cpu(platform_t plat, struct cpuref *cpuref)
367 if (platform_cpuref_valid == 0)
370 id = cpuref->cr_cpuid + 1;
371 if (id >= platform_cpuref_cnt)
374 cpuref->cr_cpuid = platform_cpuref[id].cr_cpuid;
375 cpuref->cr_hwref = platform_cpuref[id].cr_hwref;
381 powernv_smp_get_bsp(platform_t plat, struct cpuref *cpuref)
384 cpuref->cr_cpuid = platform_cpuref[0].cr_cpuid;
385 cpuref->cr_hwref = platform_cpuref[0].cr_hwref;
391 powernv_smp_start_cpu(platform_t plat, struct pcpu *pc)
398 result = opal_call(OPAL_START_CPU, pc->pc_hwref, EXC_RST);
399 if (result != OPAL_SUCCESS) {
400 printf("OPAL error (%d): unable to start AP %d\n",
401 result, (int)pc->pc_hwref);
409 powernv_smp_probe_threads(platform_t plat)
412 phandle_t cpu, dev, root;
417 dev = OF_child(root);
419 res = OF_getprop(dev, "name", buf, sizeof(buf));
420 if (res > 0 && strcmp(buf, "cpus") == 0)
426 for (cpu = OF_child(dev); cpu != 0; cpu = OF_peer(cpu)) {
427 res = OF_getprop(cpu, "device_type", buf, sizeof(buf));
428 if (res <= 0 || strcmp(buf, "cpu") != 0)
431 res = OF_getproplen(cpu, "ibm,ppc-interrupt-server#s");
434 nthreads = res / sizeof(cell_t);
440 smp_threads_per_core = nthreads;
441 if (mp_ncpus % nthreads == 0)
442 mp_ncores = mp_ncpus / nthreads;
445 static struct cpu_group *
446 powernv_smp_topo(platform_t plat)
448 if (mp_ncpus % smp_threads_per_core != 0) {
449 printf("WARNING: Irregular SMP topology. Performance may be "
450 "suboptimal (%d threads, %d on first core)\n",
451 mp_ncpus, smp_threads_per_core);
452 return (smp_topo_none());
455 /* Don't do anything fancier for non-threaded SMP */
456 if (smp_threads_per_core == 1)
457 return (smp_topo_none());
459 return (smp_topo_1level(CG_SHARE_L1, smp_threads_per_core,
466 powernv_reset(platform_t platform)
469 opal_call(OPAL_CEC_REBOOT);
473 powernv_smp_ap_init(platform_t platform)
476 xicp_smp_cpu_startup();
480 powernv_cpu_idle(sbintime_t sbt)