2 * Copyright (c) 2015 Nathan Whitehorn
3 * Copyright (c) 2017-2018 Semihalf
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
21 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
25 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 #include <sys/cdefs.h>
29 __FBSDID("$FreeBSD$");
31 #include <sys/param.h>
32 #include <sys/systm.h>
33 #include <sys/kernel.h>
41 #include <machine/bus.h>
42 #include <machine/cpu.h>
43 #include <machine/hid.h>
44 #include <machine/platformvar.h>
45 #include <machine/pmap.h>
46 #include <machine/rtas.h>
47 #include <machine/smp.h>
48 #include <machine/spr.h>
49 #include <machine/trap.h>
51 #include <dev/ofw/openfirm.h>
52 #include <machine/ofw_machdep.h>
53 #include <powerpc/aim/mmu_oea64.h>
55 #include "platform_if.h"
62 extern void xicp_smp_cpu_startup(void);
63 static int powernv_probe(platform_t);
64 static int powernv_attach(platform_t);
65 void powernv_mem_regions(platform_t, struct mem_region *phys, int *physsz,
66 struct mem_region *avail, int *availsz);
67 static u_long powernv_timebase_freq(platform_t, struct cpuref *cpuref);
68 static int powernv_smp_first_cpu(platform_t, struct cpuref *cpuref);
69 static int powernv_smp_next_cpu(platform_t, struct cpuref *cpuref);
70 static int powernv_smp_get_bsp(platform_t, struct cpuref *cpuref);
71 static void powernv_smp_ap_init(platform_t);
73 static int powernv_smp_start_cpu(platform_t, struct pcpu *cpu);
74 static struct cpu_group *powernv_smp_topo(platform_t plat);
76 static void powernv_reset(platform_t);
77 static void powernv_cpu_idle(sbintime_t sbt);
78 static int powernv_cpuref_init(void);
80 static platform_method_t powernv_methods[] = {
81 PLATFORMMETHOD(platform_probe, powernv_probe),
82 PLATFORMMETHOD(platform_attach, powernv_attach),
83 PLATFORMMETHOD(platform_mem_regions, powernv_mem_regions),
84 PLATFORMMETHOD(platform_timebase_freq, powernv_timebase_freq),
86 PLATFORMMETHOD(platform_smp_ap_init, powernv_smp_ap_init),
87 PLATFORMMETHOD(platform_smp_first_cpu, powernv_smp_first_cpu),
88 PLATFORMMETHOD(platform_smp_next_cpu, powernv_smp_next_cpu),
89 PLATFORMMETHOD(platform_smp_get_bsp, powernv_smp_get_bsp),
91 PLATFORMMETHOD(platform_smp_start_cpu, powernv_smp_start_cpu),
92 PLATFORMMETHOD(platform_smp_topo, powernv_smp_topo),
95 PLATFORMMETHOD(platform_reset, powernv_reset),
100 static platform_def_t powernv_platform = {
106 static struct cpuref platform_cpuref[MAXCPU];
107 static int platform_cpuref_cnt;
108 static int platform_cpuref_valid;
110 PLATFORM_DEF(powernv_platform);
112 static uint64_t powernv_boot_pir;
115 powernv_probe(platform_t plat)
117 if (opal_check() == 0)
118 return (BUS_PROBE_SPECIFIC);
124 powernv_attach(platform_t plat)
126 uint32_t nptlp, shift = 0, slb_encoding = 0;
127 int32_t lp_size, lp_encoding;
134 /* Ping OPAL again just to make sure */
137 #if BYTE_ORDER == LITTLE_ENDIAN
138 opal_call(OPAL_REINIT_CPUS, 2 /* Little endian */);
140 opal_call(OPAL_REINIT_CPUS, 1 /* Big endian */);
143 if (cpu_idle_hook == NULL)
144 cpu_idle_hook = powernv_cpu_idle;
146 powernv_boot_pir = mfspr(SPR_PIR);
148 /* LPID must not be altered when PSL_DR or PSL_IR is set */
150 mtmsr(msr & ~(PSL_DR | PSL_IR));
152 /* Direct interrupts to SRR instead of HSRR and reset LPCR otherwise */
156 if (cpu_features2 & PPC_FEATURE2_ARCH_3_00)
159 mtspr(SPR_LPCR, lpcr);
164 powernv_cpuref_init();
166 /* Set SLB count from device tree */
170 res = OF_getprop(cpu, "name", buf, sizeof(buf));
171 if (res > 0 && strcmp(buf, "cpus") == 0)
180 res = OF_getprop(cpu, "device_type", buf, sizeof(buf));
181 if (res > 0 && strcmp(buf, "cpu") == 0)
188 res = OF_getencprop(cpu, "ibm,slb-size", &prop, sizeof(prop));
193 * Scan the large page size property for PAPR compatible machines.
194 * See PAPR D.5 Changes to Section 5.1.4, 'CPU Node Properties'
195 * for the encoding of the property.
198 len = OF_getproplen(cpu, "ibm,segment-page-sizes");
201 * We have to use a variable length array on the stack
202 * since we have very limited stack space.
204 pcell_t arr[len/sizeof(cell_t)];
205 res = OF_getencprop(cpu, "ibm,segment-page-sizes", arr,
211 slb_encoding = arr[idx + 1];
212 nptlp = arr[idx + 2];
215 while (len > 0 && nptlp) {
217 lp_encoding = arr[idx+1];
218 if (slb_encoding == SLBV_L && lp_encoding == 0)
225 if (nptlp && slb_encoding == SLBV_L && lp_encoding == 0)
230 panic("Standard large pages (SLB[L] = 1, PTE[LP] = 0) "
231 "not supported by this system.");
233 moea64_large_page_shift = shift;
234 moea64_large_page_size = 1ULL << lp_size;
243 powernv_mem_regions(platform_t plat, struct mem_region *phys, int *physsz,
244 struct mem_region *avail, int *availsz)
247 ofw_mem_regions(phys, physsz, avail, availsz);
251 powernv_timebase_freq(platform_t plat, struct cpuref *cpuref)
254 phandle_t cpu, dev, root;
259 dev = OF_child(root);
261 res = OF_getprop(dev, "name", buf, sizeof(buf));
262 if (res > 0 && strcmp(buf, "cpus") == 0)
267 for (cpu = OF_child(dev); cpu != 0; cpu = OF_peer(cpu)) {
268 res = OF_getprop(cpu, "device_type", buf, sizeof(buf));
269 if (res > 0 && strcmp(buf, "cpu") == 0)
275 OF_getencprop(cpu, "timebase-frequency", &ticks, sizeof(ticks));
278 panic("Unable to determine timebase frequency!");
285 powernv_cpuref_init(void)
289 int a, res, tmp_cpuref_cnt;
290 static struct cpuref tmp_cpuref[MAXCPU];
291 cell_t interrupt_servers[32];
294 if (platform_cpuref_valid)
300 res = OF_getprop(dev, "name", buf, sizeof(buf));
301 if (res > 0 && strcmp(buf, "cpus") == 0)
308 for (cpu = OF_child(dev); cpu != 0; cpu = OF_peer(cpu)) {
309 res = OF_getprop(cpu, "device_type", buf, sizeof(buf));
310 if (res > 0 && strcmp(buf, "cpu") == 0) {
311 res = OF_getproplen(cpu, "ibm,ppc-interrupt-server#s");
315 OF_getencprop(cpu, "ibm,ppc-interrupt-server#s",
316 interrupt_servers, res);
318 for (a = 0; a < res/sizeof(cell_t); a++) {
319 tmp_cpuref[tmp_cpuref_cnt].cr_hwref = interrupt_servers[a];
320 tmp_cpuref[tmp_cpuref_cnt].cr_cpuid = tmp_cpuref_cnt;
322 if (interrupt_servers[a] == (uint32_t)powernv_boot_pir)
323 bsp = tmp_cpuref_cnt;
331 /* Map IDs, so BSP has CPUID 0 regardless of hwref */
332 for (a = bsp; a < tmp_cpuref_cnt; a++) {
333 platform_cpuref[platform_cpuref_cnt].cr_hwref = tmp_cpuref[a].cr_hwref;
334 platform_cpuref[platform_cpuref_cnt].cr_cpuid = platform_cpuref_cnt;
335 platform_cpuref_cnt++;
337 for (a = 0; a < bsp; a++) {
338 platform_cpuref[platform_cpuref_cnt].cr_hwref = tmp_cpuref[a].cr_hwref;
339 platform_cpuref[platform_cpuref_cnt].cr_cpuid = platform_cpuref_cnt;
340 platform_cpuref_cnt++;
343 platform_cpuref_valid = 1;
349 powernv_smp_first_cpu(platform_t plat, struct cpuref *cpuref)
351 if (platform_cpuref_valid == 0)
354 cpuref->cr_cpuid = 0;
355 cpuref->cr_hwref = platform_cpuref[0].cr_hwref;
361 powernv_smp_next_cpu(platform_t plat, struct cpuref *cpuref)
365 if (platform_cpuref_valid == 0)
368 id = cpuref->cr_cpuid + 1;
369 if (id >= platform_cpuref_cnt)
372 cpuref->cr_cpuid = platform_cpuref[id].cr_cpuid;
373 cpuref->cr_hwref = platform_cpuref[id].cr_hwref;
379 powernv_smp_get_bsp(platform_t plat, struct cpuref *cpuref)
382 cpuref->cr_cpuid = platform_cpuref[0].cr_cpuid;
383 cpuref->cr_hwref = platform_cpuref[0].cr_hwref;
389 powernv_smp_start_cpu(platform_t plat, struct pcpu *pc)
396 result = opal_call(OPAL_START_CPU, pc->pc_hwref, EXC_RST);
397 if (result != OPAL_SUCCESS) {
398 printf("OPAL error (%d): unable to start AP %d\n",
399 result, (int)pc->pc_hwref);
406 static struct cpu_group *
407 powernv_smp_topo(platform_t plat)
410 phandle_t cpu, dev, root;
415 dev = OF_child(root);
417 res = OF_getprop(dev, "name", buf, sizeof(buf));
418 if (res > 0 && strcmp(buf, "cpus") == 0)
424 for (cpu = OF_child(dev); cpu != 0; cpu = OF_peer(cpu)) {
425 res = OF_getprop(cpu, "device_type", buf, sizeof(buf));
426 if (res <= 0 || strcmp(buf, "cpu") != 0)
429 res = OF_getproplen(cpu, "ibm,ppc-interrupt-server#s");
432 nthreads = res / sizeof(cell_t);
438 if (mp_ncpus % nthreads != 0) {
439 printf("WARNING: Irregular SMP topology. Performance may be "
440 "suboptimal (%d threads, %d on first core)\n",
442 return (smp_topo_none());
445 /* Don't do anything fancier for non-threaded SMP */
447 return (smp_topo_none());
449 return (smp_topo_1level(CG_SHARE_L1, nthreads, CG_FLAG_SMT));
455 powernv_reset(platform_t platform)
458 opal_call(OPAL_CEC_REBOOT);
462 powernv_smp_ap_init(platform_t platform)
465 xicp_smp_cpu_startup();
469 powernv_cpu_idle(sbintime_t sbt)