2 * SPDX-License-Identifier: BSD-4-Clause AND BSD-2-Clause-FreeBSD
4 * Copyright (c) 2001 Matt Thomas.
5 * Copyright (c) 2001 Tsubai Masanari.
6 * Copyright (c) 1998, 1999, 2001 Internet Research Institute, Inc.
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 * 3. All advertising materials mentioning features or use of this software
18 * must display the following acknowledgement:
19 * This product includes software developed by
20 * Internet Research Institute, Inc.
21 * 4. The name of the author may not be used to endorse or promote products
22 * derived from this software without specific prior written permission.
24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
25 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
26 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
27 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
28 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
29 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
30 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
31 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
32 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 * Copyright (C) 2003 Benno Rice.
37 * All rights reserved.
39 * Redistribution and use in source and binary forms, with or without
40 * modification, are permitted provided that the following conditions
42 * 1. Redistributions of source code must retain the above copyright
43 * notice, this list of conditions and the following disclaimer.
44 * 2. Redistributions in binary form must reproduce the above copyright
45 * notice, this list of conditions and the following disclaimer in the
46 * documentation and/or other materials provided with the distribution.
48 * THIS SOFTWARE IS PROVIDED BY Benno Rice ``AS IS'' AND ANY EXPRESS OR
49 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
50 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
51 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
52 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
53 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
54 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
55 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
56 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
57 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
59 * from $NetBSD: cpu_subr.c,v 1.1 2003/02/03 17:10:09 matt Exp $
63 #include <sys/param.h>
64 #include <sys/systm.h>
68 #include <sys/kernel.h>
72 #include <sys/sysctl.h>
73 #include <sys/sched.h>
76 #include <machine/bus.h>
77 #include <machine/cpu.h>
78 #include <machine/hid.h>
79 #include <machine/md_var.h>
80 #include <machine/smp.h>
81 #include <machine/spr.h>
83 #include <dev/ofw/openfirm.h>
85 static void cpu_6xx_setup(int cpuid, uint16_t vers);
86 static void cpu_970_setup(int cpuid, uint16_t vers);
87 static void cpu_booke_setup(int cpuid, uint16_t vers);
88 static void cpu_powerx_setup(int cpuid, uint16_t vers);
90 int powerpc_pow_enabled;
91 void (*cpu_idle_hook)(sbintime_t) = NULL;
92 static void cpu_idle_60x(sbintime_t);
93 static void cpu_idle_booke(sbintime_t);
95 static void cpu_idle_e500mc(sbintime_t sbt);
97 #if defined(__powerpc64__) && defined(AIM)
98 static void cpu_idle_powerx(sbintime_t);
99 static void cpu_idle_power9(sbintime_t);
106 int features; /* Do not include PPC_FEATURE_32 or
107 * PPC_FEATURE_HAS_MMU */
109 void (*cpu_setup)(int cpuid, uint16_t vers);
111 #define REVFMT_MAJMIN 1 /* %u.%u */
112 #define REVFMT_HEX 2 /* 0x%04x */
113 #define REVFMT_DEC 3 /* %u */
114 static const struct cputab models[] = {
115 { "Motorola PowerPC 601", MPC601, REVFMT_DEC,
116 PPC_FEATURE_HAS_FPU | PPC_FEATURE_UNIFIED_CACHE, 0, cpu_6xx_setup },
117 { "Motorola PowerPC 602", MPC602, REVFMT_DEC,
118 PPC_FEATURE_HAS_FPU, 0, cpu_6xx_setup },
119 { "Motorola PowerPC 603", MPC603, REVFMT_MAJMIN,
120 PPC_FEATURE_HAS_FPU, 0, cpu_6xx_setup },
121 { "Motorola PowerPC 603e", MPC603e, REVFMT_MAJMIN,
122 PPC_FEATURE_HAS_FPU, 0, cpu_6xx_setup },
123 { "Motorola PowerPC 603ev", MPC603ev, REVFMT_MAJMIN,
124 PPC_FEATURE_HAS_FPU, 0, cpu_6xx_setup },
125 { "Motorola PowerPC 604", MPC604, REVFMT_MAJMIN,
126 PPC_FEATURE_HAS_FPU, 0, cpu_6xx_setup },
127 { "Motorola PowerPC 604ev", MPC604ev, REVFMT_MAJMIN,
128 PPC_FEATURE_HAS_FPU, 0, cpu_6xx_setup },
129 { "Motorola PowerPC 620", MPC620, REVFMT_HEX,
130 PPC_FEATURE_64 | PPC_FEATURE_HAS_FPU, 0, NULL },
131 { "Motorola PowerPC 750", MPC750, REVFMT_MAJMIN,
132 PPC_FEATURE_HAS_FPU, 0, cpu_6xx_setup },
133 { "IBM PowerPC 750FX", IBM750FX, REVFMT_MAJMIN,
134 PPC_FEATURE_HAS_FPU, 0, cpu_6xx_setup },
135 { "IBM PowerPC 970", IBM970, REVFMT_MAJMIN,
136 PPC_FEATURE_64 | PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU,
138 { "IBM PowerPC 970FX", IBM970FX, REVFMT_MAJMIN,
139 PPC_FEATURE_64 | PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU,
141 { "IBM PowerPC 970GX", IBM970GX, REVFMT_MAJMIN,
142 PPC_FEATURE_64 | PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU,
144 { "IBM PowerPC 970MP", IBM970MP, REVFMT_MAJMIN,
145 PPC_FEATURE_64 | PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU,
147 { "IBM POWER4", IBMPOWER4, REVFMT_MAJMIN,
148 PPC_FEATURE_64 | PPC_FEATURE_HAS_FPU | PPC_FEATURE_POWER4, 0, NULL },
149 { "IBM POWER4+", IBMPOWER4PLUS, REVFMT_MAJMIN,
150 PPC_FEATURE_64 | PPC_FEATURE_HAS_FPU | PPC_FEATURE_POWER4, 0, NULL },
151 { "IBM POWER5", IBMPOWER5, REVFMT_MAJMIN,
152 PPC_FEATURE_64 | PPC_FEATURE_HAS_FPU | PPC_FEATURE_POWER4 |
153 PPC_FEATURE_SMT | PPC_FEATURE_ICACHE_SNOOP, 0, NULL },
154 { "IBM POWER5+", IBMPOWER5PLUS, REVFMT_MAJMIN,
155 PPC_FEATURE_64 | PPC_FEATURE_HAS_FPU | PPC_FEATURE_POWER5_PLUS |
156 PPC_FEATURE_SMT | PPC_FEATURE_ICACHE_SNOOP, 0, NULL },
157 { "IBM POWER6", IBMPOWER6, REVFMT_MAJMIN,
158 PPC_FEATURE_64 | PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU |
159 PPC_FEATURE_SMT | PPC_FEATURE_ICACHE_SNOOP | PPC_FEATURE_ARCH_2_05 |
160 PPC_FEATURE_TRUE_LE, 0, NULL },
161 { "IBM POWER7", IBMPOWER7, REVFMT_MAJMIN,
162 PPC_FEATURE_64 | PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU |
163 PPC_FEATURE_SMT | PPC_FEATURE_ARCH_2_05 | PPC_FEATURE_ARCH_2_06 |
164 PPC_FEATURE_HAS_VSX | PPC_FEATURE_TRUE_LE, PPC_FEATURE2_DSCR, NULL },
165 { "IBM POWER7+", IBMPOWER7PLUS, REVFMT_MAJMIN,
166 PPC_FEATURE_64 | PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU |
167 PPC_FEATURE_SMT | PPC_FEATURE_ARCH_2_05 | PPC_FEATURE_ARCH_2_06 |
168 PPC_FEATURE_HAS_VSX, PPC_FEATURE2_DSCR, NULL },
169 { "IBM POWER8E", IBMPOWER8E, REVFMT_MAJMIN,
170 PPC_FEATURE_64 | PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU |
171 PPC_FEATURE_SMT | PPC_FEATURE_ICACHE_SNOOP | PPC_FEATURE_ARCH_2_05 |
172 PPC_FEATURE_ARCH_2_06 | PPC_FEATURE_HAS_VSX | PPC_FEATURE_TRUE_LE,
173 PPC_FEATURE2_ARCH_2_07 | PPC_FEATURE2_HTM | PPC_FEATURE2_DSCR |
174 PPC_FEATURE2_ISEL | PPC_FEATURE2_TAR | PPC_FEATURE2_HAS_VEC_CRYPTO |
175 PPC_FEATURE2_HTM_NOSC, cpu_powerx_setup },
176 { "IBM POWER8NVL", IBMPOWER8NVL, REVFMT_MAJMIN,
177 PPC_FEATURE_64 | PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU |
178 PPC_FEATURE_SMT | PPC_FEATURE_ICACHE_SNOOP | PPC_FEATURE_ARCH_2_05 |
179 PPC_FEATURE_ARCH_2_06 | PPC_FEATURE_HAS_VSX | PPC_FEATURE_TRUE_LE,
180 PPC_FEATURE2_ARCH_2_07 | PPC_FEATURE2_HTM | PPC_FEATURE2_DSCR |
181 PPC_FEATURE2_ISEL | PPC_FEATURE2_TAR | PPC_FEATURE2_HAS_VEC_CRYPTO |
182 PPC_FEATURE2_HTM_NOSC, cpu_powerx_setup },
183 { "IBM POWER8", IBMPOWER8, REVFMT_MAJMIN,
184 PPC_FEATURE_64 | PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU |
185 PPC_FEATURE_SMT | PPC_FEATURE_ICACHE_SNOOP | PPC_FEATURE_ARCH_2_05 |
186 PPC_FEATURE_ARCH_2_06 | PPC_FEATURE_HAS_VSX | PPC_FEATURE_TRUE_LE,
187 PPC_FEATURE2_ARCH_2_07 | PPC_FEATURE2_HTM | PPC_FEATURE2_DSCR |
188 PPC_FEATURE2_ISEL | PPC_FEATURE2_TAR | PPC_FEATURE2_HAS_VEC_CRYPTO |
189 PPC_FEATURE2_HTM_NOSC, cpu_powerx_setup },
190 { "IBM POWER9", IBMPOWER9, REVFMT_MAJMIN,
191 PPC_FEATURE_64 | PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU |
192 PPC_FEATURE_SMT | PPC_FEATURE_ICACHE_SNOOP | PPC_FEATURE_ARCH_2_05 |
193 PPC_FEATURE_ARCH_2_06 | PPC_FEATURE_HAS_VSX | PPC_FEATURE_TRUE_LE,
194 PPC_FEATURE2_ARCH_2_07 | PPC_FEATURE2_HTM | PPC_FEATURE2_DSCR |
195 PPC_FEATURE2_EBB | PPC_FEATURE2_ISEL | PPC_FEATURE2_TAR |
196 PPC_FEATURE2_HAS_VEC_CRYPTO | PPC_FEATURE2_HTM_NOSC |
197 PPC_FEATURE2_ARCH_3_00 | PPC_FEATURE2_HAS_IEEE128 |
198 PPC_FEATURE2_DARN, cpu_powerx_setup },
199 { "Motorola PowerPC 7400", MPC7400, REVFMT_MAJMIN,
200 PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU, 0, cpu_6xx_setup },
201 { "Motorola PowerPC 7410", MPC7410, REVFMT_MAJMIN,
202 PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU, 0, cpu_6xx_setup },
203 { "Motorola PowerPC 7450", MPC7450, REVFMT_MAJMIN,
204 PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU, 0, cpu_6xx_setup },
205 { "Motorola PowerPC 7455", MPC7455, REVFMT_MAJMIN,
206 PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU, 0, cpu_6xx_setup },
207 { "Motorola PowerPC 7457", MPC7457, REVFMT_MAJMIN,
208 PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU, 0, cpu_6xx_setup },
209 { "Motorola PowerPC 7447A", MPC7447A, REVFMT_MAJMIN,
210 PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU, 0, cpu_6xx_setup },
211 { "Motorola PowerPC 7448", MPC7448, REVFMT_MAJMIN,
212 PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU, 0, cpu_6xx_setup },
213 { "Motorola PowerPC 8240", MPC8240, REVFMT_MAJMIN,
214 PPC_FEATURE_HAS_FPU, 0, cpu_6xx_setup },
215 { "Motorola PowerPC 8245", MPC8245, REVFMT_MAJMIN,
216 PPC_FEATURE_HAS_FPU, 0, cpu_6xx_setup },
217 { "Freescale e500v1 core", FSL_E500v1, REVFMT_MAJMIN,
218 PPC_FEATURE_HAS_SPE | PPC_FEATURE_HAS_EFP_SINGLE | PPC_FEATURE_BOOKE,
219 PPC_FEATURE2_ISEL, cpu_booke_setup },
220 { "Freescale e500v2 core", FSL_E500v2, REVFMT_MAJMIN,
221 PPC_FEATURE_HAS_SPE | PPC_FEATURE_BOOKE |
222 PPC_FEATURE_HAS_EFP_SINGLE | PPC_FEATURE_HAS_EFP_DOUBLE,
223 PPC_FEATURE2_ISEL, cpu_booke_setup },
224 { "Freescale e500mc core", FSL_E500mc, REVFMT_MAJMIN,
225 PPC_FEATURE_HAS_FPU | PPC_FEATURE_BOOKE | PPC_FEATURE_ARCH_2_05 |
226 PPC_FEATURE_ARCH_2_06, PPC_FEATURE2_ISEL,
228 { "Freescale e5500 core", FSL_E5500, REVFMT_MAJMIN,
229 PPC_FEATURE_64 | PPC_FEATURE_HAS_FPU | PPC_FEATURE_BOOKE |
230 PPC_FEATURE_ARCH_2_05 | PPC_FEATURE_ARCH_2_06,
231 PPC_FEATURE2_ISEL, cpu_booke_setup },
232 { "Freescale e6500 core", FSL_E6500, REVFMT_MAJMIN,
233 PPC_FEATURE_64 | PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU |
234 PPC_FEATURE_BOOKE | PPC_FEATURE_ARCH_2_05 | PPC_FEATURE_ARCH_2_06,
235 PPC_FEATURE2_ISEL, cpu_booke_setup },
236 { "IBM Cell Broadband Engine", IBMCELLBE, REVFMT_MAJMIN,
237 PPC_FEATURE_64 | PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU |
238 PPC_FEATURE_CELL | PPC_FEATURE_SMT, 0, NULL},
239 { "Unknown PowerPC CPU", 0, REVFMT_HEX, 0, 0, NULL },
242 static void cpu_6xx_print_cacheinfo(u_int, uint16_t);
243 static int cpu_feature_bit(SYSCTL_HANDLER_ARGS);
245 static char model[64];
246 SYSCTL_STRING(_hw, HW_MODEL, model, CTLFLAG_RD, model, 0, "");
248 static const struct cputab *cput;
250 u_long cpu_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU;
251 u_long cpu_features2 = 0;
252 SYSCTL_OPAQUE(_hw, OID_AUTO, cpu_features, CTLFLAG_RD,
253 &cpu_features, sizeof(cpu_features), "LX", "PowerPC CPU features");
254 SYSCTL_OPAQUE(_hw, OID_AUTO, cpu_features2, CTLFLAG_RD,
255 &cpu_features2, sizeof(cpu_features2), "LX", "PowerPC CPU features 2");
258 register_t lpcr = LPCR_LPES;
261 /* Provide some user-friendly aliases for bits in cpu_features */
262 SYSCTL_PROC(_hw, OID_AUTO, floatingpoint, CTLTYPE_INT | CTLFLAG_RD,
263 0, PPC_FEATURE_HAS_FPU, cpu_feature_bit, "I",
264 "Floating point instructions executed in hardware");
265 SYSCTL_PROC(_hw, OID_AUTO, altivec, CTLTYPE_INT | CTLFLAG_RD,
266 0, PPC_FEATURE_HAS_ALTIVEC, cpu_feature_bit, "I", "CPU supports Altivec");
269 * Phase 1 (early) CPU setup. Setup the cpu_features/cpu_features2 variables,
270 * so they can be used during platform and MMU bringup.
277 const struct cputab *cp;
281 for (cp = models; cp->version != 0; cp++) {
282 if (cp->version == vers)
287 cpu_features |= cp->features;
288 cpu_features2 |= cp->features2;
293 cpu_setup(u_int cpuid)
298 uint16_t rev, revfmt, vers;
305 min = (pvr >> 0) & 0xff;
306 maj = min <= 4 ? 1 : 2;
312 maj = (pvr >> 4) & 0xf;
313 min = (pvr >> 0) & 0xf;
316 maj = (pvr >> 8) & 0xf;
317 min = (pvr >> 0) & 0xf;
320 revfmt = cput->revfmt;
322 if (rev == MPC750 && pvr == 15) {
323 name = "Motorola MPC755";
326 strncpy(model, name, sizeof(model) - 1);
328 printf("cpu%d: %s revision ", cpuid, name);
332 printf("%u.%u", maj, min);
335 printf("0x%04x", rev);
342 if (cpu_est_clockrate(0, &cps) == 0)
343 printf(", %jd.%02jd MHz", cps / 1000000, (cps / 10000) % 100);
346 printf("cpu%d: Features %b\n", cpuid, (int)cpu_features,
347 PPC_FEATURE_BITMASK);
348 if (cpu_features2 != 0)
349 printf("cpu%d: Features2 %b\n", cpuid, (int)cpu_features2,
350 PPC_FEATURE2_BITMASK);
355 if (cput->cpu_setup != NULL)
356 cput->cpu_setup(cpuid, vers);
359 /* Get current clock frequency for the given cpu id. */
361 cpu_est_clockrate(int cpu_id, uint64_t *cps)
365 phandle_t cpu, dev, root;
369 vers = mfpvr() >> 16;
371 mtmsr(msr & ~PSL_EE);
383 mtspr(SPR_MMCR0, SPR_MMCR0_FC);
385 mtspr(SPR_MMCR0, SPR_MMCR0_PMC1SEL(PMCN_CYCLES));
387 *cps = (mfspr(SPR_PMC1) * 1000) + 4999;
388 mtspr(SPR_MMCR0, SPR_MMCR0_FC);
396 mtspr(SPR_970MMCR0, SPR_MMCR0_FC);
398 mtspr(SPR_970MMCR1, 0);
399 mtspr(SPR_970MMCRA, 0);
400 mtspr(SPR_970PMC1, 0);
402 SPR_970MMCR0_PMC1SEL(PMC970N_CYCLES));
406 mtspr(SPR_970MMCR0, SPR_MMCR0_FC);
407 *cps = (mfspr(SPR_970PMC1) * 1000) + 4999;
417 dev = OF_child(root);
419 res = OF_getprop(dev, "name", buf, sizeof(buf));
420 if (res > 0 && strcmp(buf, "cpus") == 0)
426 res = OF_getprop(cpu, "device_type", buf,
428 if (res > 0 && strcmp(buf, "cpu") == 0)
434 if (OF_getprop(cpu, "ibm,extended-clock-frequency",
435 cps, sizeof(*cps)) >= 0) {
437 } else if (OF_getprop(cpu, "clock-frequency", cps,
438 sizeof(cell_t)) >= 0) {
448 cpu_6xx_setup(int cpuid, uint16_t vers)
450 register_t hid0, pvr;
453 hid0 = mfspr(SPR_HID0);
457 * Configure power-saving mode.
470 /* Select DOZE mode. */
471 hid0 &= ~(HID0_DOZE | HID0_NAP | HID0_SLEEP);
472 hid0 |= HID0_DOZE | HID0_DPM;
473 powerpc_pow_enabled = 1;
481 /* Enable the 7450 branch caches */
482 hid0 |= HID0_SGE | HID0_BTIC;
483 hid0 |= HID0_LRSTK | HID0_FOLD | HID0_BHT;
484 /* Disable BTIC on 7450 Rev 2.0 or earlier and on 7457 */
485 if (((pvr >> 16) == MPC7450 && (pvr & 0xFFFF) <= 0x0200)
486 || (pvr >> 16) == MPC7457)
488 /* Select NAP mode. */
489 hid0 &= ~(HID0_DOZE | HID0_NAP | HID0_SLEEP);
490 hid0 |= HID0_NAP | HID0_DPM;
491 powerpc_pow_enabled = 1;
495 /* No power-saving mode is available. */ ;
501 hid0 &= ~HID0_DBP; /* XXX correct? */
502 hid0 |= HID0_EMCP | HID0_BTIC | HID0_SGE | HID0_BHT;
508 hid0 |= HID0_EMCP | HID0_BTIC | HID0_SGE | HID0_BHT;
514 mtspr(SPR_HID0, hid0);
517 cpu_6xx_print_cacheinfo(cpuid, vers);
525 bitmask = HID0_7450_BITMASK;
528 bitmask = HID0_BITMASK;
532 printf("cpu%d: HID0 %b\n", cpuid, (int)hid0, bitmask);
534 if (cpu_idle_hook == NULL)
535 cpu_idle_hook = cpu_idle_60x;
540 cpu_6xx_print_cacheinfo(u_int cpuid, uint16_t vers)
544 hid = mfspr(SPR_HID0);
545 printf("cpu%u: ", cpuid);
546 printf("L1 I-cache %sabled, ", (hid & HID0_ICE) ? "en" : "dis");
547 printf("L1 D-cache %sabled\n", (hid & HID0_DCE) ? "en" : "dis");
549 printf("cpu%u: ", cpuid);
550 if (mfspr(SPR_L2CR) & L2CR_L2E) {
555 printf("256KB L2 cache, ");
556 if (mfspr(SPR_L3CR) & L3CR_L3E)
557 printf("%cMB L3 backside cache",
558 mfspr(SPR_L3CR) & L3CR_L3SIZ ? '2' : '1');
560 printf("L3 cache disabled");
564 printf("512KB L2 cache\n");
567 switch (mfspr(SPR_L2CR) & L2CR_L2SIZ) {
578 printf("write-%s", (mfspr(SPR_L2CR) & L2CR_L2WT)
579 ? "through" : "back");
580 if (mfspr(SPR_L2CR) & L2CR_L2PE)
581 printf(", with parity");
582 printf(" backside cache\n");
586 printf("L2 cache disabled\n");
590 cpu_booke_setup(int cpuid, uint16_t vers)
596 hid0 = mfspr(SPR_HID0);
600 bitmask = HID0_E500MC_BITMASK;
601 cpu_idle_hook = cpu_idle_e500mc;
605 bitmask = HID0_E5500_BITMASK;
606 cpu_idle_hook = cpu_idle_e500mc;
610 /* Only e500v1/v2 support HID0 power management setup. */
612 /* Program power-management mode. */
613 hid0 &= ~(HID0_DOZE | HID0_NAP | HID0_SLEEP);
616 mtspr(SPR_HID0, hid0);
618 bitmask = HID0_E500_BITMASK;
621 printf("cpu%d: HID0 %b\n", cpuid, (int)hid0, bitmask);
624 if (cpu_idle_hook == NULL)
625 cpu_idle_hook = cpu_idle_booke;
629 cpu_970_setup(int cpuid, uint16_t vers)
632 uint32_t hid0_hi, hid0_lo;
634 __asm __volatile ("mfspr %0,%2; clrldi %1,%0,32; srdi %0,%0,32;"
635 : "=r" (hid0_hi), "=r" (hid0_lo) : "K" (SPR_HID0));
637 /* Configure power-saving mode */
640 hid0_hi |= (HID0_DEEPNAP | HID0_NAP | HID0_DPM);
641 hid0_hi &= ~HID0_DOZE;
644 hid0_hi |= (HID0_NAP | HID0_DPM);
645 hid0_hi &= ~(HID0_DOZE | HID0_DEEPNAP);
648 powerpc_pow_enabled = 1;
650 __asm __volatile (" \
652 sldi %0,%0,32; or %0,%0,%1; \
654 mfspr %0, %2; mfspr %0, %2; mfspr %0, %2; \
655 mfspr %0, %2; mfspr %0, %2; mfspr %0, %2; \
657 :: "r" (hid0_hi), "r"(hid0_lo), "K" (SPR_HID0));
659 __asm __volatile ("mfspr %0,%1; srdi %0,%0,32;"
660 : "=r" (hid0_hi) : "K" (SPR_HID0));
661 printf("cpu%d: HID0 %b\n", cpuid, (int)(hid0_hi), HID0_970_BITMASK);
664 cpu_idle_hook = cpu_idle_60x;
668 cpu_powerx_setup(int cpuid, uint16_t vers)
671 #if defined(__powerpc64__) && defined(AIM)
672 if ((mfmsr() & PSL_HV) == 0)
675 /* Nuke the FSCR, to disable all facilities. */
678 /* Configure power-saving */
683 cpu_idle_hook = cpu_idle_powerx;
684 mtspr(SPR_LPCR, mfspr(SPR_LPCR) | LPCR_PECE_WAKESET);
688 cpu_idle_hook = cpu_idle_power9;
689 mtspr(SPR_LPCR, mfspr(SPR_LPCR) | LPCR_PECE_WAKESET);
700 cpu_feature_bit(SYSCTL_HANDLER_ARGS)
704 result = (cpu_features & arg2) ? 1 : 0;
706 return (sysctl_handle_int(oidp, &result, 0, req));
715 if ((mfmsr() & PSL_EE) != PSL_EE) {
716 struct thread *td = curthread;
717 printf("td msr %#lx\n", (u_long)td->td_md.md_saved_msr);
718 panic("ints disabled in idleproc!");
722 CTR2(KTR_SPARE2, "cpu_idle(%d) at %d",
725 if (cpu_idle_hook != NULL) {
728 sbt = cpu_idleclock();
737 CTR2(KTR_SPARE2, "cpu_idle(%d) at %d done",
742 cpu_idle_60x(sbintime_t sbt)
747 if (!powerpc_pow_enabled)
751 vers = mfpvr() >> 16;
764 dssall; sync; mtmsr %0; isync"
765 :: "r"(msr | PSL_POW));
769 mtmsr(msr | PSL_POW);
777 cpu_idle_e500mc(sbintime_t sbt)
780 * Base binutils doesn't know what the 'wait' instruction is, so
781 * use the opcode encoding here.
783 __asm __volatile(".long 0x7c00007c");
788 cpu_idle_booke(sbintime_t sbt)
800 #if defined(__powerpc64__) && defined(AIM)
802 cpu_idle_powerx(sbintime_t sbt)
804 /* Sleeping when running on one cpu gives no advantages - avoid it */
805 if (smp_started == 0)
809 if (sched_runnable()) {
823 cpu_idle_power9(sbintime_t sbt)
829 /* Suspend external interrupts until stop instruction completes. */
830 mtmsr(msr & ~PSL_EE);
831 /* Set the stop state to lowest latency, wake up to next instruction */
832 /* Set maximum transition level to 2, for deepest lossless sleep. */
833 mtspr(SPR_PSSCR, (2 << PSSCR_MTL_S) | (0 << PSSCR_RL_S));
834 /* "stop" instruction (PowerISA 3.0) */
835 __asm __volatile (".long 0x4c0002e4");
837 * Re-enable external interrupts to capture the interrupt that caused
846 cpu_idle_wakeup(int cpu)