sys/powerpc/powerpc/cpu.c

   1 /*-
   2  * SPDX-License-Identifier: BSD-4-Clause AND BSD-2-Clause-FreeBSD
   3  *
   4  * Copyright (c) 2001 Matt Thomas.
   5  * Copyright (c) 2001 Tsubai Masanari.
   6  * Copyright (c) 1998, 1999, 2001 Internet Research Institute, Inc.
   7  * All rights reserved.
   8  *
   9  * Redistribution and use in source and binary forms, with or without
  10  * modification, are permitted provided that the following conditions
  11  * are met:
  12  * 1. Redistributions of source code must retain the above copyright
  13  *    notice, this list of conditions and the following disclaimer.
  14  * 2. Redistributions in binary form must reproduce the above copyright
  15  *    notice, this list of conditions and the following disclaimer in the
  16  *    documentation and/or other materials provided with the distribution.
  17  * 3. All advertising materials mentioning features or use of this software
  18  *    must display the following acknowledgement:
  19  *      This product includes software developed by
  20  *      Internet Research Institute, Inc.
  21  * 4. The name of the author may not be used to endorse or promote products
  22  *    derived from this software without specific prior written permission.
  23  *
  24  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  25  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  26  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  27  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  28  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  29  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  30  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  31  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  32  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  33  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  34  */
  35 /*-
  36  * Copyright (C) 2003 Benno Rice.
  37  * All rights reserved.
  38  *
  39  * Redistribution and use in source and binary forms, with or without
  40  * modification, are permitted provided that the following conditions
  41  * are met:
  42  * 1. Redistributions of source code must retain the above copyright
  43  *    notice, this list of conditions and the following disclaimer.
  44  * 2. Redistributions in binary form must reproduce the above copyright
  45  *    notice, this list of conditions and the following disclaimer in the
  46  *    documentation and/or other materials provided with the distribution.
  47  *
  48  * THIS SOFTWARE IS PROVIDED BY Benno Rice ``AS IS'' AND ANY EXPRESS OR
  49  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  50  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  51  * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  52  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
  53  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
  54  * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
  55  * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
  56  * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
  57  * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  58  *
  59  * from $NetBSD: cpu_subr.c,v 1.1 2003/02/03 17:10:09 matt Exp $
  60  * $FreeBSD$
  61  */
  62
  63 #include <sys/param.h>
  64 #include <sys/systm.h>
  65 #include <sys/bus.h>
  66 #include <sys/conf.h>
  67 #include <sys/cpu.h>
  68 #include <sys/kernel.h>
  69 #include <sys/proc.h>
  70 #include <sys/sysctl.h>
  71 #include <sys/sched.h>
  72 #include <sys/smp.h>
  73
  74 #include <machine/bus.h>
  75 #include <machine/cpu.h>
  76 #include <machine/hid.h>
  77 #include <machine/md_var.h>
  78 #include <machine/smp.h>
  79 #include <machine/spr.h>
  80
  81 #include <dev/ofw/openfirm.h>
  82
  83 static void     cpu_6xx_setup(int cpuid, uint16_t vers);
  84 static void     cpu_970_setup(int cpuid, uint16_t vers);
  85 static void     cpu_booke_setup(int cpuid, uint16_t vers);
  86 static void     cpu_powerx_setup(int cpuid, uint16_t vers);
  87
  88 int powerpc_pow_enabled;
  89 void (*cpu_idle_hook)(sbintime_t) = NULL;
  90 static void     cpu_idle_60x(sbintime_t);
  91 static void     cpu_idle_booke(sbintime_t);
  92 #ifdef BOOKE_E500
  93 static void     cpu_idle_e500mc(sbintime_t sbt);
  94 #endif
  95 #if defined(__powerpc64__) && defined(AIM)
  96 static void     cpu_idle_powerx(sbintime_t);
  97 static void     cpu_idle_power9(sbintime_t);
  98 #endif
  99
 100 struct cputab {
 101         const char      *name;
 102         uint16_t        version;
 103         uint16_t        revfmt;
 104         int             features;       /* Do not include PPC_FEATURE_32 or
 105                                          * PPC_FEATURE_HAS_MMU */
 106         int             features2;
 107         void            (*cpu_setup)(int cpuid, uint16_t vers);
 108 };
 109 #define REVFMT_MAJMIN   1       /* %u.%u */
 110 #define REVFMT_HEX      2       /* 0x%04x */
 111 #define REVFMT_DEC      3       /* %u */
 112 static const struct cputab models[] = {
 113         { "Motorola PowerPC 601",       MPC601,         REVFMT_DEC,
 114            PPC_FEATURE_HAS_FPU | PPC_FEATURE_UNIFIED_CACHE, 0, cpu_6xx_setup },
 115         { "Motorola PowerPC 602",       MPC602,         REVFMT_DEC,
 116            PPC_FEATURE_HAS_FPU, 0, cpu_6xx_setup },
 117         { "Motorola PowerPC 603",       MPC603,         REVFMT_MAJMIN,
 118            PPC_FEATURE_HAS_FPU, 0, cpu_6xx_setup },
 119         { "Motorola PowerPC 603e",      MPC603e,        REVFMT_MAJMIN,
 120            PPC_FEATURE_HAS_FPU, 0, cpu_6xx_setup },
 121         { "Motorola PowerPC 603ev",     MPC603ev,       REVFMT_MAJMIN,
 122            PPC_FEATURE_HAS_FPU, 0, cpu_6xx_setup },
 123         { "Motorola PowerPC 604",       MPC604,         REVFMT_MAJMIN,
 124            PPC_FEATURE_HAS_FPU, 0, cpu_6xx_setup },
 125         { "Motorola PowerPC 604ev",     MPC604ev,       REVFMT_MAJMIN,
 126            PPC_FEATURE_HAS_FPU, 0, cpu_6xx_setup },
 127         { "Motorola PowerPC 620",       MPC620,         REVFMT_HEX,
 128            PPC_FEATURE_64 | PPC_FEATURE_HAS_FPU, 0, NULL },
 129         { "Motorola PowerPC 750",       MPC750,         REVFMT_MAJMIN,
 130            PPC_FEATURE_HAS_FPU, 0, cpu_6xx_setup },
 131         { "IBM PowerPC 750FX",          IBM750FX,       REVFMT_MAJMIN,
 132            PPC_FEATURE_HAS_FPU, 0, cpu_6xx_setup },
 133         { "IBM PowerPC 970",            IBM970,         REVFMT_MAJMIN,
 134            PPC_FEATURE_64 | PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU,
 135            0, cpu_970_setup },
 136         { "IBM PowerPC 970FX",          IBM970FX,       REVFMT_MAJMIN,
 137            PPC_FEATURE_64 | PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU,
 138            0, cpu_970_setup },
 139         { "IBM PowerPC 970GX",          IBM970GX,       REVFMT_MAJMIN,
 140            PPC_FEATURE_64 | PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU,
 141            0, cpu_970_setup },
 142         { "IBM PowerPC 970MP",          IBM970MP,       REVFMT_MAJMIN,
 143            PPC_FEATURE_64 | PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU,
 144            0, cpu_970_setup },
 145         { "IBM POWER4",         IBMPOWER4,      REVFMT_MAJMIN,
 146            PPC_FEATURE_64 | PPC_FEATURE_HAS_FPU | PPC_FEATURE_POWER4, 0, NULL },
 147         { "IBM POWER4+",        IBMPOWER4PLUS,  REVFMT_MAJMIN,
 148            PPC_FEATURE_64 | PPC_FEATURE_HAS_FPU | PPC_FEATURE_POWER4, 0, NULL },
 149         { "IBM POWER5",         IBMPOWER5,      REVFMT_MAJMIN,
 150            PPC_FEATURE_64 | PPC_FEATURE_HAS_FPU | PPC_FEATURE_POWER4 |
 151            PPC_FEATURE_SMT | PPC_FEATURE_ICACHE_SNOOP, 0, NULL },
 152         { "IBM POWER5+",        IBMPOWER5PLUS,  REVFMT_MAJMIN,
 153            PPC_FEATURE_64 | PPC_FEATURE_HAS_FPU | PPC_FEATURE_POWER5_PLUS |
 154            PPC_FEATURE_SMT | PPC_FEATURE_ICACHE_SNOOP, 0, NULL },
 155         { "IBM POWER6",         IBMPOWER6,      REVFMT_MAJMIN,
 156            PPC_FEATURE_64 | PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU |
 157            PPC_FEATURE_SMT | PPC_FEATURE_ICACHE_SNOOP | PPC_FEATURE_ARCH_2_05 |
 158            PPC_FEATURE_TRUE_LE, 0, NULL },
 159         { "IBM POWER7",         IBMPOWER7,      REVFMT_MAJMIN,
 160            PPC_FEATURE_64 | PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU |
 161            PPC_FEATURE_SMT | PPC_FEATURE_ARCH_2_05 | PPC_FEATURE_ARCH_2_06 |
 162            PPC_FEATURE_HAS_VSX | PPC_FEATURE_TRUE_LE, PPC_FEATURE2_DSCR, NULL },
 163         { "IBM POWER7+",        IBMPOWER7PLUS,  REVFMT_MAJMIN,
 164            PPC_FEATURE_64 | PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU |
 165            PPC_FEATURE_SMT | PPC_FEATURE_ARCH_2_05 | PPC_FEATURE_ARCH_2_06 |
 166            PPC_FEATURE_HAS_VSX, PPC_FEATURE2_DSCR, NULL },
 167         { "IBM POWER8E",        IBMPOWER8E,     REVFMT_MAJMIN,
 168            PPC_FEATURE_64 | PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU |
 169            PPC_FEATURE_SMT | PPC_FEATURE_ICACHE_SNOOP | PPC_FEATURE_ARCH_2_05 |
 170            PPC_FEATURE_ARCH_2_06 | PPC_FEATURE_HAS_VSX | PPC_FEATURE_TRUE_LE,
 171            PPC_FEATURE2_ARCH_2_07 | PPC_FEATURE2_HTM | PPC_FEATURE2_DSCR |
 172            PPC_FEATURE2_ISEL | PPC_FEATURE2_TAR | PPC_FEATURE2_HAS_VEC_CRYPTO |
 173            PPC_FEATURE2_HTM_NOSC, cpu_powerx_setup },
 174         { "IBM POWER8",         IBMPOWER8,      REVFMT_MAJMIN,
 175            PPC_FEATURE_64 | PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU |
 176            PPC_FEATURE_SMT | PPC_FEATURE_ICACHE_SNOOP | PPC_FEATURE_ARCH_2_05 |
 177            PPC_FEATURE_ARCH_2_06 | PPC_FEATURE_HAS_VSX | PPC_FEATURE_TRUE_LE,
 178            PPC_FEATURE2_ARCH_2_07 | PPC_FEATURE2_HTM | PPC_FEATURE2_DSCR |
 179            PPC_FEATURE2_ISEL | PPC_FEATURE2_TAR | PPC_FEATURE2_HAS_VEC_CRYPTO |
 180            PPC_FEATURE2_HTM_NOSC, cpu_powerx_setup },
 181         { "IBM POWER9",         IBMPOWER9,      REVFMT_MAJMIN,
 182            PPC_FEATURE_64 | PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU |
 183            PPC_FEATURE_SMT | PPC_FEATURE_ICACHE_SNOOP | PPC_FEATURE_ARCH_2_05 |
 184            PPC_FEATURE_ARCH_2_06 | PPC_FEATURE_HAS_VSX | PPC_FEATURE_TRUE_LE,
 185            PPC_FEATURE2_ARCH_2_07 | PPC_FEATURE2_HTM | PPC_FEATURE2_DSCR |
 186            PPC_FEATURE2_EBB | PPC_FEATURE2_ISEL | PPC_FEATURE2_TAR |
 187            PPC_FEATURE2_HAS_VEC_CRYPTO | PPC_FEATURE2_HTM_NOSC |
 188            PPC_FEATURE2_ARCH_3_00 | PPC_FEATURE2_HAS_IEEE128 |
 189            PPC_FEATURE2_DARN, cpu_powerx_setup },
 190         { "Motorola PowerPC 7400",      MPC7400,        REVFMT_MAJMIN,
 191            PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU, 0, cpu_6xx_setup },
 192         { "Motorola PowerPC 7410",      MPC7410,        REVFMT_MAJMIN,
 193            PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU, 0, cpu_6xx_setup },
 194         { "Motorola PowerPC 7450",      MPC7450,        REVFMT_MAJMIN,
 195            PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU, 0, cpu_6xx_setup },
 196         { "Motorola PowerPC 7455",      MPC7455,        REVFMT_MAJMIN,
 197            PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU, 0, cpu_6xx_setup },
 198         { "Motorola PowerPC 7457",      MPC7457,        REVFMT_MAJMIN,
 199            PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU, 0, cpu_6xx_setup },
 200         { "Motorola PowerPC 7447A",     MPC7447A,       REVFMT_MAJMIN,
 201            PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU, 0, cpu_6xx_setup },
 202         { "Motorola PowerPC 7448",      MPC7448,        REVFMT_MAJMIN,
 203            PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU, 0, cpu_6xx_setup },
 204         { "Motorola PowerPC 8240",      MPC8240,        REVFMT_MAJMIN,
 205            PPC_FEATURE_HAS_FPU, 0, cpu_6xx_setup },
 206         { "Motorola PowerPC 8245",      MPC8245,        REVFMT_MAJMIN,
 207            PPC_FEATURE_HAS_FPU, 0, cpu_6xx_setup },
 208         { "Freescale e500v1 core",      FSL_E500v1,     REVFMT_MAJMIN,
 209            PPC_FEATURE_HAS_SPE | PPC_FEATURE_HAS_EFP_SINGLE | PPC_FEATURE_BOOKE,
 210            PPC_FEATURE2_ISEL, cpu_booke_setup },
 211         { "Freescale e500v2 core",      FSL_E500v2,     REVFMT_MAJMIN,
 212            PPC_FEATURE_HAS_SPE | PPC_FEATURE_BOOKE |
 213            PPC_FEATURE_HAS_EFP_SINGLE | PPC_FEATURE_HAS_EFP_DOUBLE,
 214            PPC_FEATURE2_ISEL, cpu_booke_setup },
 215         { "Freescale e500mc core",      FSL_E500mc,     REVFMT_MAJMIN,
 216            PPC_FEATURE_HAS_FPU | PPC_FEATURE_BOOKE | PPC_FEATURE_ARCH_2_05 |
 217            PPC_FEATURE_ARCH_2_06, PPC_FEATURE2_ISEL,
 218            cpu_booke_setup },
 219         { "Freescale e5500 core",       FSL_E5500,      REVFMT_MAJMIN,
 220            PPC_FEATURE_64 | PPC_FEATURE_HAS_FPU | PPC_FEATURE_BOOKE |
 221            PPC_FEATURE_ARCH_2_05 | PPC_FEATURE_ARCH_2_06,
 222            PPC_FEATURE2_ISEL, cpu_booke_setup },
 223         { "Freescale e6500 core",       FSL_E6500,      REVFMT_MAJMIN,
 224            PPC_FEATURE_64 | PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU |
 225            PPC_FEATURE_BOOKE | PPC_FEATURE_ARCH_2_05 | PPC_FEATURE_ARCH_2_06,
 226            PPC_FEATURE2_ISEL, cpu_booke_setup },
 227         { "IBM Cell Broadband Engine",  IBMCELLBE,      REVFMT_MAJMIN,
 228            PPC_FEATURE_64 | PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU |
 229            PPC_FEATURE_CELL | PPC_FEATURE_SMT, 0, NULL},
 230         { "Unknown PowerPC CPU",        0,              REVFMT_HEX, 0, 0, NULL },
 231 };
 232
 233 static void     cpu_6xx_print_cacheinfo(u_int, uint16_t);
 234 static int      cpu_feature_bit(SYSCTL_HANDLER_ARGS);
 235
 236 static char model[64];
 237 SYSCTL_STRING(_hw, HW_MODEL, model, CTLFLAG_RD, model, 0, "");
 238
 239 static const struct cputab      *cput;
 240
 241 u_long cpu_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU;
 242 u_long cpu_features2 = 0;
 243 SYSCTL_OPAQUE(_hw, OID_AUTO, cpu_features, CTLFLAG_RD,
 244     &cpu_features, sizeof(cpu_features), "LX", "PowerPC CPU features");
 245 SYSCTL_OPAQUE(_hw, OID_AUTO, cpu_features2, CTLFLAG_RD,
 246     &cpu_features2, sizeof(cpu_features2), "LX", "PowerPC CPU features 2");
 247
 248 #ifdef __powerpc64__
 249 register_t      lpcr = LPCR_LPES;
 250 #endif
 251
 252 /* Provide some user-friendly aliases for bits in cpu_features */
 253 SYSCTL_PROC(_hw, OID_AUTO, floatingpoint, CTLTYPE_INT | CTLFLAG_RD,
 254     0, PPC_FEATURE_HAS_FPU, cpu_feature_bit, "I",
 255     "Floating point instructions executed in hardware");
 256 SYSCTL_PROC(_hw, OID_AUTO, altivec, CTLTYPE_INT | CTLFLAG_RD,
 257     0, PPC_FEATURE_HAS_ALTIVEC, cpu_feature_bit, "I", "CPU supports Altivec");
 258
 259 /*
 260  * Phase 1 (early) CPU setup.  Setup the cpu_features/cpu_features2 variables,
 261  * so they can be used during platform and MMU bringup.
 262  */
 263 void
 264 cpu_feature_setup()
 265 {
 266         u_int           pvr;
 267         uint16_t        vers;
 268         const struct    cputab *cp;
 269
 270         pvr = mfpvr();
 271         vers = pvr >> 16;
 272         for (cp = models; cp->version != 0; cp++) {
 273                 if (cp->version == vers)
 274                         break;
 275         }
 276
 277         cput = cp;
 278         cpu_features |= cp->features;
 279         cpu_features2 |= cp->features2;
 280 }
 281
 282
 283 void
 284 cpu_setup(u_int cpuid)
 285 {
 286         uint64_t        cps;
 287         const char      *name;
 288         u_int           maj, min, pvr;
 289         uint16_t        rev, revfmt, vers;
 290
 291         pvr = mfpvr();
 292         vers = pvr >> 16;
 293         rev = pvr;
 294         switch (vers) {
 295                 case MPC7410:
 296                         min = (pvr >> 0) & 0xff;
 297                         maj = min <= 4 ? 1 : 2;
 298                         break;
 299                 case FSL_E500v1:
 300                 case FSL_E500v2:
 301                 case FSL_E500mc:
 302                 case FSL_E5500:
 303                         maj = (pvr >>  4) & 0xf;
 304                         min = (pvr >>  0) & 0xf;
 305                         break;
 306                 default:
 307                         maj = (pvr >>  8) & 0xf;
 308                         min = (pvr >>  0) & 0xf;
 309         }
 310
 311         revfmt = cput->revfmt;
 312         name = cput->name;
 313         if (rev == MPC750 && pvr == 15) {
 314                 name = "Motorola MPC755";
 315                 revfmt = REVFMT_HEX;
 316         }
 317         strncpy(model, name, sizeof(model) - 1);
 318
 319         printf("cpu%d: %s revision ", cpuid, name);
 320
 321         switch (revfmt) {
 322                 case REVFMT_MAJMIN:
 323                         printf("%u.%u", maj, min);
 324                         break;
 325                 case REVFMT_HEX:
 326                         printf("0x%04x", rev);
 327                         break;
 328                 case REVFMT_DEC:
 329                         printf("%u", rev);
 330                         break;
 331         }
 332
 333         if (cpu_est_clockrate(0, &cps) == 0)
 334                 printf(", %jd.%02jd MHz", cps / 1000000, (cps / 10000) % 100);
 335         printf("\n");
 336
 337         printf("cpu%d: Features %b\n", cpuid, (int)cpu_features,
 338             PPC_FEATURE_BITMASK);
 339         if (cpu_features2 != 0)
 340                 printf("cpu%d: Features2 %b\n", cpuid, (int)cpu_features2,
 341                     PPC_FEATURE2_BITMASK);
 342
 343         /*
 344          * Configure CPU
 345          */
 346         if (cput->cpu_setup != NULL)
 347                 cput->cpu_setup(cpuid, vers);
 348 }
 349
 350 /* Get current clock frequency for the given cpu id. */
 351 int
 352 cpu_est_clockrate(int cpu_id, uint64_t *cps)
 353 {
 354         uint16_t        vers;
 355         register_t      msr;
 356         phandle_t       cpu, dev, root;
 357         int             res  = 0;
 358         char            buf[8];
 359
 360         vers = mfpvr() >> 16;
 361         msr = mfmsr();
 362         mtmsr(msr & ~PSL_EE);
 363
 364         switch (vers) {
 365                 case MPC7450:
 366                 case MPC7455:
 367                 case MPC7457:
 368                 case MPC750:
 369                 case IBM750FX:
 370                 case MPC7400:
 371                 case MPC7410:
 372                 case MPC7447A:
 373                 case MPC7448:
 374                         mtspr(SPR_MMCR0, SPR_MMCR0_FC);
 375                         mtspr(SPR_PMC1, 0);
 376                         mtspr(SPR_MMCR0, SPR_MMCR0_PMC1SEL(PMCN_CYCLES));
 377                         DELAY(1000);
 378                         *cps = (mfspr(SPR_PMC1) * 1000) + 4999;
 379                         mtspr(SPR_MMCR0, SPR_MMCR0_FC);
 380
 381                         mtmsr(msr);
 382                         return (0);
 383                 case IBM970:
 384                 case IBM970FX:
 385                 case IBM970MP:
 386                         isync();
 387                         mtspr(SPR_970MMCR0, SPR_MMCR0_FC);
 388                         isync();
 389                         mtspr(SPR_970MMCR1, 0);
 390                         mtspr(SPR_970MMCRA, 0);
 391                         mtspr(SPR_970PMC1, 0);
 392                         mtspr(SPR_970MMCR0,
 393                             SPR_970MMCR0_PMC1SEL(PMC970N_CYCLES));
 394                         isync();
 395                         DELAY(1000);
 396                         powerpc_sync();
 397                         mtspr(SPR_970MMCR0, SPR_MMCR0_FC);
 398                         *cps = (mfspr(SPR_970PMC1) * 1000) + 4999;
 399
 400                         mtmsr(msr);
 401                         return (0);
 402
 403                 default:
 404                         root = OF_peer(0);
 405                         if (root == 0)
 406                                 return (ENXIO);
 407
 408                         dev = OF_child(root);
 409                         while (dev != 0) {
 410                                 res = OF_getprop(dev, "name", buf, sizeof(buf));
 411                                 if (res > 0 && strcmp(buf, "cpus") == 0)
 412                                         break;
 413                                 dev = OF_peer(dev);
 414                         }
 415                         cpu = OF_child(dev);
 416                         while (cpu != 0) {
 417                                 res = OF_getprop(cpu, "device_type", buf,
 418                                                 sizeof(buf));
 419                                 if (res > 0 && strcmp(buf, "cpu") == 0)
 420                                         break;
 421                                 cpu = OF_peer(cpu);
 422                         }
 423                         if (cpu == 0)
 424                                 return (ENOENT);
 425                         if (OF_getprop(cpu, "ibm,extended-clock-frequency",
 426                             cps, sizeof(*cps)) >= 0) {
 427                                 return (0);
 428                         } else if (OF_getprop(cpu, "clock-frequency", cps,
 429                             sizeof(cell_t)) >= 0) {
 430                                 *cps >>= 32;
 431                                 return (0);
 432                         } else {
 433                                 return (ENOENT);
 434                         }
 435         }
 436 }
 437
 438 void
 439 cpu_6xx_setup(int cpuid, uint16_t vers)
 440 {
 441         register_t hid0, pvr;
 442         const char *bitmask;
 443
 444         hid0 = mfspr(SPR_HID0);
 445         pvr = mfpvr();
 446
 447         /*
 448          * Configure power-saving mode.
 449          */
 450         switch (vers) {
 451                 case MPC603:
 452                 case MPC603e:
 453                 case MPC603ev:
 454                 case MPC604ev:
 455                 case MPC750:
 456                 case IBM750FX:
 457                 case MPC7400:
 458                 case MPC7410:
 459                 case MPC8240:
 460                 case MPC8245:
 461                         /* Select DOZE mode. */
 462                         hid0 &= ~(HID0_DOZE | HID0_NAP | HID0_SLEEP);
 463                         hid0 |= HID0_DOZE | HID0_DPM;
 464                         powerpc_pow_enabled = 1;
 465                         break;
 466
 467                 case MPC7448:
 468                 case MPC7447A:
 469                 case MPC7457:
 470                 case MPC7455:
 471                 case MPC7450:
 472                         /* Enable the 7450 branch caches */
 473                         hid0 |= HID0_SGE | HID0_BTIC;
 474                         hid0 |= HID0_LRSTK | HID0_FOLD | HID0_BHT;
 475                         /* Disable BTIC on 7450 Rev 2.0 or earlier and on 7457 */
 476                         if (((pvr >> 16) == MPC7450 && (pvr & 0xFFFF) <= 0x0200)
 477                                         || (pvr >> 16) == MPC7457)
 478                                 hid0 &= ~HID0_BTIC;
 479                         /* Select NAP mode. */
 480                         hid0 &= ~(HID0_DOZE | HID0_NAP | HID0_SLEEP);
 481                         hid0 |= HID0_NAP | HID0_DPM;
 482                         powerpc_pow_enabled = 1;
 483                         break;
 484
 485                 default:
 486                         /* No power-saving mode is available. */ ;
 487         }
 488
 489         switch (vers) {
 490                 case IBM750FX:
 491                 case MPC750:
 492                         hid0 &= ~HID0_DBP;              /* XXX correct? */
 493                         hid0 |= HID0_EMCP | HID0_BTIC | HID0_SGE | HID0_BHT;
 494                         break;
 495
 496                 case MPC7400:
 497                 case MPC7410:
 498                         hid0 &= ~HID0_SPD;
 499                         hid0 |= HID0_EMCP | HID0_BTIC | HID0_SGE | HID0_BHT;
 500                         hid0 |= HID0_EIEC;
 501                         break;
 502
 503         }
 504
 505         mtspr(SPR_HID0, hid0);
 506
 507         if (bootverbose)
 508                 cpu_6xx_print_cacheinfo(cpuid, vers);
 509
 510         switch (vers) {
 511                 case MPC7447A:
 512                 case MPC7448:
 513                 case MPC7450:
 514                 case MPC7455:
 515                 case MPC7457:
 516                         bitmask = HID0_7450_BITMASK;
 517                         break;
 518                 default:
 519                         bitmask = HID0_BITMASK;
 520                         break;
 521         }
 522
 523         printf("cpu%d: HID0 %b\n", cpuid, (int)hid0, bitmask);
 524
 525         if (cpu_idle_hook == NULL)
 526                 cpu_idle_hook = cpu_idle_60x;
 527 }
 528
 529
 530 static void
 531 cpu_6xx_print_cacheinfo(u_int cpuid, uint16_t vers)
 532 {
 533         register_t hid;
 534
 535         hid = mfspr(SPR_HID0);
 536         printf("cpu%u: ", cpuid);
 537         printf("L1 I-cache %sabled, ", (hid & HID0_ICE) ? "en" : "dis");
 538         printf("L1 D-cache %sabled\n", (hid & HID0_DCE) ? "en" : "dis");
 539
 540         printf("cpu%u: ", cpuid);
 541         if (mfspr(SPR_L2CR) & L2CR_L2E) {
 542                 switch (vers) {
 543                 case MPC7450:
 544                 case MPC7455:
 545                 case MPC7457:
 546                         printf("256KB L2 cache, ");
 547                         if (mfspr(SPR_L3CR) & L3CR_L3E)
 548                                 printf("%cMB L3 backside cache",
 549                                     mfspr(SPR_L3CR) & L3CR_L3SIZ ? '2' : '1');
 550                         else
 551                                 printf("L3 cache disabled");
 552                         printf("\n");
 553                         break;
 554                 case IBM750FX:
 555                         printf("512KB L2 cache\n");
 556                         break;
 557                 default:
 558                         switch (mfspr(SPR_L2CR) & L2CR_L2SIZ) {
 559                         case L2SIZ_256K:
 560                                 printf("256KB ");
 561                                 break;
 562                         case L2SIZ_512K:
 563                                 printf("512KB ");
 564                                 break;
 565                         case L2SIZ_1M:
 566                                 printf("1MB ");
 567                                 break;
 568                         }
 569                         printf("write-%s", (mfspr(SPR_L2CR) & L2CR_L2WT)
 570                             ? "through" : "back");
 571                         if (mfspr(SPR_L2CR) & L2CR_L2PE)
 572                                 printf(", with parity");
 573                         printf(" backside cache\n");
 574                         break;
 575                 }
 576         } else
 577                 printf("L2 cache disabled\n");
 578 }
 579
 580 static void
 581 cpu_booke_setup(int cpuid, uint16_t vers)
 582 {
 583 #ifdef BOOKE_E500
 584         register_t hid0;
 585         const char *bitmask;
 586
 587         hid0 = mfspr(SPR_HID0);
 588
 589         switch (vers) {
 590         case FSL_E500mc:
 591                 bitmask = HID0_E500MC_BITMASK;
 592                 cpu_idle_hook = cpu_idle_e500mc;
 593                 break;
 594         case FSL_E5500:
 595         case FSL_E6500:
 596                 bitmask = HID0_E5500_BITMASK;
 597                 cpu_idle_hook = cpu_idle_e500mc;
 598                 break;
 599         case FSL_E500v1:
 600         case FSL_E500v2:
 601                 /* Only e500v1/v2 support HID0 power management setup. */
 602
 603                 /* Program power-management mode. */
 604                 hid0 &= ~(HID0_DOZE | HID0_NAP | HID0_SLEEP);
 605                 hid0 |= HID0_DOZE;
 606
 607                 mtspr(SPR_HID0, hid0);
 608         default:
 609                 bitmask = HID0_E500_BITMASK;
 610                 break;
 611         }
 612         printf("cpu%d: HID0 %b\n", cpuid, (int)hid0, bitmask);
 613 #endif
 614
 615         if (cpu_idle_hook == NULL)
 616                 cpu_idle_hook = cpu_idle_booke;
 617 }
 618
 619 static void
 620 cpu_970_setup(int cpuid, uint16_t vers)
 621 {
 622 #ifdef AIM
 623         uint32_t hid0_hi, hid0_lo;
 624
 625         __asm __volatile ("mfspr %0,%2; clrldi %1,%0,32; srdi %0,%0,32;"
 626             : "=r" (hid0_hi), "=r" (hid0_lo) : "K" (SPR_HID0));
 627
 628         /* Configure power-saving mode */
 629         switch (vers) {
 630         case IBM970MP:
 631                 hid0_hi |= (HID0_DEEPNAP | HID0_NAP | HID0_DPM);
 632                 hid0_hi &= ~HID0_DOZE;
 633                 break;
 634         default:
 635                 hid0_hi |= (HID0_NAP | HID0_DPM);
 636                 hid0_hi &= ~(HID0_DOZE | HID0_DEEPNAP);
 637                 break;
 638         }
 639         powerpc_pow_enabled = 1;
 640
 641         __asm __volatile (" \
 642                 sync; isync;                                    \
 643                 sldi    %0,%0,32; or %0,%0,%1;                  \
 644                 mtspr   %2, %0;                                 \
 645                 mfspr   %0, %2; mfspr   %0, %2; mfspr   %0, %2; \
 646                 mfspr   %0, %2; mfspr   %0, %2; mfspr   %0, %2; \
 647                 sync; isync"
 648             :: "r" (hid0_hi), "r"(hid0_lo), "K" (SPR_HID0));
 649
 650         __asm __volatile ("mfspr %0,%1; srdi %0,%0,32;"
 651             : "=r" (hid0_hi) : "K" (SPR_HID0));
 652         printf("cpu%d: HID0 %b\n", cpuid, (int)(hid0_hi), HID0_970_BITMASK);
 653 #endif
 654
 655         cpu_idle_hook = cpu_idle_60x;
 656 }
 657
 658 static void
 659 cpu_powerx_setup(int cpuid, uint16_t vers)
 660 {
 661
 662 #if defined(__powerpc64__) && defined(AIM)
 663         if ((mfmsr() & PSL_HV) == 0)
 664                 return;
 665
 666         /* Nuke the FSCR, to disable all facilities. */
 667         mtspr(SPR_FSCR, 0);
 668
 669         /* Configure power-saving */
 670         switch (vers) {
 671         case IBMPOWER8:
 672         case IBMPOWER8E:
 673                 cpu_idle_hook = cpu_idle_powerx;
 674                 mtspr(SPR_LPCR, mfspr(SPR_LPCR) | LPCR_PECE_WAKESET);
 675                 isync();
 676                 break;
 677         case IBMPOWER9:
 678                 cpu_idle_hook = cpu_idle_power9;
 679                 mtspr(SPR_LPCR, mfspr(SPR_LPCR) | LPCR_PECE_WAKESET);
 680                 isync();
 681                 break;
 682         default:
 683                 return;
 684         }
 685
 686 #endif
 687 }
 688
 689 static int
 690 cpu_feature_bit(SYSCTL_HANDLER_ARGS)
 691 {
 692         int result;
 693
 694         result = (cpu_features & arg2) ? 1 : 0;
 695
 696         return (sysctl_handle_int(oidp, &result, 0, req));
 697 }
 698
 699 void
 700 cpu_idle(int busy)
 701 {
 702         sbintime_t sbt = -1;
 703
 704 #ifdef INVARIANTS
 705         if ((mfmsr() & PSL_EE) != PSL_EE) {
 706                 struct thread *td = curthread;
 707                 printf("td msr %#lx\n", (u_long)td->td_md.md_saved_msr);
 708                 panic("ints disabled in idleproc!");
 709         }
 710 #endif
 711
 712         CTR2(KTR_SPARE2, "cpu_idle(%d) at %d",
 713             busy, curcpu);
 714
 715         if (cpu_idle_hook != NULL) {
 716                 if (!busy) {
 717                         critical_enter();
 718                         sbt = cpu_idleclock();
 719                 }
 720                 cpu_idle_hook(sbt);
 721                 if (!busy) {
 722                         cpu_activeclock();
 723                         critical_exit();
 724                 }
 725         }
 726
 727         CTR2(KTR_SPARE2, "cpu_idle(%d) at %d done",
 728             busy, curcpu);
 729 }
 730
 731 static void
 732 cpu_idle_60x(sbintime_t sbt)
 733 {
 734         register_t msr;
 735         uint16_t vers;
 736
 737         if (!powerpc_pow_enabled)
 738                 return;
 739
 740         msr = mfmsr();
 741         vers = mfpvr() >> 16;
 742
 743 #ifdef AIM
 744         switch (vers) {
 745         case IBM970:
 746         case IBM970FX:
 747         case IBM970MP:
 748         case MPC7447A:
 749         case MPC7448:
 750         case MPC7450:
 751         case MPC7455:
 752         case MPC7457:
 753                 __asm __volatile("\
 754                             dssall; sync; mtmsr %0; isync"
 755                             :: "r"(msr | PSL_POW));
 756                 break;
 757         default:
 758                 powerpc_sync();
 759                 mtmsr(msr | PSL_POW);
 760                 break;
 761         }
 762 #endif
 763 }
 764
 765 #ifdef BOOKE_E500
 766 static void
 767 cpu_idle_e500mc(sbintime_t sbt)
 768 {
 769         /*
 770          * Base binutils doesn't know what the 'wait' instruction is, so
 771          * use the opcode encoding here.
 772          */
 773         __asm __volatile(".long 0x7c00007c");
 774 }
 775 #endif
 776
 777 static void
 778 cpu_idle_booke(sbintime_t sbt)
 779 {
 780         register_t msr;
 781
 782         msr = mfmsr();
 783
 784 #ifdef BOOKE_E500
 785         powerpc_sync();
 786         mtmsr(msr | PSL_WE);
 787 #endif
 788 }
 789
 790 #if defined(__powerpc64__) && defined(AIM)
 791 static void
 792 cpu_idle_powerx(sbintime_t sbt)
 793 {
 794         /* Sleeping when running on one cpu gives no advantages - avoid it */
 795         if (smp_started == 0)
 796                 return;
 797
 798         spinlock_enter();
 799         if (sched_runnable()) {
 800                 spinlock_exit();
 801                 return;
 802         }
 803
 804         if (can_wakeup == 0)
 805                 can_wakeup = 1;
 806         mb();
 807
 808         enter_idle_powerx();
 809         spinlock_exit();
 810 }
 811
 812 static void
 813 cpu_idle_power9(sbintime_t sbt)
 814 {
 815         register_t msr;
 816
 817         msr = mfmsr();
 818
 819         /* Suspend external interrupts until stop instruction completes. */
 820         mtmsr(msr &  ~PSL_EE);
 821         /* Set the stop state to lowest latency, wake up to next instruction */
 822         /* Set maximum transition level to 2, for deepest lossless sleep. */
 823         mtspr(SPR_PSSCR, (2 << PSSCR_MTL_S) | (0 << PSSCR_RL_S));
 824         /* "stop" instruction (PowerISA 3.0) */
 825         __asm __volatile (".long 0x4c0002e4");
 826         /*
 827          * Re-enable external interrupts to capture the interrupt that caused
 828          * the wake up.
 829          */
 830         mtmsr(msr);
 831
 832 }
 833 #endif
 834
 835 int
 836 cpu_idle_wakeup(int cpu)
 837 {
 838
 839         return (0);
 840 }