2 * Copyright (c) 2001 Matt Thomas.
3 * Copyright (c) 2001 Tsubai Masanari.
4 * Copyright (c) 1998, 1999, 2001 Internet Research Institute, Inc.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. All advertising materials mentioning features or use of this software
16 * must display the following acknowledgement:
17 * This product includes software developed by
18 * Internet Research Institute, Inc.
19 * 4. The name of the author may not be used to endorse or promote products
20 * derived from this software without specific prior written permission.
22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 * Copyright (C) 2003 Benno Rice.
35 * All rights reserved.
37 * Redistribution and use in source and binary forms, with or without
38 * modification, are permitted provided that the following conditions
40 * 1. Redistributions of source code must retain the above copyright
41 * notice, this list of conditions and the following disclaimer.
42 * 2. Redistributions in binary form must reproduce the above copyright
43 * notice, this list of conditions and the following disclaimer in the
44 * documentation and/or other materials provided with the distribution.
46 * THIS SOFTWARE IS PROVIDED BY Benno Rice ``AS IS'' AND ANY EXPRESS OR
47 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
48 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
49 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
50 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
51 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
52 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
53 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
54 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
55 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
57 * from $NetBSD: cpu_subr.c,v 1.1 2003/02/03 17:10:09 matt Exp $
61 #include <sys/param.h>
62 #include <sys/systm.h>
66 #include <sys/kernel.h>
68 #include <sys/sysctl.h>
70 #include <machine/bus.h>
71 #include <machine/cpu.h>
72 #include <machine/hid.h>
73 #include <machine/md_var.h>
74 #include <machine/smp.h>
75 #include <machine/spr.h>
77 static void cpu_6xx_setup(int cpuid, uint16_t vers);
78 static void cpu_970_setup(int cpuid, uint16_t vers);
79 static void cpu_booke_setup(int cpuid, uint16_t vers);
81 int powerpc_pow_enabled;
82 void (*cpu_idle_hook)(void) = NULL;
83 static void cpu_idle_60x(void);
84 static void cpu_idle_booke(void);
90 int features; /* Do not include PPC_FEATURE_32 or
91 * PPC_FEATURE_HAS_MMU */
92 void (*cpu_setup)(int cpuid, uint16_t vers);
94 #define REVFMT_MAJMIN 1 /* %u.%u */
95 #define REVFMT_HEX 2 /* 0x%04x */
96 #define REVFMT_DEC 3 /* %u */
97 static const struct cputab models[] = {
98 { "Motorola PowerPC 601", MPC601, REVFMT_DEC,
99 PPC_FEATURE_HAS_FPU | PPC_FEATURE_UNIFIED_CACHE, cpu_6xx_setup },
100 { "Motorola PowerPC 602", MPC602, REVFMT_DEC,
101 PPC_FEATURE_HAS_FPU, cpu_6xx_setup },
102 { "Motorola PowerPC 603", MPC603, REVFMT_MAJMIN,
103 PPC_FEATURE_HAS_FPU, cpu_6xx_setup },
104 { "Motorola PowerPC 603e", MPC603e, REVFMT_MAJMIN,
105 PPC_FEATURE_HAS_FPU, cpu_6xx_setup },
106 { "Motorola PowerPC 603ev", MPC603ev, REVFMT_MAJMIN,
107 PPC_FEATURE_HAS_FPU, cpu_6xx_setup },
108 { "Motorola PowerPC 604", MPC604, REVFMT_MAJMIN,
109 PPC_FEATURE_HAS_FPU, cpu_6xx_setup },
110 { "Motorola PowerPC 604ev", MPC604ev, REVFMT_MAJMIN,
111 PPC_FEATURE_HAS_FPU, cpu_6xx_setup },
112 { "Motorola PowerPC 620", MPC620, REVFMT_HEX,
113 PPC_FEATURE_64 | PPC_FEATURE_HAS_FPU, NULL },
114 { "Motorola PowerPC 750", MPC750, REVFMT_MAJMIN,
115 PPC_FEATURE_HAS_FPU, cpu_6xx_setup },
116 { "IBM PowerPC 750FX", IBM750FX, REVFMT_MAJMIN,
117 PPC_FEATURE_HAS_FPU, cpu_6xx_setup },
118 { "IBM PowerPC 970", IBM970, REVFMT_MAJMIN,
119 PPC_FEATURE_64 | PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU,
121 { "IBM PowerPC 970FX", IBM970FX, REVFMT_MAJMIN,
122 PPC_FEATURE_64 | PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU,
124 { "IBM PowerPC 970GX", IBM970GX, REVFMT_MAJMIN,
125 PPC_FEATURE_64 | PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU,
127 { "IBM PowerPC 970MP", IBM970MP, REVFMT_MAJMIN,
128 PPC_FEATURE_64 | PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU,
130 { "Motorola PowerPC 7400", MPC7400, REVFMT_MAJMIN,
131 PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU, cpu_6xx_setup },
132 { "Motorola PowerPC 7410", MPC7410, REVFMT_MAJMIN,
133 PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU, cpu_6xx_setup },
134 { "Motorola PowerPC 7450", MPC7450, REVFMT_MAJMIN,
135 PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU, cpu_6xx_setup },
136 { "Motorola PowerPC 7455", MPC7455, REVFMT_MAJMIN,
137 PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU, cpu_6xx_setup },
138 { "Motorola PowerPC 7457", MPC7457, REVFMT_MAJMIN,
139 PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU, cpu_6xx_setup },
140 { "Motorola PowerPC 7447A", MPC7447A, REVFMT_MAJMIN,
141 PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU, cpu_6xx_setup },
142 { "Motorola PowerPC 7448", MPC7448, REVFMT_MAJMIN,
143 PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU, cpu_6xx_setup },
144 { "Motorola PowerPC 8240", MPC8240, REVFMT_MAJMIN,
145 PPC_FEATURE_HAS_FPU, cpu_6xx_setup },
146 { "Motorola PowerPC 8245", MPC8245, REVFMT_MAJMIN,
147 PPC_FEATURE_HAS_FPU, cpu_6xx_setup },
148 { "Freescale e500v1 core", FSL_E500v1, REVFMT_MAJMIN,
149 0, cpu_booke_setup },
150 { "Freescale e500v2 core", FSL_E500v2, REVFMT_MAJMIN,
151 0, cpu_booke_setup },
152 { "Freescale e500mc core", FSL_E500mc, REVFMT_MAJMIN,
153 0, cpu_booke_setup },
154 { "Freescale e5500 core", FSL_E5500, REVFMT_MAJMIN,
155 0, cpu_booke_setup },
156 { "IBM Cell Broadband Engine", IBMCELLBE, REVFMT_MAJMIN,
157 PPC_FEATURE_64 | PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU,
159 { "Unknown PowerPC CPU", 0, REVFMT_HEX, 0, NULL },
162 static void cpu_6xx_print_cacheinfo(u_int, uint16_t);
163 static int cpu_feature_bit(SYSCTL_HANDLER_ARGS);
165 static char model[64];
166 SYSCTL_STRING(_hw, HW_MODEL, model, CTLFLAG_RD, model, 0, "");
168 int cpu_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU;
169 SYSCTL_OPAQUE(_hw, OID_AUTO, cpu_features, CTLTYPE_INT | CTLFLAG_RD,
170 &cpu_features, sizeof(cpu_features), "IX", "PowerPC CPU features");
172 /* Provide some user-friendly aliases for bits in cpu_features */
173 SYSCTL_PROC(_hw, OID_AUTO, floatingpoint, CTLTYPE_INT | CTLFLAG_RD,
174 0, PPC_FEATURE_HAS_FPU, cpu_feature_bit, "I",
175 "Floating point instructions executed in hardware");
176 SYSCTL_PROC(_hw, OID_AUTO, altivec, CTLTYPE_INT | CTLFLAG_RD,
177 0, PPC_FEATURE_HAS_ALTIVEC, cpu_feature_bit, "I", "CPU supports Altivec");
180 cpu_setup(u_int cpuid)
183 uint16_t vers, rev, revfmt;
185 const struct cputab *cp;
193 min = (pvr >> 0) & 0xff;
194 maj = min <= 4 ? 1 : 2;
200 maj = (pvr >> 4) & 0xf;
201 min = (pvr >> 0) & 0xf;
204 maj = (pvr >> 8) & 0xf;
205 min = (pvr >> 0) & 0xf;
208 for (cp = models; cp->version != 0; cp++) {
209 if (cp->version == vers)
215 if (rev == MPC750 && pvr == 15) {
216 name = "Motorola MPC755";
219 strncpy(model, name, sizeof(model) - 1);
221 printf("cpu%d: %s revision ", cpuid, name);
225 printf("%u.%u", maj, min);
228 printf("0x%04x", rev);
235 if (cpu_est_clockrate(0, &cps) == 0)
236 printf(", %jd.%02jd MHz", cps / 1000000, (cps / 10000) % 100);
239 cpu_features |= cp->features;
240 printf("cpu%d: Features %b\n", cpuid, cpu_features,
241 PPC_FEATURE_BITMASK);
246 if (cp->cpu_setup != NULL)
247 cp->cpu_setup(cpuid, vers);
250 /* Get current clock frequency for the given cpu id. */
252 cpu_est_clockrate(int cpu_id, uint64_t *cps)
257 vers = mfpvr() >> 16;
259 mtmsr(msr & ~PSL_EE);
271 mtspr(SPR_MMCR0, SPR_MMCR0_FC);
273 mtspr(SPR_MMCR0, SPR_MMCR0_PMC1SEL(PMCN_CYCLES));
275 *cps = (mfspr(SPR_PMC1) * 1000) + 4999;
276 mtspr(SPR_MMCR0, SPR_MMCR0_FC);
284 mtspr(SPR_970MMCR0, SPR_MMCR0_FC);
286 mtspr(SPR_970MMCR1, 0);
287 mtspr(SPR_970MMCRA, 0);
288 mtspr(SPR_970PMC1, 0);
290 SPR_970MMCR0_PMC1SEL(PMC970N_CYCLES));
294 mtspr(SPR_970MMCR0, SPR_MMCR0_FC);
295 *cps = (mfspr(SPR_970PMC1) * 1000) + 4999;
305 cpu_6xx_setup(int cpuid, uint16_t vers)
307 register_t hid0, pvr;
310 hid0 = mfspr(SPR_HID0);
314 * Configure power-saving mode.
327 /* Select DOZE mode. */
328 hid0 &= ~(HID0_DOZE | HID0_NAP | HID0_SLEEP);
329 hid0 |= HID0_DOZE | HID0_DPM;
330 powerpc_pow_enabled = 1;
338 /* Enable the 7450 branch caches */
339 hid0 |= HID0_SGE | HID0_BTIC;
340 hid0 |= HID0_LRSTK | HID0_FOLD | HID0_BHT;
341 /* Disable BTIC on 7450 Rev 2.0 or earlier and on 7457 */
342 if (((pvr >> 16) == MPC7450 && (pvr & 0xFFFF) <= 0x0200)
343 || (pvr >> 16) == MPC7457)
345 /* Select NAP mode. */
346 hid0 &= ~(HID0_DOZE | HID0_NAP | HID0_SLEEP);
347 hid0 |= HID0_NAP | HID0_DPM;
348 powerpc_pow_enabled = 1;
352 /* No power-saving mode is available. */ ;
358 hid0 &= ~HID0_DBP; /* XXX correct? */
359 hid0 |= HID0_EMCP | HID0_BTIC | HID0_SGE | HID0_BHT;
365 hid0 |= HID0_EMCP | HID0_BTIC | HID0_SGE | HID0_BHT;
371 mtspr(SPR_HID0, hid0);
374 cpu_6xx_print_cacheinfo(cpuid, vers);
382 bitmask = HID0_7450_BITMASK;
385 bitmask = HID0_BITMASK;
389 printf("cpu%d: HID0 %b\n", cpuid, (int)hid0, bitmask);
391 if (cpu_idle_hook == NULL)
392 cpu_idle_hook = cpu_idle_60x;
397 cpu_6xx_print_cacheinfo(u_int cpuid, uint16_t vers)
401 hid = mfspr(SPR_HID0);
402 printf("cpu%u: ", cpuid);
403 printf("L1 I-cache %sabled, ", (hid & HID0_ICE) ? "en" : "dis");
404 printf("L1 D-cache %sabled\n", (hid & HID0_DCE) ? "en" : "dis");
406 printf("cpu%u: ", cpuid);
407 if (mfspr(SPR_L2CR) & L2CR_L2E) {
412 printf("256KB L2 cache, ");
413 if (mfspr(SPR_L3CR) & L3CR_L3E)
414 printf("%cMB L3 backside cache",
415 mfspr(SPR_L3CR) & L3CR_L3SIZ ? '2' : '1');
417 printf("L3 cache disabled");
421 printf("512KB L2 cache\n");
424 switch (mfspr(SPR_L2CR) & L2CR_L2SIZ) {
435 printf("write-%s", (mfspr(SPR_L2CR) & L2CR_L2WT)
436 ? "through" : "back");
437 if (mfspr(SPR_L2CR) & L2CR_L2PE)
438 printf(", with parity");
439 printf(" backside cache\n");
443 printf("L2 cache disabled\n");
447 cpu_booke_setup(int cpuid, uint16_t vers)
452 hid0 = mfspr(SPR_HID0);
454 /* Programe power-management mode. */
455 hid0 &= ~(HID0_DOZE | HID0_NAP | HID0_SLEEP);
458 mtspr(SPR_HID0, hid0);
460 printf("cpu%d: HID0 %b\n", cpuid, (int)hid0, HID0_E500_BITMASK);
463 if (cpu_idle_hook == NULL)
464 cpu_idle_hook = cpu_idle_booke;
468 cpu_970_setup(int cpuid, uint16_t vers)
471 uint32_t hid0_hi, hid0_lo;
473 __asm __volatile ("mfspr %0,%2; clrldi %1,%0,32; srdi %0,%0,32;"
474 : "=r" (hid0_hi), "=r" (hid0_lo) : "K" (SPR_HID0));
476 /* Configure power-saving mode */
479 hid0_hi |= (HID0_DEEPNAP | HID0_NAP | HID0_DPM);
480 hid0_hi &= ~HID0_DOZE;
483 hid0_hi |= (HID0_NAP | HID0_DPM);
484 hid0_hi &= ~(HID0_DOZE | HID0_DEEPNAP);
487 powerpc_pow_enabled = 1;
489 __asm __volatile (" \
491 sldi %0,%0,32; or %0,%0,%1; \
493 mfspr %0, %2; mfspr %0, %2; mfspr %0, %2; \
494 mfspr %0, %2; mfspr %0, %2; mfspr %0, %2; \
496 :: "r" (hid0_hi), "r"(hid0_lo), "K" (SPR_HID0));
498 __asm __volatile ("mfspr %0,%1; srdi %0,%0,32;"
499 : "=r" (hid0_hi) : "K" (SPR_HID0));
500 printf("cpu%d: HID0 %b\n", cpuid, (int)(hid0_hi), HID0_970_BITMASK);
503 cpu_idle_hook = cpu_idle_60x;
507 cpu_feature_bit(SYSCTL_HANDLER_ARGS)
511 result = (cpu_features & arg2) ? 1 : 0;
513 return (sysctl_handle_int(oidp, &result, 0, req));
521 if ((mfmsr() & PSL_EE) != PSL_EE) {
522 struct thread *td = curthread;
523 printf("td msr %#lx\n", (u_long)td->td_md.md_saved_msr);
524 panic("ints disabled in idleproc!");
528 CTR2(KTR_SPARE2, "cpu_idle(%d) at %d",
531 if (cpu_idle_hook != NULL) {
543 CTR2(KTR_SPARE2, "cpu_idle(%d) at %d done",
548 cpu_idle_wakeup(int cpu)
559 if (!powerpc_pow_enabled)
563 vers = mfpvr() >> 16;
576 dssall; sync; mtmsr %0; isync"
577 :: "r"(msr | PSL_POW));
581 mtmsr(msr | PSL_POW);
596 /* Freescale E500 core RM section 6.4.1. */
597 __asm __volatile("msync; mtmsr %0; isync" ::