sys/powerpc/powerpc/cpu.c

   1 /*-
   2  * SPDX-License-Identifier: BSD-4-Clause AND BSD-2-Clause-FreeBSD
   3  *
   4  * Copyright (c) 2001 Matt Thomas.
   5  * Copyright (c) 2001 Tsubai Masanari.
   6  * Copyright (c) 1998, 1999, 2001 Internet Research Institute, Inc.
   7  * All rights reserved.
   8  *
   9  * Redistribution and use in source and binary forms, with or without
  10  * modification, are permitted provided that the following conditions
  11  * are met:
  12  * 1. Redistributions of source code must retain the above copyright
  13  *    notice, this list of conditions and the following disclaimer.
  14  * 2. Redistributions in binary form must reproduce the above copyright
  15  *    notice, this list of conditions and the following disclaimer in the
  16  *    documentation and/or other materials provided with the distribution.
  17  * 3. All advertising materials mentioning features or use of this software
  18  *    must display the following acknowledgement:
  19  *      This product includes software developed by
  20  *      Internet Research Institute, Inc.
  21  * 4. The name of the author may not be used to endorse or promote products
  22  *    derived from this software without specific prior written permission.
  23  *
  24  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  25  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  26  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  27  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  28  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  29  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  30  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  31  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  32  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  33  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  34  */
  35 /*-
  36  * Copyright (C) 2003 Benno Rice.
  37  * All rights reserved.
  38  *
  39  * Redistribution and use in source and binary forms, with or without
  40  * modification, are permitted provided that the following conditions
  41  * are met:
  42  * 1. Redistributions of source code must retain the above copyright
  43  *    notice, this list of conditions and the following disclaimer.
  44  * 2. Redistributions in binary form must reproduce the above copyright
  45  *    notice, this list of conditions and the following disclaimer in the
  46  *    documentation and/or other materials provided with the distribution.
  47  *
  48  * THIS SOFTWARE IS PROVIDED BY Benno Rice ``AS IS'' AND ANY EXPRESS OR
  49  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  50  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  51  * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  52  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
  53  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
  54  * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
  55  * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
  56  * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
  57  * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  58  *
  59  * from $NetBSD: cpu_subr.c,v 1.1 2003/02/03 17:10:09 matt Exp $
  60  * $FreeBSD$
  61  */
  62
  63 #include <sys/param.h>
  64 #include <sys/systm.h>
  65 #include <sys/bus.h>
  66 #include <sys/conf.h>
  67 #include <sys/cpu.h>
  68 #include <sys/kernel.h>
  69 #include <sys/proc.h>
  70 #include <sys/sysctl.h>
  71 #include <sys/sched.h>
  72 #include <sys/smp.h>
  73
  74 #include <machine/bus.h>
  75 #include <machine/cpu.h>
  76 #include <machine/hid.h>
  77 #include <machine/md_var.h>
  78 #include <machine/smp.h>
  79 #include <machine/spr.h>
  80
  81 #include <dev/ofw/openfirm.h>
  82
  83 static void     cpu_6xx_setup(int cpuid, uint16_t vers);
  84 static void     cpu_970_setup(int cpuid, uint16_t vers);
  85 static void     cpu_booke_setup(int cpuid, uint16_t vers);
  86 static void     cpu_powerx_setup(int cpuid, uint16_t vers);
  87
  88 int powerpc_pow_enabled;
  89 void (*cpu_idle_hook)(sbintime_t) = NULL;
  90 static void     cpu_idle_60x(sbintime_t);
  91 static void     cpu_idle_booke(sbintime_t);
  92 #if defined(__powerpc64__) && defined(AIM)
  93 static void     cpu_idle_powerx(sbintime_t);
  94 #endif
  95
  96 struct cputab {
  97         const char      *name;
  98         uint16_t        version;
  99         uint16_t        revfmt;
 100         int             features;       /* Do not include PPC_FEATURE_32 or
 101                                          * PPC_FEATURE_HAS_MMU */
 102         int             features2;
 103         void            (*cpu_setup)(int cpuid, uint16_t vers);
 104 };
 105 #define REVFMT_MAJMIN   1       /* %u.%u */
 106 #define REVFMT_HEX      2       /* 0x%04x */
 107 #define REVFMT_DEC      3       /* %u */
 108 static const struct cputab models[] = {
 109         { "Motorola PowerPC 601",       MPC601,         REVFMT_DEC,
 110            PPC_FEATURE_HAS_FPU | PPC_FEATURE_UNIFIED_CACHE, 0, cpu_6xx_setup },
 111         { "Motorola PowerPC 602",       MPC602,         REVFMT_DEC,
 112            PPC_FEATURE_HAS_FPU, 0, cpu_6xx_setup },
 113         { "Motorola PowerPC 603",       MPC603,         REVFMT_MAJMIN,
 114            PPC_FEATURE_HAS_FPU, 0, cpu_6xx_setup },
 115         { "Motorola PowerPC 603e",      MPC603e,        REVFMT_MAJMIN,
 116            PPC_FEATURE_HAS_FPU, 0, cpu_6xx_setup },
 117         { "Motorola PowerPC 603ev",     MPC603ev,       REVFMT_MAJMIN,
 118            PPC_FEATURE_HAS_FPU, 0, cpu_6xx_setup },
 119         { "Motorola PowerPC 604",       MPC604,         REVFMT_MAJMIN,
 120            PPC_FEATURE_HAS_FPU, 0, cpu_6xx_setup },
 121         { "Motorola PowerPC 604ev",     MPC604ev,       REVFMT_MAJMIN,
 122            PPC_FEATURE_HAS_FPU, 0, cpu_6xx_setup },
 123         { "Motorola PowerPC 620",       MPC620,         REVFMT_HEX,
 124            PPC_FEATURE_64 | PPC_FEATURE_HAS_FPU, 0, NULL },
 125         { "Motorola PowerPC 750",       MPC750,         REVFMT_MAJMIN,
 126            PPC_FEATURE_HAS_FPU, 0, cpu_6xx_setup },
 127         { "IBM PowerPC 750FX",          IBM750FX,       REVFMT_MAJMIN,
 128            PPC_FEATURE_HAS_FPU, 0, cpu_6xx_setup },
 129         { "IBM PowerPC 970",            IBM970,         REVFMT_MAJMIN,
 130            PPC_FEATURE_64 | PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU,
 131            0, cpu_970_setup },
 132         { "IBM PowerPC 970FX",          IBM970FX,       REVFMT_MAJMIN,
 133            PPC_FEATURE_64 | PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU,
 134            0, cpu_970_setup },
 135         { "IBM PowerPC 970GX",          IBM970GX,       REVFMT_MAJMIN,
 136            PPC_FEATURE_64 | PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU,
 137            0, cpu_970_setup },
 138         { "IBM PowerPC 970MP",          IBM970MP,       REVFMT_MAJMIN,
 139            PPC_FEATURE_64 | PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU,
 140            0, cpu_970_setup },
 141         { "IBM POWER4",         IBMPOWER4,      REVFMT_MAJMIN,
 142            PPC_FEATURE_64 | PPC_FEATURE_HAS_FPU | PPC_FEATURE_POWER4, 0, NULL },
 143         { "IBM POWER4+",        IBMPOWER4PLUS,  REVFMT_MAJMIN,
 144            PPC_FEATURE_64 | PPC_FEATURE_HAS_FPU | PPC_FEATURE_POWER4, 0, NULL },
 145         { "IBM POWER5",         IBMPOWER5,      REVFMT_MAJMIN,
 146            PPC_FEATURE_64 | PPC_FEATURE_HAS_FPU | PPC_FEATURE_POWER4 |
 147            PPC_FEATURE_SMT | PPC_FEATURE_ICACHE_SNOOP, 0, NULL },
 148         { "IBM POWER5+",        IBMPOWER5PLUS,  REVFMT_MAJMIN,
 149            PPC_FEATURE_64 | PPC_FEATURE_HAS_FPU | PPC_FEATURE_POWER5_PLUS |
 150            PPC_FEATURE_SMT | PPC_FEATURE_ICACHE_SNOOP, 0, NULL },
 151         { "IBM POWER6",         IBMPOWER6,      REVFMT_MAJMIN,
 152            PPC_FEATURE_64 | PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU |
 153            PPC_FEATURE_SMT | PPC_FEATURE_ICACHE_SNOOP | PPC_FEATURE_ARCH_2_05 |
 154            PPC_FEATURE_TRUE_LE, 0, NULL },
 155         { "IBM POWER7",         IBMPOWER7,      REVFMT_MAJMIN,
 156            PPC_FEATURE_64 | PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU |
 157            PPC_FEATURE_SMT | PPC_FEATURE_ARCH_2_05 | PPC_FEATURE_ARCH_2_06 |
 158            PPC_FEATURE_HAS_VSX | PPC_FEATURE_TRUE_LE, PPC_FEATURE2_DSCR, NULL },
 159         { "IBM POWER7+",        IBMPOWER7PLUS,  REVFMT_MAJMIN,
 160            PPC_FEATURE_64 | PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU |
 161            PPC_FEATURE_SMT | PPC_FEATURE_ARCH_2_05 | PPC_FEATURE_ARCH_2_06 |
 162            PPC_FEATURE_HAS_VSX, PPC_FEATURE2_DSCR, NULL },
 163         { "IBM POWER8E",        IBMPOWER8E,     REVFMT_MAJMIN,
 164            PPC_FEATURE_64 | PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU |
 165            PPC_FEATURE_SMT | PPC_FEATURE_ICACHE_SNOOP | PPC_FEATURE_ARCH_2_05 |
 166            PPC_FEATURE_ARCH_2_06 | PPC_FEATURE_HAS_VSX | PPC_FEATURE_TRUE_LE,
 167            PPC_FEATURE2_ARCH_2_07 | PPC_FEATURE2_HTM | PPC_FEATURE2_DSCR |
 168            PPC_FEATURE2_ISEL | PPC_FEATURE2_TAR | PPC_FEATURE2_HAS_VEC_CRYPTO |
 169            PPC_FEATURE2_HTM_NOSC, cpu_powerx_setup },
 170         { "IBM POWER8",         IBMPOWER8,      REVFMT_MAJMIN,
 171            PPC_FEATURE_64 | PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU |
 172            PPC_FEATURE_SMT | PPC_FEATURE_ICACHE_SNOOP | PPC_FEATURE_ARCH_2_05 |
 173            PPC_FEATURE_ARCH_2_06 | PPC_FEATURE_HAS_VSX | PPC_FEATURE_TRUE_LE,
 174            PPC_FEATURE2_ARCH_2_07 | PPC_FEATURE2_HTM | PPC_FEATURE2_DSCR |
 175            PPC_FEATURE2_ISEL | PPC_FEATURE2_TAR | PPC_FEATURE2_HAS_VEC_CRYPTO |
 176            PPC_FEATURE2_HTM_NOSC, cpu_powerx_setup },
 177         { "IBM POWER9",         IBMPOWER9,      REVFMT_MAJMIN,
 178            PPC_FEATURE_64 | PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU |
 179            PPC_FEATURE_SMT | PPC_FEATURE_ICACHE_SNOOP | PPC_FEATURE_ARCH_2_05 |
 180            PPC_FEATURE_ARCH_2_06 | PPC_FEATURE_HAS_VSX | PPC_FEATURE_TRUE_LE,
 181            PPC_FEATURE2_ARCH_2_07 | PPC_FEATURE2_HTM | PPC_FEATURE2_DSCR |
 182            PPC_FEATURE2_ISEL | PPC_FEATURE2_TAR | PPC_FEATURE2_HAS_VEC_CRYPTO |
 183            PPC_FEATURE2_ARCH_3_00 | PPC_FEATURE2_HAS_IEEE128 |
 184            PPC_FEATURE2_DARN, NULL },
 185         { "Motorola PowerPC 7400",      MPC7400,        REVFMT_MAJMIN,
 186            PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU, 0, cpu_6xx_setup },
 187         { "Motorola PowerPC 7410",      MPC7410,        REVFMT_MAJMIN,
 188            PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU, 0, cpu_6xx_setup },
 189         { "Motorola PowerPC 7450",      MPC7450,        REVFMT_MAJMIN,
 190            PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU, 0, cpu_6xx_setup },
 191         { "Motorola PowerPC 7455",      MPC7455,        REVFMT_MAJMIN,
 192            PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU, 0, cpu_6xx_setup },
 193         { "Motorola PowerPC 7457",      MPC7457,        REVFMT_MAJMIN,
 194            PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU, 0, cpu_6xx_setup },
 195         { "Motorola PowerPC 7447A",     MPC7447A,       REVFMT_MAJMIN,
 196            PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU, 0, cpu_6xx_setup },
 197         { "Motorola PowerPC 7448",      MPC7448,        REVFMT_MAJMIN,
 198            PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU, 0, cpu_6xx_setup },
 199         { "Motorola PowerPC 8240",      MPC8240,        REVFMT_MAJMIN,
 200            PPC_FEATURE_HAS_FPU, 0, cpu_6xx_setup },
 201         { "Motorola PowerPC 8245",      MPC8245,        REVFMT_MAJMIN,
 202            PPC_FEATURE_HAS_FPU, 0, cpu_6xx_setup },
 203         { "Freescale e500v1 core",      FSL_E500v1,     REVFMT_MAJMIN,
 204            PPC_FEATURE_HAS_SPE | PPC_FEATURE_HAS_EFP_SINGLE | PPC_FEATURE_BOOKE,
 205            PPC_FEATURE2_ISEL, cpu_booke_setup },
 206         { "Freescale e500v2 core",      FSL_E500v2,     REVFMT_MAJMIN,
 207            PPC_FEATURE_HAS_SPE | PPC_FEATURE_BOOKE |
 208            PPC_FEATURE_HAS_EFP_SINGLE | PPC_FEATURE_HAS_EFP_DOUBLE,
 209            PPC_FEATURE2_ISEL, cpu_booke_setup },
 210         { "Freescale e500mc core",      FSL_E500mc,     REVFMT_MAJMIN,
 211            PPC_FEATURE_HAS_FPU | PPC_FEATURE_BOOKE | PPC_FEATURE_ARCH_2_05 |
 212            PPC_FEATURE_ARCH_2_06, PPC_FEATURE2_ISEL,
 213            cpu_booke_setup },
 214         { "Freescale e5500 core",       FSL_E5500,      REVFMT_MAJMIN,
 215            PPC_FEATURE_64 | PPC_FEATURE_HAS_FPU | PPC_FEATURE_BOOKE |
 216            PPC_FEATURE_ARCH_2_05 | PPC_FEATURE_ARCH_2_06,
 217            PPC_FEATURE2_ISEL, cpu_booke_setup },
 218         { "Freescale e6500 core",       FSL_E6500,      REVFMT_MAJMIN,
 219            PPC_FEATURE_64 | PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU |
 220            PPC_FEATURE_BOOKE | PPC_FEATURE_ARCH_2_05 | PPC_FEATURE_ARCH_2_06,
 221            PPC_FEATURE2_ISEL, cpu_booke_setup },
 222         { "IBM Cell Broadband Engine",  IBMCELLBE,      REVFMT_MAJMIN,
 223            PPC_FEATURE_64 | PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU |
 224            PPC_FEATURE_CELL | PPC_FEATURE_SMT, 0, NULL},
 225         { "Unknown PowerPC CPU",        0,              REVFMT_HEX, 0, 0, NULL },
 226 };
 227
 228 static void     cpu_6xx_print_cacheinfo(u_int, uint16_t);
 229 static int      cpu_feature_bit(SYSCTL_HANDLER_ARGS);
 230
 231 static char model[64];
 232 SYSCTL_STRING(_hw, HW_MODEL, model, CTLFLAG_RD, model, 0, "");
 233
 234 static const struct cputab      *cput;
 235
 236 u_long cpu_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU;
 237 u_long cpu_features2 = 0;
 238 SYSCTL_OPAQUE(_hw, OID_AUTO, cpu_features, CTLFLAG_RD,
 239     &cpu_features, sizeof(cpu_features), "LX", "PowerPC CPU features");
 240 SYSCTL_OPAQUE(_hw, OID_AUTO, cpu_features2, CTLFLAG_RD,
 241     &cpu_features2, sizeof(cpu_features2), "LX", "PowerPC CPU features 2");
 242
 243 /* Provide some user-friendly aliases for bits in cpu_features */
 244 SYSCTL_PROC(_hw, OID_AUTO, floatingpoint, CTLTYPE_INT | CTLFLAG_RD,
 245     0, PPC_FEATURE_HAS_FPU, cpu_feature_bit, "I",
 246     "Floating point instructions executed in hardware");
 247 SYSCTL_PROC(_hw, OID_AUTO, altivec, CTLTYPE_INT | CTLFLAG_RD,
 248     0, PPC_FEATURE_HAS_ALTIVEC, cpu_feature_bit, "I", "CPU supports Altivec");
 249
 250 /*
 251  * Phase 1 (early) CPU setup.  Setup the cpu_features/cpu_features2 variables,
 252  * so they can be used during platform and MMU bringup.
 253  */
 254 void
 255 cpu_feature_setup()
 256 {
 257         u_int           pvr;
 258         uint16_t        vers;
 259         const struct    cputab *cp;
 260
 261         pvr = mfpvr();
 262         vers = pvr >> 16;
 263         for (cp = models; cp->version != 0; cp++) {
 264                 if (cp->version == vers)
 265                         break;
 266         }
 267
 268         cput = cp;
 269         cpu_features |= cp->features;
 270         cpu_features2 |= cp->features2;
 271 }
 272
 273
 274 void
 275 cpu_setup(u_int cpuid)
 276 {
 277         uint64_t        cps;
 278         const char      *name;
 279         u_int           maj, min, pvr;
 280         uint16_t        rev, revfmt, vers;
 281
 282         pvr = mfpvr();
 283         vers = pvr >> 16;
 284         rev = pvr;
 285         switch (vers) {
 286                 case MPC7410:
 287                         min = (pvr >> 0) & 0xff;
 288                         maj = min <= 4 ? 1 : 2;
 289                         break;
 290                 case FSL_E500v1:
 291                 case FSL_E500v2:
 292                 case FSL_E500mc:
 293                 case FSL_E5500:
 294                         maj = (pvr >>  4) & 0xf;
 295                         min = (pvr >>  0) & 0xf;
 296                         break;
 297                 default:
 298                         maj = (pvr >>  8) & 0xf;
 299                         min = (pvr >>  0) & 0xf;
 300         }
 301
 302         revfmt = cput->revfmt;
 303         name = cput->name;
 304         if (rev == MPC750 && pvr == 15) {
 305                 name = "Motorola MPC755";
 306                 revfmt = REVFMT_HEX;
 307         }
 308         strncpy(model, name, sizeof(model) - 1);
 309
 310         printf("cpu%d: %s revision ", cpuid, name);
 311
 312         switch (revfmt) {
 313                 case REVFMT_MAJMIN:
 314                         printf("%u.%u", maj, min);
 315                         break;
 316                 case REVFMT_HEX:
 317                         printf("0x%04x", rev);
 318                         break;
 319                 case REVFMT_DEC:
 320                         printf("%u", rev);
 321                         break;
 322         }
 323
 324         if (cpu_est_clockrate(0, &cps) == 0)
 325                 printf(", %jd.%02jd MHz", cps / 1000000, (cps / 10000) % 100);
 326         printf("\n");
 327
 328         printf("cpu%d: Features %b\n", cpuid, (int)cpu_features,
 329             PPC_FEATURE_BITMASK);
 330         if (cpu_features2 != 0)
 331                 printf("cpu%d: Features2 %b\n", cpuid, (int)cpu_features2,
 332                     PPC_FEATURE2_BITMASK);
 333
 334         /*
 335          * Configure CPU
 336          */
 337         if (cput->cpu_setup != NULL)
 338                 cput->cpu_setup(cpuid, vers);
 339 }
 340
 341 /* Get current clock frequency for the given cpu id. */
 342 int
 343 cpu_est_clockrate(int cpu_id, uint64_t *cps)
 344 {
 345         uint16_t        vers;
 346         register_t      msr;
 347         phandle_t       cpu, dev, root;
 348         int             res  = 0;
 349         char            buf[8];
 350
 351         vers = mfpvr() >> 16;
 352         msr = mfmsr();
 353         mtmsr(msr & ~PSL_EE);
 354
 355         switch (vers) {
 356                 case MPC7450:
 357                 case MPC7455:
 358                 case MPC7457:
 359                 case MPC750:
 360                 case IBM750FX:
 361                 case MPC7400:
 362                 case MPC7410:
 363                 case MPC7447A:
 364                 case MPC7448:
 365                         mtspr(SPR_MMCR0, SPR_MMCR0_FC);
 366                         mtspr(SPR_PMC1, 0);
 367                         mtspr(SPR_MMCR0, SPR_MMCR0_PMC1SEL(PMCN_CYCLES));
 368                         DELAY(1000);
 369                         *cps = (mfspr(SPR_PMC1) * 1000) + 4999;
 370                         mtspr(SPR_MMCR0, SPR_MMCR0_FC);
 371
 372                         mtmsr(msr);
 373                         return (0);
 374                 case IBM970:
 375                 case IBM970FX:
 376                 case IBM970MP:
 377                         isync();
 378                         mtspr(SPR_970MMCR0, SPR_MMCR0_FC);
 379                         isync();
 380                         mtspr(SPR_970MMCR1, 0);
 381                         mtspr(SPR_970MMCRA, 0);
 382                         mtspr(SPR_970PMC1, 0);
 383                         mtspr(SPR_970MMCR0,
 384                             SPR_970MMCR0_PMC1SEL(PMC970N_CYCLES));
 385                         isync();
 386                         DELAY(1000);
 387                         powerpc_sync();
 388                         mtspr(SPR_970MMCR0, SPR_MMCR0_FC);
 389                         *cps = (mfspr(SPR_970PMC1) * 1000) + 4999;
 390
 391                         mtmsr(msr);
 392                         return (0);
 393
 394                 default:
 395                         root = OF_peer(0);
 396                         if (root == 0)
 397                                 return (ENXIO);
 398
 399                         dev = OF_child(root);
 400                         while (dev != 0) {
 401                                 res = OF_getprop(dev, "name", buf, sizeof(buf));
 402                                 if (res > 0 && strcmp(buf, "cpus") == 0)
 403                                         break;
 404                                 dev = OF_peer(dev);
 405                         }
 406                         cpu = OF_child(dev);
 407                         while (cpu != 0) {
 408                                 res = OF_getprop(cpu, "device_type", buf,
 409                                                 sizeof(buf));
 410                                 if (res > 0 && strcmp(buf, "cpu") == 0)
 411                                         break;
 412                                 cpu = OF_peer(cpu);
 413                         }
 414                         if (cpu == 0)
 415                                 return (ENOENT);
 416                         if (OF_getprop(cpu, "ibm,extended-clock-frequency",
 417                             cps, sizeof(*cps)) >= 0) {
 418                                 return (0);
 419                         } else if (OF_getprop(cpu, "clock-frequency", cps,
 420                             sizeof(cell_t)) >= 0) {
 421                                 *cps >>= 32;
 422                                 return (0);
 423                         } else {
 424                                 return (ENOENT);
 425                         }
 426         }
 427 }
 428
 429 void
 430 cpu_6xx_setup(int cpuid, uint16_t vers)
 431 {
 432         register_t hid0, pvr;
 433         const char *bitmask;
 434
 435         hid0 = mfspr(SPR_HID0);
 436         pvr = mfpvr();
 437
 438         /*
 439          * Configure power-saving mode.
 440          */
 441         switch (vers) {
 442                 case MPC603:
 443                 case MPC603e:
 444                 case MPC603ev:
 445                 case MPC604ev:
 446                 case MPC750:
 447                 case IBM750FX:
 448                 case MPC7400:
 449                 case MPC7410:
 450                 case MPC8240:
 451                 case MPC8245:
 452                         /* Select DOZE mode. */
 453                         hid0 &= ~(HID0_DOZE | HID0_NAP | HID0_SLEEP);
 454                         hid0 |= HID0_DOZE | HID0_DPM;
 455                         powerpc_pow_enabled = 1;
 456                         break;
 457
 458                 case MPC7448:
 459                 case MPC7447A:
 460                 case MPC7457:
 461                 case MPC7455:
 462                 case MPC7450:
 463                         /* Enable the 7450 branch caches */
 464                         hid0 |= HID0_SGE | HID0_BTIC;
 465                         hid0 |= HID0_LRSTK | HID0_FOLD | HID0_BHT;
 466                         /* Disable BTIC on 7450 Rev 2.0 or earlier and on 7457 */
 467                         if (((pvr >> 16) == MPC7450 && (pvr & 0xFFFF) <= 0x0200)
 468                                         || (pvr >> 16) == MPC7457)
 469                                 hid0 &= ~HID0_BTIC;
 470                         /* Select NAP mode. */
 471                         hid0 &= ~(HID0_DOZE | HID0_NAP | HID0_SLEEP);
 472                         hid0 |= HID0_NAP | HID0_DPM;
 473                         powerpc_pow_enabled = 1;
 474                         break;
 475
 476                 default:
 477                         /* No power-saving mode is available. */ ;
 478         }
 479
 480         switch (vers) {
 481                 case IBM750FX:
 482                 case MPC750:
 483                         hid0 &= ~HID0_DBP;              /* XXX correct? */
 484                         hid0 |= HID0_EMCP | HID0_BTIC | HID0_SGE | HID0_BHT;
 485                         break;
 486
 487                 case MPC7400:
 488                 case MPC7410:
 489                         hid0 &= ~HID0_SPD;
 490                         hid0 |= HID0_EMCP | HID0_BTIC | HID0_SGE | HID0_BHT;
 491                         hid0 |= HID0_EIEC;
 492                         break;
 493
 494         }
 495
 496         mtspr(SPR_HID0, hid0);
 497
 498         if (bootverbose)
 499                 cpu_6xx_print_cacheinfo(cpuid, vers);
 500
 501         switch (vers) {
 502                 case MPC7447A:
 503                 case MPC7448:
 504                 case MPC7450:
 505                 case MPC7455:
 506                 case MPC7457:
 507                         bitmask = HID0_7450_BITMASK;
 508                         break;
 509                 default:
 510                         bitmask = HID0_BITMASK;
 511                         break;
 512         }
 513
 514         printf("cpu%d: HID0 %b\n", cpuid, (int)hid0, bitmask);
 515
 516         if (cpu_idle_hook == NULL)
 517                 cpu_idle_hook = cpu_idle_60x;
 518 }
 519
 520
 521 static void
 522 cpu_6xx_print_cacheinfo(u_int cpuid, uint16_t vers)
 523 {
 524         register_t hid;
 525
 526         hid = mfspr(SPR_HID0);
 527         printf("cpu%u: ", cpuid);
 528         printf("L1 I-cache %sabled, ", (hid & HID0_ICE) ? "en" : "dis");
 529         printf("L1 D-cache %sabled\n", (hid & HID0_DCE) ? "en" : "dis");
 530
 531         printf("cpu%u: ", cpuid);
 532         if (mfspr(SPR_L2CR) & L2CR_L2E) {
 533                 switch (vers) {
 534                 case MPC7450:
 535                 case MPC7455:
 536                 case MPC7457:
 537                         printf("256KB L2 cache, ");
 538                         if (mfspr(SPR_L3CR) & L3CR_L3E)
 539                                 printf("%cMB L3 backside cache",
 540                                     mfspr(SPR_L3CR) & L3CR_L3SIZ ? '2' : '1');
 541                         else
 542                                 printf("L3 cache disabled");
 543                         printf("\n");
 544                         break;
 545                 case IBM750FX:
 546                         printf("512KB L2 cache\n");
 547                         break;
 548                 default:
 549                         switch (mfspr(SPR_L2CR) & L2CR_L2SIZ) {
 550                         case L2SIZ_256K:
 551                                 printf("256KB ");
 552                                 break;
 553                         case L2SIZ_512K:
 554                                 printf("512KB ");
 555                                 break;
 556                         case L2SIZ_1M:
 557                                 printf("1MB ");
 558                                 break;
 559                         }
 560                         printf("write-%s", (mfspr(SPR_L2CR) & L2CR_L2WT)
 561                             ? "through" : "back");
 562                         if (mfspr(SPR_L2CR) & L2CR_L2PE)
 563                                 printf(", with parity");
 564                         printf(" backside cache\n");
 565                         break;
 566                 }
 567         } else
 568                 printf("L2 cache disabled\n");
 569 }
 570
 571 static void
 572 cpu_booke_setup(int cpuid, uint16_t vers)
 573 {
 574 #ifdef BOOKE_E500
 575         register_t hid0;
 576         const char *bitmask;
 577
 578         hid0 = mfspr(SPR_HID0);
 579
 580         switch (vers) {
 581         case FSL_E500mc:
 582                 bitmask = HID0_E500MC_BITMASK;
 583                 break;
 584         case FSL_E5500:
 585         case FSL_E6500:
 586                 bitmask = HID0_E5500_BITMASK;
 587                 break;
 588         case FSL_E500v1:
 589         case FSL_E500v2:
 590                 /* Only e500v1/v2 support HID0 power management setup. */
 591
 592                 /* Program power-management mode. */
 593                 hid0 &= ~(HID0_DOZE | HID0_NAP | HID0_SLEEP);
 594                 hid0 |= HID0_DOZE;
 595
 596                 mtspr(SPR_HID0, hid0);
 597         default:
 598                 bitmask = HID0_E500_BITMASK;
 599                 break;
 600         }
 601         printf("cpu%d: HID0 %b\n", cpuid, (int)hid0, bitmask);
 602 #endif
 603
 604         if (cpu_idle_hook == NULL)
 605                 cpu_idle_hook = cpu_idle_booke;
 606 }
 607
 608 static void
 609 cpu_970_setup(int cpuid, uint16_t vers)
 610 {
 611 #ifdef AIM
 612         uint32_t hid0_hi, hid0_lo;
 613
 614         __asm __volatile ("mfspr %0,%2; clrldi %1,%0,32; srdi %0,%0,32;"
 615             : "=r" (hid0_hi), "=r" (hid0_lo) : "K" (SPR_HID0));
 616
 617         /* Configure power-saving mode */
 618         switch (vers) {
 619         case IBM970MP:
 620                 hid0_hi |= (HID0_DEEPNAP | HID0_NAP | HID0_DPM);
 621                 hid0_hi &= ~HID0_DOZE;
 622                 break;
 623         default:
 624                 hid0_hi |= (HID0_NAP | HID0_DPM);
 625                 hid0_hi &= ~(HID0_DOZE | HID0_DEEPNAP);
 626                 break;
 627         }
 628         powerpc_pow_enabled = 1;
 629
 630         __asm __volatile (" \
 631                 sync; isync;                                    \
 632                 sldi    %0,%0,32; or %0,%0,%1;                  \
 633                 mtspr   %2, %0;                                 \
 634                 mfspr   %0, %2; mfspr   %0, %2; mfspr   %0, %2; \
 635                 mfspr   %0, %2; mfspr   %0, %2; mfspr   %0, %2; \
 636                 sync; isync"
 637             :: "r" (hid0_hi), "r"(hid0_lo), "K" (SPR_HID0));
 638
 639         __asm __volatile ("mfspr %0,%1; srdi %0,%0,32;"
 640             : "=r" (hid0_hi) : "K" (SPR_HID0));
 641         printf("cpu%d: HID0 %b\n", cpuid, (int)(hid0_hi), HID0_970_BITMASK);
 642 #endif
 643
 644         cpu_idle_hook = cpu_idle_60x;
 645 }
 646
 647 static void
 648 cpu_powerx_setup(int cpuid, uint16_t vers)
 649 {
 650
 651 #if defined(__powerpc64__) && defined(AIM)
 652         if ((mfmsr() & PSL_HV) == 0)
 653                 return;
 654
 655         /* Configure power-saving */
 656         switch (vers) {
 657         case IBMPOWER8:
 658         case IBMPOWER8E:
 659         case IBMPOWER9:
 660                 mtspr(SPR_LPCR, mfspr(SPR_LPCR) | LPCR_PECE_WAKESET);
 661                 isync();
 662                 break;
 663         default:
 664                 return;
 665         }
 666
 667         cpu_idle_hook = cpu_idle_powerx;
 668 #endif
 669 }
 670
 671 static int
 672 cpu_feature_bit(SYSCTL_HANDLER_ARGS)
 673 {
 674         int result;
 675
 676         result = (cpu_features & arg2) ? 1 : 0;
 677
 678         return (sysctl_handle_int(oidp, &result, 0, req));
 679 }
 680
 681 void
 682 cpu_idle(int busy)
 683 {
 684         sbintime_t sbt = -1;
 685
 686 #ifdef INVARIANTS
 687         if ((mfmsr() & PSL_EE) != PSL_EE) {
 688                 struct thread *td = curthread;
 689                 printf("td msr %#lx\n", (u_long)td->td_md.md_saved_msr);
 690                 panic("ints disabled in idleproc!");
 691         }
 692 #endif
 693
 694         CTR2(KTR_SPARE2, "cpu_idle(%d) at %d",
 695             busy, curcpu);
 696
 697         if (cpu_idle_hook != NULL) {
 698                 if (!busy) {
 699                         critical_enter();
 700                         sbt = cpu_idleclock();
 701                 }
 702                 cpu_idle_hook(sbt);
 703                 if (!busy) {
 704                         cpu_activeclock();
 705                         critical_exit();
 706                 }
 707         }
 708
 709         CTR2(KTR_SPARE2, "cpu_idle(%d) at %d done",
 710             busy, curcpu);
 711 }
 712
 713 static void
 714 cpu_idle_60x(sbintime_t sbt)
 715 {
 716         register_t msr;
 717         uint16_t vers;
 718
 719         if (!powerpc_pow_enabled)
 720                 return;
 721
 722         msr = mfmsr();
 723         vers = mfpvr() >> 16;
 724
 725 #ifdef AIM
 726         switch (vers) {
 727         case IBM970:
 728         case IBM970FX:
 729         case IBM970MP:
 730         case MPC7447A:
 731         case MPC7448:
 732         case MPC7450:
 733         case MPC7455:
 734         case MPC7457:
 735                 __asm __volatile("\
 736                             dssall; sync; mtmsr %0; isync"
 737                             :: "r"(msr | PSL_POW));
 738                 break;
 739         default:
 740                 powerpc_sync();
 741                 mtmsr(msr | PSL_POW);
 742                 break;
 743         }
 744 #endif
 745 }
 746
 747 static void
 748 cpu_idle_booke(sbintime_t sbt)
 749 {
 750         register_t msr;
 751         uint16_t vers;
 752
 753         msr = mfmsr();
 754         vers = mfpvr() >> 16;
 755
 756 #ifdef BOOKE
 757         switch (vers) {
 758         case FSL_E500mc:
 759         case FSL_E5500:
 760         case FSL_E6500:
 761                 /*
 762                  * Base binutils doesn't know what the 'wait' instruction is, so
 763                  * use the opcode encoding here.
 764                  */
 765                 __asm __volatile(".long 0x7c00007c");
 766                 break;
 767         default:
 768                 powerpc_sync();
 769                 mtmsr(msr | PSL_WE);
 770                 break;
 771         }
 772 #endif
 773 }
 774
 775 #if defined(__powerpc64__) && defined(AIM)
 776 static void
 777 cpu_idle_powerx(sbintime_t sbt)
 778 {
 779
 780         /* Sleeping when running on one cpu gives no advantages - avoid it */
 781         if (smp_started == 0)
 782                 return;
 783
 784         spinlock_enter();
 785         if (sched_runnable()) {
 786                 spinlock_exit();
 787                 return;
 788         }
 789
 790         if (can_wakeup == 0)
 791                 can_wakeup = 1;
 792         mb();
 793
 794         enter_idle_powerx();
 795         spinlock_exit();
 796 }
 797 #endif
 798
 799 int
 800 cpu_idle_wakeup(int cpu)
 801 {
 802
 803         return (0);
 804 }