sys/powerpc/powerpc/cpu.c

   1 /*-
   2  * Copyright (c) 2001 Matt Thomas.
   3  * Copyright (c) 2001 Tsubai Masanari.
   4  * Copyright (c) 1998, 1999, 2001 Internet Research Institute, Inc.
   5  * All rights reserved.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  * 1. Redistributions of source code must retain the above copyright
  11  *    notice, this list of conditions and the following disclaimer.
  12  * 2. Redistributions in binary form must reproduce the above copyright
  13  *    notice, this list of conditions and the following disclaimer in the
  14  *    documentation and/or other materials provided with the distribution.
  15  * 3. All advertising materials mentioning features or use of this software
  16  *    must display the following acknowledgement:
  17  *      This product includes software developed by
  18  *      Internet Research Institute, Inc.
  19  * 4. The name of the author may not be used to endorse or promote products
  20  *    derived from this software without specific prior written permission.
  21  *
  22  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  23  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  24  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  25  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  26  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  27  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33 /*-
  34  * Copyright (C) 2003 Benno Rice.
  35  * All rights reserved.
  36  *
  37  * Redistribution and use in source and binary forms, with or without
  38  * modification, are permitted provided that the following conditions
  39  * are met:
  40  * 1. Redistributions of source code must retain the above copyright
  41  *    notice, this list of conditions and the following disclaimer.
  42  * 2. Redistributions in binary form must reproduce the above copyright
  43  *    notice, this list of conditions and the following disclaimer in the
  44  *    documentation and/or other materials provided with the distribution.
  45  *
  46  * THIS SOFTWARE IS PROVIDED BY Benno Rice ``AS IS'' AND ANY EXPRESS OR
  47  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  48  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  49  * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  50  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
  51  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
  52  * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
  53  * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
  54  * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
  55  * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  56  *
  57  * from $NetBSD: cpu_subr.c,v 1.1 2003/02/03 17:10:09 matt Exp $
  58  * $FreeBSD$
  59  */
  60
  61 #include <sys/param.h>
  62 #include <sys/systm.h>
  63 #include <sys/bus.h>
  64 #include <sys/conf.h>
  65 #include <sys/cpu.h>
  66 #include <sys/kernel.h>
  67 #include <sys/proc.h>
  68 #include <sys/sysctl.h>
  69
  70 #include <machine/bus.h>
  71 #include <machine/cpu.h>
  72 #include <machine/hid.h>
  73 #include <machine/md_var.h>
  74 #include <machine/smp.h>
  75 #include <machine/spr.h>
  76
  77 #include <dev/ofw/openfirm.h>
  78
  79 static void     cpu_6xx_setup(int cpuid, uint16_t vers);
  80 static void     cpu_970_setup(int cpuid, uint16_t vers);
  81 static void     cpu_booke_setup(int cpuid, uint16_t vers);
  82
  83 int powerpc_pow_enabled;
  84 void (*cpu_idle_hook)(sbintime_t) = NULL;
  85 static void     cpu_idle_60x(sbintime_t);
  86 static void     cpu_idle_booke(sbintime_t);
  87
  88 struct cputab {
  89         const char      *name;
  90         uint16_t        version;
  91         uint16_t        revfmt;
  92         int             features;       /* Do not include PPC_FEATURE_32 or
  93                                          * PPC_FEATURE_HAS_MMU */
  94         int             features2;
  95         void            (*cpu_setup)(int cpuid, uint16_t vers);
  96 };
  97 #define REVFMT_MAJMIN   1       /* %u.%u */
  98 #define REVFMT_HEX      2       /* 0x%04x */
  99 #define REVFMT_DEC      3       /* %u */
 100 static const struct cputab models[] = {
 101         { "Motorola PowerPC 601",       MPC601,         REVFMT_DEC,
 102            PPC_FEATURE_HAS_FPU | PPC_FEATURE_UNIFIED_CACHE, 0, cpu_6xx_setup },
 103         { "Motorola PowerPC 602",       MPC602,         REVFMT_DEC,
 104            PPC_FEATURE_HAS_FPU, 0, cpu_6xx_setup },
 105         { "Motorola PowerPC 603",       MPC603,         REVFMT_MAJMIN,
 106            PPC_FEATURE_HAS_FPU, 0, cpu_6xx_setup },
 107         { "Motorola PowerPC 603e",      MPC603e,        REVFMT_MAJMIN,
 108            PPC_FEATURE_HAS_FPU, 0, cpu_6xx_setup },
 109         { "Motorola PowerPC 603ev",     MPC603ev,       REVFMT_MAJMIN,
 110            PPC_FEATURE_HAS_FPU, 0, cpu_6xx_setup },
 111         { "Motorola PowerPC 604",       MPC604,         REVFMT_MAJMIN,
 112            PPC_FEATURE_HAS_FPU, 0, cpu_6xx_setup },
 113         { "Motorola PowerPC 604ev",     MPC604ev,       REVFMT_MAJMIN,
 114            PPC_FEATURE_HAS_FPU, 0, cpu_6xx_setup },
 115         { "Motorola PowerPC 620",       MPC620,         REVFMT_HEX,
 116            PPC_FEATURE_64 | PPC_FEATURE_HAS_FPU, 0, NULL },
 117         { "Motorola PowerPC 750",       MPC750,         REVFMT_MAJMIN,
 118            PPC_FEATURE_HAS_FPU, 0, cpu_6xx_setup },
 119         { "IBM PowerPC 750FX",          IBM750FX,       REVFMT_MAJMIN,
 120            PPC_FEATURE_HAS_FPU, 0, cpu_6xx_setup },
 121         { "IBM PowerPC 970",            IBM970,         REVFMT_MAJMIN,
 122            PPC_FEATURE_64 | PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU,
 123            0, cpu_970_setup },
 124         { "IBM PowerPC 970FX",          IBM970FX,       REVFMT_MAJMIN,
 125            PPC_FEATURE_64 | PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU,
 126            0, cpu_970_setup },
 127         { "IBM PowerPC 970GX",          IBM970GX,       REVFMT_MAJMIN,
 128            PPC_FEATURE_64 | PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU,
 129            0, cpu_970_setup },
 130         { "IBM PowerPC 970MP",          IBM970MP,       REVFMT_MAJMIN,
 131            PPC_FEATURE_64 | PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU,
 132            0, cpu_970_setup },
 133         { "IBM POWER4",         IBMPOWER4,      REVFMT_MAJMIN,
 134            PPC_FEATURE_64 | PPC_FEATURE_HAS_FPU, 0, NULL },
 135         { "IBM POWER4+",        IBMPOWER4PLUS,  REVFMT_MAJMIN,
 136            PPC_FEATURE_64 | PPC_FEATURE_HAS_FPU, 0, NULL },
 137         { "IBM POWER5",         IBMPOWER5,      REVFMT_MAJMIN,
 138            PPC_FEATURE_64 | PPC_FEATURE_HAS_FPU | PPC_FEATURE_SMT, 0, NULL },
 139         { "IBM POWER5+",        IBMPOWER5PLUS,  REVFMT_MAJMIN,
 140            PPC_FEATURE_64 | PPC_FEATURE_HAS_FPU | PPC_FEATURE_SMT, 0, NULL },
 141         { "IBM POWER6",         IBMPOWER6,      REVFMT_MAJMIN,
 142            PPC_FEATURE_64 | PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU |
 143            PPC_FEATURE_SMT | PPC_FEATURE_ARCH_2_05, 0, NULL },
 144         { "IBM POWER7",         IBMPOWER7,      REVFMT_MAJMIN,
 145            PPC_FEATURE_64 | PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU |
 146            PPC_FEATURE_SMT | PPC_FEATURE_ARCH_2_05 | PPC_FEATURE_ARCH_2_06 |
 147            PPC_FEATURE_HAS_VSX, 0, NULL },
 148         { "IBM POWER7+",        IBMPOWER7PLUS,  REVFMT_MAJMIN,
 149            PPC_FEATURE_64 | PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU |
 150            PPC_FEATURE_SMT | PPC_FEATURE_ARCH_2_05 | PPC_FEATURE_ARCH_2_06 |
 151            PPC_FEATURE_HAS_VSX, 0, NULL },
 152         { "IBM POWER8E",        IBMPOWER8E,     REVFMT_MAJMIN,
 153            PPC_FEATURE_64 | PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU |
 154            PPC_FEATURE_SMT | PPC_FEATURE_ARCH_2_05 | PPC_FEATURE_ARCH_2_06 |
 155            PPC_FEATURE_HAS_VSX,
 156            PPC_FEATURE2_ARCH_2_07 | PPC_FEATURE2_HAS_HTM | PPC_FEATURE2_ISEL |
 157            PPC_FEATURE2_HAS_VCRYPTO, NULL },
 158         { "IBM POWER8",         IBMPOWER8,      REVFMT_MAJMIN,
 159            PPC_FEATURE_64 | PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU |
 160            PPC_FEATURE_SMT | PPC_FEATURE_ARCH_2_05 | PPC_FEATURE_ARCH_2_06 |
 161            PPC_FEATURE_HAS_VSX,
 162            PPC_FEATURE2_ARCH_2_07 | PPC_FEATURE2_HAS_HTM | PPC_FEATURE2_ISEL |
 163            PPC_FEATURE2_HAS_VCRYPTO, NULL },
 164         { "Motorola PowerPC 7400",      MPC7400,        REVFMT_MAJMIN,
 165            PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU, 0, cpu_6xx_setup },
 166         { "Motorola PowerPC 7410",      MPC7410,        REVFMT_MAJMIN,
 167            PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU, 0, cpu_6xx_setup },
 168         { "Motorola PowerPC 7450",      MPC7450,        REVFMT_MAJMIN,
 169            PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU, 0, cpu_6xx_setup },
 170         { "Motorola PowerPC 7455",      MPC7455,        REVFMT_MAJMIN,
 171            PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU, 0, cpu_6xx_setup },
 172         { "Motorola PowerPC 7457",      MPC7457,        REVFMT_MAJMIN,
 173            PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU, 0, cpu_6xx_setup },
 174         { "Motorola PowerPC 7447A",     MPC7447A,       REVFMT_MAJMIN,
 175            PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU, 0, cpu_6xx_setup },
 176         { "Motorola PowerPC 7448",      MPC7448,        REVFMT_MAJMIN,
 177            PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU, 0, cpu_6xx_setup },
 178         { "Motorola PowerPC 8240",      MPC8240,        REVFMT_MAJMIN,
 179            PPC_FEATURE_HAS_FPU, 0, cpu_6xx_setup },
 180         { "Motorola PowerPC 8245",      MPC8245,        REVFMT_MAJMIN,
 181            PPC_FEATURE_HAS_FPU, 0, cpu_6xx_setup },
 182         { "Freescale e500v1 core",      FSL_E500v1,     REVFMT_MAJMIN,
 183            PPC_FEATURE_BOOKE | PPC_FEATURE_HAS_SPE | PPC_FEATURE_HAS_EFP_SINGLE,
 184            PPC_FEATURE2_ISEL, cpu_booke_setup },
 185         { "Freescale e500v2 core",      FSL_E500v2,     REVFMT_MAJMIN,
 186            PPC_FEATURE_BOOKE | PPC_FEATURE_HAS_SPE |
 187            PPC_FEATURE_HAS_EFP_SINGLE | PPC_FEATURE_HAS_EFP_DOUBLE,
 188            PPC_FEATURE2_ISEL, cpu_booke_setup },
 189         { "Freescale e500mc core",      FSL_E500mc,     REVFMT_MAJMIN,
 190            PPC_FEATURE_BOOKE | PPC_FEATURE_HAS_FPU, PPC_FEATURE2_ISEL,
 191            cpu_booke_setup },
 192         { "Freescale e5500 core",       FSL_E5500,      REVFMT_MAJMIN,
 193            PPC_FEATURE_BOOKE | PPC_FEATURE_64 | PPC_FEATURE_HAS_FPU,
 194            PPC_FEATURE2_ISEL, cpu_booke_setup },
 195         { "Freescale e6500 core",       FSL_E6500,      REVFMT_MAJMIN,
 196            PPC_FEATURE_BOOKE | PPC_FEATURE_64 | PPC_FEATURE_HAS_ALTIVEC |
 197            PPC_FEATURE_HAS_FPU, PPC_FEATURE2_ISEL, cpu_booke_setup },
 198         { "IBM Cell Broadband Engine",  IBMCELLBE,      REVFMT_MAJMIN,
 199            PPC_FEATURE_64 | PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU |
 200            PPC_FEATURE_SMT, 0, NULL},
 201         { "Unknown PowerPC CPU",        0,              REVFMT_HEX, 0, 0, NULL },
 202 };
 203
 204 static void     cpu_6xx_print_cacheinfo(u_int, uint16_t);
 205 static int      cpu_feature_bit(SYSCTL_HANDLER_ARGS);
 206
 207 static char model[64];
 208 SYSCTL_STRING(_hw, HW_MODEL, model, CTLFLAG_RD, model, 0, "");
 209
 210 int cpu_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU;
 211 int cpu_features2 = 0;
 212 SYSCTL_OPAQUE(_hw, OID_AUTO, cpu_features, CTLFLAG_RD,
 213     &cpu_features, sizeof(cpu_features), "IX", "PowerPC CPU features");
 214 SYSCTL_OPAQUE(_hw, OID_AUTO, cpu_features2, CTLFLAG_RD,
 215     &cpu_features2, sizeof(cpu_features2), "IX", "PowerPC CPU features 2");
 216
 217 /* Provide some user-friendly aliases for bits in cpu_features */
 218 SYSCTL_PROC(_hw, OID_AUTO, floatingpoint, CTLTYPE_INT | CTLFLAG_RD,
 219     0, PPC_FEATURE_HAS_FPU, cpu_feature_bit, "I",
 220     "Floating point instructions executed in hardware");
 221 SYSCTL_PROC(_hw, OID_AUTO, altivec, CTLTYPE_INT | CTLFLAG_RD,
 222     0, PPC_FEATURE_HAS_ALTIVEC, cpu_feature_bit, "I", "CPU supports Altivec");
 223
 224 void
 225 cpu_setup(u_int cpuid)
 226 {
 227         u_int           pvr, maj, min;
 228         uint16_t        vers, rev, revfmt;
 229         uint64_t        cps;
 230         const struct    cputab *cp;
 231         const char      *name;
 232
 233         pvr = mfpvr();
 234         vers = pvr >> 16;
 235         rev = pvr;
 236         switch (vers) {
 237                 case MPC7410:
 238                         min = (pvr >> 0) & 0xff;
 239                         maj = min <= 4 ? 1 : 2;
 240                         break;
 241                 case FSL_E500v1:
 242                 case FSL_E500v2:
 243                 case FSL_E500mc:
 244                 case FSL_E5500:
 245                         maj = (pvr >>  4) & 0xf;
 246                         min = (pvr >>  0) & 0xf;
 247                         break;
 248                 default:
 249                         maj = (pvr >>  8) & 0xf;
 250                         min = (pvr >>  0) & 0xf;
 251         }
 252
 253         for (cp = models; cp->version != 0; cp++) {
 254                 if (cp->version == vers)
 255                         break;
 256         }
 257
 258         revfmt = cp->revfmt;
 259         name = cp->name;
 260         if (rev == MPC750 && pvr == 15) {
 261                 name = "Motorola MPC755";
 262                 revfmt = REVFMT_HEX;
 263         }
 264         strncpy(model, name, sizeof(model) - 1);
 265
 266         printf("cpu%d: %s revision ", cpuid, name);
 267
 268         switch (revfmt) {
 269                 case REVFMT_MAJMIN:
 270                         printf("%u.%u", maj, min);
 271                         break;
 272                 case REVFMT_HEX:
 273                         printf("0x%04x", rev);
 274                         break;
 275                 case REVFMT_DEC:
 276                         printf("%u", rev);
 277                         break;
 278         }
 279
 280         if (cpu_est_clockrate(0, &cps) == 0)
 281                 printf(", %jd.%02jd MHz", cps / 1000000, (cps / 10000) % 100);
 282         printf("\n");
 283
 284         cpu_features |= cp->features;
 285         cpu_features2 |= cp->features2;
 286         printf("cpu%d: Features %b\n", cpuid, cpu_features,
 287             PPC_FEATURE_BITMASK);
 288         if (cpu_features2 != 0)
 289                 printf("cpu%d: Features2 %b\n", cpuid, cpu_features2,
 290                     PPC_FEATURE2_BITMASK);
 291
 292         /*
 293          * Configure CPU
 294          */
 295         if (cp->cpu_setup != NULL)
 296                 cp->cpu_setup(cpuid, vers);
 297 }
 298
 299 /* Get current clock frequency for the given cpu id. */
 300 int
 301 cpu_est_clockrate(int cpu_id, uint64_t *cps)
 302 {
 303         uint16_t        vers;
 304         register_t      msr;
 305         phandle_t       cpu, dev, root;
 306         int             res  = 0;
 307         char            buf[8];
 308
 309         vers = mfpvr() >> 16;
 310         msr = mfmsr();
 311         mtmsr(msr & ~PSL_EE);
 312
 313         switch (vers) {
 314                 case MPC7450:
 315                 case MPC7455:
 316                 case MPC7457:
 317                 case MPC750:
 318                 case IBM750FX:
 319                 case MPC7400:
 320                 case MPC7410:
 321                 case MPC7447A:
 322                 case MPC7448:
 323                         mtspr(SPR_MMCR0, SPR_MMCR0_FC);
 324                         mtspr(SPR_PMC1, 0);
 325                         mtspr(SPR_MMCR0, SPR_MMCR0_PMC1SEL(PMCN_CYCLES));
 326                         DELAY(1000);
 327                         *cps = (mfspr(SPR_PMC1) * 1000) + 4999;
 328                         mtspr(SPR_MMCR0, SPR_MMCR0_FC);
 329
 330                         mtmsr(msr);
 331                         return (0);
 332                 case IBM970:
 333                 case IBM970FX:
 334                 case IBM970MP:
 335                         isync();
 336                         mtspr(SPR_970MMCR0, SPR_MMCR0_FC);
 337                         isync();
 338                         mtspr(SPR_970MMCR1, 0);
 339                         mtspr(SPR_970MMCRA, 0);
 340                         mtspr(SPR_970PMC1, 0);
 341                         mtspr(SPR_970MMCR0,
 342                             SPR_970MMCR0_PMC1SEL(PMC970N_CYCLES));
 343                         isync();
 344                         DELAY(1000);
 345                         powerpc_sync();
 346                         mtspr(SPR_970MMCR0, SPR_MMCR0_FC);
 347                         *cps = (mfspr(SPR_970PMC1) * 1000) + 4999;
 348
 349                         mtmsr(msr);
 350                         return (0);
 351
 352                 default:
 353                         root = OF_peer(0);
 354                         if (root == 0)
 355                                 return (ENXIO);
 356
 357                         dev = OF_child(root);
 358                         while (dev != 0) {
 359                                 res = OF_getprop(dev, "name", buf, sizeof(buf));
 360                                 if (res > 0 && strcmp(buf, "cpus") == 0)
 361                                         break;
 362                                 dev = OF_peer(dev);
 363                         }
 364                         cpu = OF_child(dev);
 365                         while (cpu != 0) {
 366                                 res = OF_getprop(cpu, "device_type", buf,
 367                                                 sizeof(buf));
 368                                 if (res > 0 && strcmp(buf, "cpu") == 0)
 369                                         break;
 370                                 cpu = OF_peer(cpu);
 371                         }
 372                         if (cpu == 0)
 373                                 return (ENOENT);
 374                         if (OF_getprop(cpu, "ibm,extended-clock-frequency",
 375                             cps, sizeof(*cps)) >= 0) {
 376                                 return (0);
 377                         } else if (OF_getprop(cpu, "clock-frequency", cps,
 378                             sizeof(cell_t)) >= 0) {
 379                                 *cps >>= 32;
 380                                 return (0);
 381                         } else {
 382                                 return (ENOENT);
 383                         }
 384         }
 385 }
 386
 387 void
 388 cpu_6xx_setup(int cpuid, uint16_t vers)
 389 {
 390         register_t hid0, pvr;
 391         const char *bitmask;
 392
 393         hid0 = mfspr(SPR_HID0);
 394         pvr = mfpvr();
 395
 396         /*
 397          * Configure power-saving mode.
 398          */
 399         switch (vers) {
 400                 case MPC603:
 401                 case MPC603e:
 402                 case MPC603ev:
 403                 case MPC604ev:
 404                 case MPC750:
 405                 case IBM750FX:
 406                 case MPC7400:
 407                 case MPC7410:
 408                 case MPC8240:
 409                 case MPC8245:
 410                         /* Select DOZE mode. */
 411                         hid0 &= ~(HID0_DOZE | HID0_NAP | HID0_SLEEP);
 412                         hid0 |= HID0_DOZE | HID0_DPM;
 413                         powerpc_pow_enabled = 1;
 414                         break;
 415
 416                 case MPC7448:
 417                 case MPC7447A:
 418                 case MPC7457:
 419                 case MPC7455:
 420                 case MPC7450:
 421                         /* Enable the 7450 branch caches */
 422                         hid0 |= HID0_SGE | HID0_BTIC;
 423                         hid0 |= HID0_LRSTK | HID0_FOLD | HID0_BHT;
 424                         /* Disable BTIC on 7450 Rev 2.0 or earlier and on 7457 */
 425                         if (((pvr >> 16) == MPC7450 && (pvr & 0xFFFF) <= 0x0200)
 426                                         || (pvr >> 16) == MPC7457)
 427                                 hid0 &= ~HID0_BTIC;
 428                         /* Select NAP mode. */
 429                         hid0 &= ~(HID0_DOZE | HID0_NAP | HID0_SLEEP);
 430                         hid0 |= HID0_NAP | HID0_DPM;
 431                         powerpc_pow_enabled = 1;
 432                         break;
 433
 434                 default:
 435                         /* No power-saving mode is available. */ ;
 436         }
 437
 438         switch (vers) {
 439                 case IBM750FX:
 440                 case MPC750:
 441                         hid0 &= ~HID0_DBP;              /* XXX correct? */
 442                         hid0 |= HID0_EMCP | HID0_BTIC | HID0_SGE | HID0_BHT;
 443                         break;
 444
 445                 case MPC7400:
 446                 case MPC7410:
 447                         hid0 &= ~HID0_SPD;
 448                         hid0 |= HID0_EMCP | HID0_BTIC | HID0_SGE | HID0_BHT;
 449                         hid0 |= HID0_EIEC;
 450                         break;
 451
 452         }
 453
 454         mtspr(SPR_HID0, hid0);
 455
 456         if (bootverbose)
 457                 cpu_6xx_print_cacheinfo(cpuid, vers);
 458
 459         switch (vers) {
 460                 case MPC7447A:
 461                 case MPC7448:
 462                 case MPC7450:
 463                 case MPC7455:
 464                 case MPC7457:
 465                         bitmask = HID0_7450_BITMASK;
 466                         break;
 467                 default:
 468                         bitmask = HID0_BITMASK;
 469                         break;
 470         }
 471
 472         printf("cpu%d: HID0 %b\n", cpuid, (int)hid0, bitmask);
 473
 474         if (cpu_idle_hook == NULL)
 475                 cpu_idle_hook = cpu_idle_60x;
 476 }
 477
 478
 479 static void
 480 cpu_6xx_print_cacheinfo(u_int cpuid, uint16_t vers)
 481 {
 482         register_t hid;
 483
 484         hid = mfspr(SPR_HID0);
 485         printf("cpu%u: ", cpuid);
 486         printf("L1 I-cache %sabled, ", (hid & HID0_ICE) ? "en" : "dis");
 487         printf("L1 D-cache %sabled\n", (hid & HID0_DCE) ? "en" : "dis");
 488
 489         printf("cpu%u: ", cpuid);
 490         if (mfspr(SPR_L2CR) & L2CR_L2E) {
 491                 switch (vers) {
 492                 case MPC7450:
 493                 case MPC7455:
 494                 case MPC7457:
 495                         printf("256KB L2 cache, ");
 496                         if (mfspr(SPR_L3CR) & L3CR_L3E)
 497                                 printf("%cMB L3 backside cache",
 498                                     mfspr(SPR_L3CR) & L3CR_L3SIZ ? '2' : '1');
 499                         else
 500                                 printf("L3 cache disabled");
 501                         printf("\n");
 502                         break;
 503                 case IBM750FX:
 504                         printf("512KB L2 cache\n");
 505                         break;
 506                 default:
 507                         switch (mfspr(SPR_L2CR) & L2CR_L2SIZ) {
 508                         case L2SIZ_256K:
 509                                 printf("256KB ");
 510                                 break;
 511                         case L2SIZ_512K:
 512                                 printf("512KB ");
 513                                 break;
 514                         case L2SIZ_1M:
 515                                 printf("1MB ");
 516                                 break;
 517                         }
 518                         printf("write-%s", (mfspr(SPR_L2CR) & L2CR_L2WT)
 519                             ? "through" : "back");
 520                         if (mfspr(SPR_L2CR) & L2CR_L2PE)
 521                                 printf(", with parity");
 522                         printf(" backside cache\n");
 523                         break;
 524                 }
 525         } else
 526                 printf("L2 cache disabled\n");
 527 }
 528
 529 static void
 530 cpu_booke_setup(int cpuid, uint16_t vers)
 531 {
 532 #ifdef BOOKE_E500
 533         register_t hid0;
 534         const char *bitmask;
 535
 536         hid0 = mfspr(SPR_HID0);
 537
 538         switch (vers) {
 539         case FSL_E500mc:
 540                 bitmask = HID0_E500MC_BITMASK;
 541                 break;
 542         case FSL_E5500:
 543         case FSL_E6500:
 544                 bitmask = HID0_E5500_BITMASK;
 545                 break;
 546         case FSL_E500v1:
 547         case FSL_E500v2:
 548                 /* Only e500v1/v2 support HID0 power management setup. */
 549
 550                 /* Programe power-management mode. */
 551                 hid0 &= ~(HID0_DOZE | HID0_NAP | HID0_SLEEP);
 552                 hid0 |= HID0_DOZE;
 553
 554                 mtspr(SPR_HID0, hid0);
 555         default:
 556                 bitmask = HID0_E500_BITMASK;
 557                 break;
 558         }
 559         printf("cpu%d: HID0 %b\n", cpuid, (int)hid0, bitmask);
 560 #endif
 561
 562         if (cpu_idle_hook == NULL)
 563                 cpu_idle_hook = cpu_idle_booke;
 564 }
 565
 566 static void
 567 cpu_970_setup(int cpuid, uint16_t vers)
 568 {
 569 #ifdef AIM
 570         uint32_t hid0_hi, hid0_lo;
 571
 572         __asm __volatile ("mfspr %0,%2; clrldi %1,%0,32; srdi %0,%0,32;"
 573             : "=r" (hid0_hi), "=r" (hid0_lo) : "K" (SPR_HID0));
 574
 575         /* Configure power-saving mode */
 576         switch (vers) {
 577         case IBM970MP:
 578                 hid0_hi |= (HID0_DEEPNAP | HID0_NAP | HID0_DPM);
 579                 hid0_hi &= ~HID0_DOZE;
 580                 break;
 581         default:
 582                 hid0_hi |= (HID0_NAP | HID0_DPM);
 583                 hid0_hi &= ~(HID0_DOZE | HID0_DEEPNAP);
 584                 break;
 585         }
 586         powerpc_pow_enabled = 1;
 587
 588         __asm __volatile (" \
 589                 sync; isync;                                    \
 590                 sldi    %0,%0,32; or %0,%0,%1;                  \
 591                 mtspr   %2, %0;                                 \
 592                 mfspr   %0, %2; mfspr   %0, %2; mfspr   %0, %2; \
 593                 mfspr   %0, %2; mfspr   %0, %2; mfspr   %0, %2; \
 594                 sync; isync"
 595             :: "r" (hid0_hi), "r"(hid0_lo), "K" (SPR_HID0));
 596
 597         __asm __volatile ("mfspr %0,%1; srdi %0,%0,32;"
 598             : "=r" (hid0_hi) : "K" (SPR_HID0));
 599         printf("cpu%d: HID0 %b\n", cpuid, (int)(hid0_hi), HID0_970_BITMASK);
 600 #endif
 601
 602         cpu_idle_hook = cpu_idle_60x;
 603 }
 604
 605 static int
 606 cpu_feature_bit(SYSCTL_HANDLER_ARGS)
 607 {
 608         int result;
 609
 610         result = (cpu_features & arg2) ? 1 : 0;
 611
 612         return (sysctl_handle_int(oidp, &result, 0, req));
 613 }
 614
 615 void
 616 cpu_idle(int busy)
 617 {
 618         sbintime_t sbt = -1;
 619
 620 #ifdef INVARIANTS
 621         if ((mfmsr() & PSL_EE) != PSL_EE) {
 622                 struct thread *td = curthread;
 623                 printf("td msr %#lx\n", (u_long)td->td_md.md_saved_msr);
 624                 panic("ints disabled in idleproc!");
 625         }
 626 #endif
 627
 628         CTR2(KTR_SPARE2, "cpu_idle(%d) at %d",
 629             busy, curcpu);
 630
 631         if (cpu_idle_hook != NULL) {
 632                 if (!busy) {
 633                         critical_enter();
 634                         sbt = cpu_idleclock();
 635                 }
 636                 cpu_idle_hook(sbt);
 637                 if (!busy) {
 638                         cpu_activeclock();
 639                         critical_exit();
 640                 }
 641         }
 642
 643         CTR2(KTR_SPARE2, "cpu_idle(%d) at %d done",
 644             busy, curcpu);
 645 }
 646
 647 static void
 648 cpu_idle_60x(sbintime_t sbt)
 649 {
 650         register_t msr;
 651         uint16_t vers;
 652
 653         if (!powerpc_pow_enabled)
 654                 return;
 655
 656         msr = mfmsr();
 657         vers = mfpvr() >> 16;
 658
 659 #ifdef AIM
 660         switch (vers) {
 661         case IBM970:
 662         case IBM970FX:
 663         case IBM970MP:
 664         case MPC7447A:
 665         case MPC7448:
 666         case MPC7450:
 667         case MPC7455:
 668         case MPC7457:
 669                 __asm __volatile("\
 670                             dssall; sync; mtmsr %0; isync"
 671                             :: "r"(msr | PSL_POW));
 672                 break;
 673         default:
 674                 powerpc_sync();
 675                 mtmsr(msr | PSL_POW);
 676                 isync();
 677                 break;
 678         }
 679 #endif
 680 }
 681
 682 static void
 683 cpu_idle_booke(sbintime_t sbt)
 684 {
 685
 686 #ifdef BOOKE_E500
 687         platform_cpu_idle(PCPU_GET(cpuid));
 688 #endif
 689 }
 690