sys/powerpc/powerpc/cpu.c

   1 /*-
   2  * SPDX-License-Identifier: BSD-4-Clause AND BSD-2-Clause-FreeBSD
   3  *
   4  * Copyright (c) 2001 Matt Thomas.
   5  * Copyright (c) 2001 Tsubai Masanari.
   6  * Copyright (c) 1998, 1999, 2001 Internet Research Institute, Inc.
   7  * All rights reserved.
   8  *
   9  * Redistribution and use in source and binary forms, with or without
  10  * modification, are permitted provided that the following conditions
  11  * are met:
  12  * 1. Redistributions of source code must retain the above copyright
  13  *    notice, this list of conditions and the following disclaimer.
  14  * 2. Redistributions in binary form must reproduce the above copyright
  15  *    notice, this list of conditions and the following disclaimer in the
  16  *    documentation and/or other materials provided with the distribution.
  17  * 3. All advertising materials mentioning features or use of this software
  18  *    must display the following acknowledgement:
  19  *      This product includes software developed by
  20  *      Internet Research Institute, Inc.
  21  * 4. The name of the author may not be used to endorse or promote products
  22  *    derived from this software without specific prior written permission.
  23  *
  24  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  25  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  26  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  27  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  28  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  29  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  30  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  31  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  32  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  33  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  34  */
  35 /*-
  36  * Copyright (C) 2003 Benno Rice.
  37  * All rights reserved.
  38  *
  39  * Redistribution and use in source and binary forms, with or without
  40  * modification, are permitted provided that the following conditions
  41  * are met:
  42  * 1. Redistributions of source code must retain the above copyright
  43  *    notice, this list of conditions and the following disclaimer.
  44  * 2. Redistributions in binary form must reproduce the above copyright
  45  *    notice, this list of conditions and the following disclaimer in the
  46  *    documentation and/or other materials provided with the distribution.
  47  *
  48  * THIS SOFTWARE IS PROVIDED BY Benno Rice ``AS IS'' AND ANY EXPRESS OR
  49  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  50  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  51  * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  52  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
  53  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
  54  * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
  55  * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
  56  * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
  57  * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  58  *
  59  * from $NetBSD: cpu_subr.c,v 1.1 2003/02/03 17:10:09 matt Exp $
  60  * $FreeBSD$
  61  */
  62
  63 #include <sys/param.h>
  64 #include <sys/systm.h>
  65 #include <sys/bus.h>
  66 #include <sys/conf.h>
  67 #include <sys/cpu.h>
  68 #include <sys/kernel.h>
  69 #include <sys/proc.h>
  70 #include <sys/sysctl.h>
  71 #include <sys/sched.h>
  72 #include <sys/smp.h>
  73
  74 #include <machine/bus.h>
  75 #include <machine/cpu.h>
  76 #include <machine/hid.h>
  77 #include <machine/md_var.h>
  78 #include <machine/smp.h>
  79 #include <machine/spr.h>
  80
  81 #include <dev/ofw/openfirm.h>
  82
  83 static void     cpu_6xx_setup(int cpuid, uint16_t vers);
  84 static void     cpu_970_setup(int cpuid, uint16_t vers);
  85 static void     cpu_booke_setup(int cpuid, uint16_t vers);
  86 static void     cpu_powerx_setup(int cpuid, uint16_t vers);
  87
  88 int powerpc_pow_enabled;
  89 void (*cpu_idle_hook)(sbintime_t) = NULL;
  90 static void     cpu_idle_60x(sbintime_t);
  91 static void     cpu_idle_booke(sbintime_t);
  92 #ifdef __powerpc64__
  93 static void     cpu_idle_powerx(sbintime_t);
  94 #endif
  95
  96 struct cputab {
  97         const char      *name;
  98         uint16_t        version;
  99         uint16_t        revfmt;
 100         int             features;       /* Do not include PPC_FEATURE_32 or
 101                                          * PPC_FEATURE_HAS_MMU */
 102         int             features2;
 103         void            (*cpu_setup)(int cpuid, uint16_t vers);
 104 };
 105 #define REVFMT_MAJMIN   1       /* %u.%u */
 106 #define REVFMT_HEX      2       /* 0x%04x */
 107 #define REVFMT_DEC      3       /* %u */
 108 static const struct cputab models[] = {
 109         { "Motorola PowerPC 601",       MPC601,         REVFMT_DEC,
 110            PPC_FEATURE_HAS_FPU | PPC_FEATURE_UNIFIED_CACHE, 0, cpu_6xx_setup },
 111         { "Motorola PowerPC 602",       MPC602,         REVFMT_DEC,
 112            PPC_FEATURE_HAS_FPU, 0, cpu_6xx_setup },
 113         { "Motorola PowerPC 603",       MPC603,         REVFMT_MAJMIN,
 114            PPC_FEATURE_HAS_FPU, 0, cpu_6xx_setup },
 115         { "Motorola PowerPC 603e",      MPC603e,        REVFMT_MAJMIN,
 116            PPC_FEATURE_HAS_FPU, 0, cpu_6xx_setup },
 117         { "Motorola PowerPC 603ev",     MPC603ev,       REVFMT_MAJMIN,
 118            PPC_FEATURE_HAS_FPU, 0, cpu_6xx_setup },
 119         { "Motorola PowerPC 604",       MPC604,         REVFMT_MAJMIN,
 120            PPC_FEATURE_HAS_FPU, 0, cpu_6xx_setup },
 121         { "Motorola PowerPC 604ev",     MPC604ev,       REVFMT_MAJMIN,
 122            PPC_FEATURE_HAS_FPU, 0, cpu_6xx_setup },
 123         { "Motorola PowerPC 620",       MPC620,         REVFMT_HEX,
 124            PPC_FEATURE_64 | PPC_FEATURE_HAS_FPU, 0, NULL },
 125         { "Motorola PowerPC 750",       MPC750,         REVFMT_MAJMIN,
 126            PPC_FEATURE_HAS_FPU, 0, cpu_6xx_setup },
 127         { "IBM PowerPC 750FX",          IBM750FX,       REVFMT_MAJMIN,
 128            PPC_FEATURE_HAS_FPU, 0, cpu_6xx_setup },
 129         { "IBM PowerPC 970",            IBM970,         REVFMT_MAJMIN,
 130            PPC_FEATURE_64 | PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU,
 131            0, cpu_970_setup },
 132         { "IBM PowerPC 970FX",          IBM970FX,       REVFMT_MAJMIN,
 133            PPC_FEATURE_64 | PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU,
 134            0, cpu_970_setup },
 135         { "IBM PowerPC 970GX",          IBM970GX,       REVFMT_MAJMIN,
 136            PPC_FEATURE_64 | PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU,
 137            0, cpu_970_setup },
 138         { "IBM PowerPC 970MP",          IBM970MP,       REVFMT_MAJMIN,
 139            PPC_FEATURE_64 | PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU,
 140            0, cpu_970_setup },
 141         { "IBM POWER4",         IBMPOWER4,      REVFMT_MAJMIN,
 142            PPC_FEATURE_64 | PPC_FEATURE_HAS_FPU, 0, NULL },
 143         { "IBM POWER4+",        IBMPOWER4PLUS,  REVFMT_MAJMIN,
 144            PPC_FEATURE_64 | PPC_FEATURE_HAS_FPU, 0, NULL },
 145         { "IBM POWER5",         IBMPOWER5,      REVFMT_MAJMIN,
 146            PPC_FEATURE_64 | PPC_FEATURE_HAS_FPU | PPC_FEATURE_SMT, 0, NULL },
 147         { "IBM POWER5+",        IBMPOWER5PLUS,  REVFMT_MAJMIN,
 148            PPC_FEATURE_64 | PPC_FEATURE_HAS_FPU | PPC_FEATURE_SMT, 0, NULL },
 149         { "IBM POWER6",         IBMPOWER6,      REVFMT_MAJMIN,
 150            PPC_FEATURE_64 | PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU |
 151            PPC_FEATURE_SMT | PPC_FEATURE_ARCH_2_05, 0, NULL },
 152         { "IBM POWER7",         IBMPOWER7,      REVFMT_MAJMIN,
 153            PPC_FEATURE_64 | PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU |
 154            PPC_FEATURE_SMT | PPC_FEATURE_ARCH_2_05 | PPC_FEATURE_ARCH_2_06 |
 155            PPC_FEATURE_HAS_VSX, 0, NULL },
 156         { "IBM POWER7+",        IBMPOWER7PLUS,  REVFMT_MAJMIN,
 157            PPC_FEATURE_64 | PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU |
 158            PPC_FEATURE_SMT | PPC_FEATURE_ARCH_2_05 | PPC_FEATURE_ARCH_2_06 |
 159            PPC_FEATURE_HAS_VSX, 0, NULL },
 160         { "IBM POWER8E",        IBMPOWER8E,     REVFMT_MAJMIN,
 161            PPC_FEATURE_64 | PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU |
 162            PPC_FEATURE_SMT | PPC_FEATURE_ARCH_2_05 | PPC_FEATURE_ARCH_2_06 |
 163            PPC_FEATURE_HAS_VSX,
 164            PPC_FEATURE2_ARCH_2_07 | PPC_FEATURE2_HAS_HTM | PPC_FEATURE2_ISEL |
 165            PPC_FEATURE2_HAS_VCRYPTO, cpu_powerx_setup },
 166         { "IBM POWER8",         IBMPOWER8,      REVFMT_MAJMIN,
 167            PPC_FEATURE_64 | PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU |
 168            PPC_FEATURE_SMT | PPC_FEATURE_ARCH_2_05 | PPC_FEATURE_ARCH_2_06 |
 169            PPC_FEATURE_HAS_VSX,
 170            PPC_FEATURE2_ARCH_2_07 | PPC_FEATURE2_HAS_HTM | PPC_FEATURE2_ISEL |
 171            PPC_FEATURE2_HAS_VCRYPTO, cpu_powerx_setup },
 172         { "IBM POWER9",         IBMPOWER9,      REVFMT_MAJMIN,
 173            PPC_FEATURE_64 | PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU |
 174            PPC_FEATURE_SMT | PPC_FEATURE_ARCH_2_05 | PPC_FEATURE_ARCH_2_06 |
 175            PPC_FEATURE_HAS_VSX,
 176            PPC_FEATURE2_ARCH_2_07 | PPC_FEATURE2_HAS_HTM | PPC_FEATURE2_ISEL |
 177            PPC_FEATURE2_HAS_VCRYPTO, NULL },
 178         { "Motorola PowerPC 7400",      MPC7400,        REVFMT_MAJMIN,
 179            PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU, 0, cpu_6xx_setup },
 180         { "Motorola PowerPC 7410",      MPC7410,        REVFMT_MAJMIN,
 181            PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU, 0, cpu_6xx_setup },
 182         { "Motorola PowerPC 7450",      MPC7450,        REVFMT_MAJMIN,
 183            PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU, 0, cpu_6xx_setup },
 184         { "Motorola PowerPC 7455",      MPC7455,        REVFMT_MAJMIN,
 185            PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU, 0, cpu_6xx_setup },
 186         { "Motorola PowerPC 7457",      MPC7457,        REVFMT_MAJMIN,
 187            PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU, 0, cpu_6xx_setup },
 188         { "Motorola PowerPC 7447A",     MPC7447A,       REVFMT_MAJMIN,
 189            PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU, 0, cpu_6xx_setup },
 190         { "Motorola PowerPC 7448",      MPC7448,        REVFMT_MAJMIN,
 191            PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU, 0, cpu_6xx_setup },
 192         { "Motorola PowerPC 8240",      MPC8240,        REVFMT_MAJMIN,
 193            PPC_FEATURE_HAS_FPU, 0, cpu_6xx_setup },
 194         { "Motorola PowerPC 8245",      MPC8245,        REVFMT_MAJMIN,
 195            PPC_FEATURE_HAS_FPU, 0, cpu_6xx_setup },
 196         { "Freescale e500v1 core",      FSL_E500v1,     REVFMT_MAJMIN,
 197            PPC_FEATURE_BOOKE | PPC_FEATURE_HAS_SPE | PPC_FEATURE_HAS_EFP_SINGLE,
 198            PPC_FEATURE2_ISEL, cpu_booke_setup },
 199         { "Freescale e500v2 core",      FSL_E500v2,     REVFMT_MAJMIN,
 200            PPC_FEATURE_BOOKE | PPC_FEATURE_HAS_SPE |
 201            PPC_FEATURE_HAS_EFP_SINGLE | PPC_FEATURE_HAS_EFP_DOUBLE,
 202            PPC_FEATURE2_ISEL, cpu_booke_setup },
 203         { "Freescale e500mc core",      FSL_E500mc,     REVFMT_MAJMIN,
 204            PPC_FEATURE_BOOKE | PPC_FEATURE_HAS_FPU, PPC_FEATURE2_ISEL,
 205            cpu_booke_setup },
 206         { "Freescale e5500 core",       FSL_E5500,      REVFMT_MAJMIN,
 207            PPC_FEATURE_BOOKE | PPC_FEATURE_64 | PPC_FEATURE_HAS_FPU,
 208            PPC_FEATURE2_ISEL, cpu_booke_setup },
 209         { "Freescale e6500 core",       FSL_E6500,      REVFMT_MAJMIN,
 210            PPC_FEATURE_BOOKE | PPC_FEATURE_64 | PPC_FEATURE_HAS_ALTIVEC |
 211            PPC_FEATURE_HAS_FPU, PPC_FEATURE2_ISEL, cpu_booke_setup },
 212         { "IBM Cell Broadband Engine",  IBMCELLBE,      REVFMT_MAJMIN,
 213            PPC_FEATURE_64 | PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU |
 214            PPC_FEATURE_SMT, 0, NULL},
 215         { "Unknown PowerPC CPU",        0,              REVFMT_HEX, 0, 0, NULL },
 216 };
 217
 218 static void     cpu_6xx_print_cacheinfo(u_int, uint16_t);
 219 static int      cpu_feature_bit(SYSCTL_HANDLER_ARGS);
 220
 221 static char model[64];
 222 SYSCTL_STRING(_hw, HW_MODEL, model, CTLFLAG_RD, model, 0, "");
 223
 224 int cpu_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU;
 225 int cpu_features2 = 0;
 226 SYSCTL_OPAQUE(_hw, OID_AUTO, cpu_features, CTLFLAG_RD,
 227     &cpu_features, sizeof(cpu_features), "IX", "PowerPC CPU features");
 228 SYSCTL_OPAQUE(_hw, OID_AUTO, cpu_features2, CTLFLAG_RD,
 229     &cpu_features2, sizeof(cpu_features2), "IX", "PowerPC CPU features 2");
 230
 231 /* Provide some user-friendly aliases for bits in cpu_features */
 232 SYSCTL_PROC(_hw, OID_AUTO, floatingpoint, CTLTYPE_INT | CTLFLAG_RD,
 233     0, PPC_FEATURE_HAS_FPU, cpu_feature_bit, "I",
 234     "Floating point instructions executed in hardware");
 235 SYSCTL_PROC(_hw, OID_AUTO, altivec, CTLTYPE_INT | CTLFLAG_RD,
 236     0, PPC_FEATURE_HAS_ALTIVEC, cpu_feature_bit, "I", "CPU supports Altivec");
 237
 238 void
 239 cpu_setup(u_int cpuid)
 240 {
 241         u_int           pvr, maj, min;
 242         uint16_t        vers, rev, revfmt;
 243         uint64_t        cps;
 244         const struct    cputab *cp;
 245         const char      *name;
 246
 247         pvr = mfpvr();
 248         vers = pvr >> 16;
 249         rev = pvr;
 250         switch (vers) {
 251                 case MPC7410:
 252                         min = (pvr >> 0) & 0xff;
 253                         maj = min <= 4 ? 1 : 2;
 254                         break;
 255                 case FSL_E500v1:
 256                 case FSL_E500v2:
 257                 case FSL_E500mc:
 258                 case FSL_E5500:
 259                         maj = (pvr >>  4) & 0xf;
 260                         min = (pvr >>  0) & 0xf;
 261                         break;
 262                 default:
 263                         maj = (pvr >>  8) & 0xf;
 264                         min = (pvr >>  0) & 0xf;
 265         }
 266
 267         for (cp = models; cp->version != 0; cp++) {
 268                 if (cp->version == vers)
 269                         break;
 270         }
 271
 272         revfmt = cp->revfmt;
 273         name = cp->name;
 274         if (rev == MPC750 && pvr == 15) {
 275                 name = "Motorola MPC755";
 276                 revfmt = REVFMT_HEX;
 277         }
 278         strncpy(model, name, sizeof(model) - 1);
 279
 280         printf("cpu%d: %s revision ", cpuid, name);
 281
 282         switch (revfmt) {
 283                 case REVFMT_MAJMIN:
 284                         printf("%u.%u", maj, min);
 285                         break;
 286                 case REVFMT_HEX:
 287                         printf("0x%04x", rev);
 288                         break;
 289                 case REVFMT_DEC:
 290                         printf("%u", rev);
 291                         break;
 292         }
 293
 294         if (cpu_est_clockrate(0, &cps) == 0)
 295                 printf(", %jd.%02jd MHz", cps / 1000000, (cps / 10000) % 100);
 296         printf("\n");
 297
 298         cpu_features |= cp->features;
 299         cpu_features2 |= cp->features2;
 300         printf("cpu%d: Features %b\n", cpuid, cpu_features,
 301             PPC_FEATURE_BITMASK);
 302         if (cpu_features2 != 0)
 303                 printf("cpu%d: Features2 %b\n", cpuid, cpu_features2,
 304                     PPC_FEATURE2_BITMASK);
 305
 306         /*
 307          * Configure CPU
 308          */
 309         if (cp->cpu_setup != NULL)
 310                 cp->cpu_setup(cpuid, vers);
 311 }
 312
 313 /* Get current clock frequency for the given cpu id. */
 314 int
 315 cpu_est_clockrate(int cpu_id, uint64_t *cps)
 316 {
 317         uint16_t        vers;
 318         register_t      msr;
 319         phandle_t       cpu, dev, root;
 320         int             res  = 0;
 321         char            buf[8];
 322
 323         vers = mfpvr() >> 16;
 324         msr = mfmsr();
 325         mtmsr(msr & ~PSL_EE);
 326
 327         switch (vers) {
 328                 case MPC7450:
 329                 case MPC7455:
 330                 case MPC7457:
 331                 case MPC750:
 332                 case IBM750FX:
 333                 case MPC7400:
 334                 case MPC7410:
 335                 case MPC7447A:
 336                 case MPC7448:
 337                         mtspr(SPR_MMCR0, SPR_MMCR0_FC);
 338                         mtspr(SPR_PMC1, 0);
 339                         mtspr(SPR_MMCR0, SPR_MMCR0_PMC1SEL(PMCN_CYCLES));
 340                         DELAY(1000);
 341                         *cps = (mfspr(SPR_PMC1) * 1000) + 4999;
 342                         mtspr(SPR_MMCR0, SPR_MMCR0_FC);
 343
 344                         mtmsr(msr);
 345                         return (0);
 346                 case IBM970:
 347                 case IBM970FX:
 348                 case IBM970MP:
 349                         isync();
 350                         mtspr(SPR_970MMCR0, SPR_MMCR0_FC);
 351                         isync();
 352                         mtspr(SPR_970MMCR1, 0);
 353                         mtspr(SPR_970MMCRA, 0);
 354                         mtspr(SPR_970PMC1, 0);
 355                         mtspr(SPR_970MMCR0,
 356                             SPR_970MMCR0_PMC1SEL(PMC970N_CYCLES));
 357                         isync();
 358                         DELAY(1000);
 359                         powerpc_sync();
 360                         mtspr(SPR_970MMCR0, SPR_MMCR0_FC);
 361                         *cps = (mfspr(SPR_970PMC1) * 1000) + 4999;
 362
 363                         mtmsr(msr);
 364                         return (0);
 365
 366                 default:
 367                         root = OF_peer(0);
 368                         if (root == 0)
 369                                 return (ENXIO);
 370
 371                         dev = OF_child(root);
 372                         while (dev != 0) {
 373                                 res = OF_getprop(dev, "name", buf, sizeof(buf));
 374                                 if (res > 0 && strcmp(buf, "cpus") == 0)
 375                                         break;
 376                                 dev = OF_peer(dev);
 377                         }
 378                         cpu = OF_child(dev);
 379                         while (cpu != 0) {
 380                                 res = OF_getprop(cpu, "device_type", buf,
 381                                                 sizeof(buf));
 382                                 if (res > 0 && strcmp(buf, "cpu") == 0)
 383                                         break;
 384                                 cpu = OF_peer(cpu);
 385                         }
 386                         if (cpu == 0)
 387                                 return (ENOENT);
 388                         if (OF_getprop(cpu, "ibm,extended-clock-frequency",
 389                             cps, sizeof(*cps)) >= 0) {
 390                                 return (0);
 391                         } else if (OF_getprop(cpu, "clock-frequency", cps,
 392                             sizeof(cell_t)) >= 0) {
 393                                 *cps >>= 32;
 394                                 return (0);
 395                         } else {
 396                                 return (ENOENT);
 397                         }
 398         }
 399 }
 400
 401 void
 402 cpu_6xx_setup(int cpuid, uint16_t vers)
 403 {
 404         register_t hid0, pvr;
 405         const char *bitmask;
 406
 407         hid0 = mfspr(SPR_HID0);
 408         pvr = mfpvr();
 409
 410         /*
 411          * Configure power-saving mode.
 412          */
 413         switch (vers) {
 414                 case MPC603:
 415                 case MPC603e:
 416                 case MPC603ev:
 417                 case MPC604ev:
 418                 case MPC750:
 419                 case IBM750FX:
 420                 case MPC7400:
 421                 case MPC7410:
 422                 case MPC8240:
 423                 case MPC8245:
 424                         /* Select DOZE mode. */
 425                         hid0 &= ~(HID0_DOZE | HID0_NAP | HID0_SLEEP);
 426                         hid0 |= HID0_DOZE | HID0_DPM;
 427                         powerpc_pow_enabled = 1;
 428                         break;
 429
 430                 case MPC7448:
 431                 case MPC7447A:
 432                 case MPC7457:
 433                 case MPC7455:
 434                 case MPC7450:
 435                         /* Enable the 7450 branch caches */
 436                         hid0 |= HID0_SGE | HID0_BTIC;
 437                         hid0 |= HID0_LRSTK | HID0_FOLD | HID0_BHT;
 438                         /* Disable BTIC on 7450 Rev 2.0 or earlier and on 7457 */
 439                         if (((pvr >> 16) == MPC7450 && (pvr & 0xFFFF) <= 0x0200)
 440                                         || (pvr >> 16) == MPC7457)
 441                                 hid0 &= ~HID0_BTIC;
 442                         /* Select NAP mode. */
 443                         hid0 &= ~(HID0_DOZE | HID0_NAP | HID0_SLEEP);
 444                         hid0 |= HID0_NAP | HID0_DPM;
 445                         powerpc_pow_enabled = 1;
 446                         break;
 447
 448                 default:
 449                         /* No power-saving mode is available. */ ;
 450         }
 451
 452         switch (vers) {
 453                 case IBM750FX:
 454                 case MPC750:
 455                         hid0 &= ~HID0_DBP;              /* XXX correct? */
 456                         hid0 |= HID0_EMCP | HID0_BTIC | HID0_SGE | HID0_BHT;
 457                         break;
 458
 459                 case MPC7400:
 460                 case MPC7410:
 461                         hid0 &= ~HID0_SPD;
 462                         hid0 |= HID0_EMCP | HID0_BTIC | HID0_SGE | HID0_BHT;
 463                         hid0 |= HID0_EIEC;
 464                         break;
 465
 466         }
 467
 468         mtspr(SPR_HID0, hid0);
 469
 470         if (bootverbose)
 471                 cpu_6xx_print_cacheinfo(cpuid, vers);
 472
 473         switch (vers) {
 474                 case MPC7447A:
 475                 case MPC7448:
 476                 case MPC7450:
 477                 case MPC7455:
 478                 case MPC7457:
 479                         bitmask = HID0_7450_BITMASK;
 480                         break;
 481                 default:
 482                         bitmask = HID0_BITMASK;
 483                         break;
 484         }
 485
 486         printf("cpu%d: HID0 %b\n", cpuid, (int)hid0, bitmask);
 487
 488         if (cpu_idle_hook == NULL)
 489                 cpu_idle_hook = cpu_idle_60x;
 490 }
 491
 492
 493 static void
 494 cpu_6xx_print_cacheinfo(u_int cpuid, uint16_t vers)
 495 {
 496         register_t hid;
 497
 498         hid = mfspr(SPR_HID0);
 499         printf("cpu%u: ", cpuid);
 500         printf("L1 I-cache %sabled, ", (hid & HID0_ICE) ? "en" : "dis");
 501         printf("L1 D-cache %sabled\n", (hid & HID0_DCE) ? "en" : "dis");
 502
 503         printf("cpu%u: ", cpuid);
 504         if (mfspr(SPR_L2CR) & L2CR_L2E) {
 505                 switch (vers) {
 506                 case MPC7450:
 507                 case MPC7455:
 508                 case MPC7457:
 509                         printf("256KB L2 cache, ");
 510                         if (mfspr(SPR_L3CR) & L3CR_L3E)
 511                                 printf("%cMB L3 backside cache",
 512                                     mfspr(SPR_L3CR) & L3CR_L3SIZ ? '2' : '1');
 513                         else
 514                                 printf("L3 cache disabled");
 515                         printf("\n");
 516                         break;
 517                 case IBM750FX:
 518                         printf("512KB L2 cache\n");
 519                         break;
 520                 default:
 521                         switch (mfspr(SPR_L2CR) & L2CR_L2SIZ) {
 522                         case L2SIZ_256K:
 523                                 printf("256KB ");
 524                                 break;
 525                         case L2SIZ_512K:
 526                                 printf("512KB ");
 527                                 break;
 528                         case L2SIZ_1M:
 529                                 printf("1MB ");
 530                                 break;
 531                         }
 532                         printf("write-%s", (mfspr(SPR_L2CR) & L2CR_L2WT)
 533                             ? "through" : "back");
 534                         if (mfspr(SPR_L2CR) & L2CR_L2PE)
 535                                 printf(", with parity");
 536                         printf(" backside cache\n");
 537                         break;
 538                 }
 539         } else
 540                 printf("L2 cache disabled\n");
 541 }
 542
 543 static void
 544 cpu_booke_setup(int cpuid, uint16_t vers)
 545 {
 546 #ifdef BOOKE_E500
 547         register_t hid0;
 548         const char *bitmask;
 549
 550         hid0 = mfspr(SPR_HID0);
 551
 552         switch (vers) {
 553         case FSL_E500mc:
 554                 bitmask = HID0_E500MC_BITMASK;
 555                 break;
 556         case FSL_E5500:
 557         case FSL_E6500:
 558                 bitmask = HID0_E5500_BITMASK;
 559                 break;
 560         case FSL_E500v1:
 561         case FSL_E500v2:
 562                 /* Only e500v1/v2 support HID0 power management setup. */
 563
 564                 /* Programe power-management mode. */
 565                 hid0 &= ~(HID0_DOZE | HID0_NAP | HID0_SLEEP);
 566                 hid0 |= HID0_DOZE;
 567
 568                 mtspr(SPR_HID0, hid0);
 569         default:
 570                 bitmask = HID0_E500_BITMASK;
 571                 break;
 572         }
 573         printf("cpu%d: HID0 %b\n", cpuid, (int)hid0, bitmask);
 574 #endif
 575
 576         if (cpu_idle_hook == NULL)
 577                 cpu_idle_hook = cpu_idle_booke;
 578 }
 579
 580 static void
 581 cpu_970_setup(int cpuid, uint16_t vers)
 582 {
 583 #ifdef AIM
 584         uint32_t hid0_hi, hid0_lo;
 585
 586         __asm __volatile ("mfspr %0,%2; clrldi %1,%0,32; srdi %0,%0,32;"
 587             : "=r" (hid0_hi), "=r" (hid0_lo) : "K" (SPR_HID0));
 588
 589         /* Configure power-saving mode */
 590         switch (vers) {
 591         case IBM970MP:
 592                 hid0_hi |= (HID0_DEEPNAP | HID0_NAP | HID0_DPM);
 593                 hid0_hi &= ~HID0_DOZE;
 594                 break;
 595         default:
 596                 hid0_hi |= (HID0_NAP | HID0_DPM);
 597                 hid0_hi &= ~(HID0_DOZE | HID0_DEEPNAP);
 598                 break;
 599         }
 600         powerpc_pow_enabled = 1;
 601
 602         __asm __volatile (" \
 603                 sync; isync;                                    \
 604                 sldi    %0,%0,32; or %0,%0,%1;                  \
 605                 mtspr   %2, %0;                                 \
 606                 mfspr   %0, %2; mfspr   %0, %2; mfspr   %0, %2; \
 607                 mfspr   %0, %2; mfspr   %0, %2; mfspr   %0, %2; \
 608                 sync; isync"
 609             :: "r" (hid0_hi), "r"(hid0_lo), "K" (SPR_HID0));
 610
 611         __asm __volatile ("mfspr %0,%1; srdi %0,%0,32;"
 612             : "=r" (hid0_hi) : "K" (SPR_HID0));
 613         printf("cpu%d: HID0 %b\n", cpuid, (int)(hid0_hi), HID0_970_BITMASK);
 614 #endif
 615
 616         cpu_idle_hook = cpu_idle_60x;
 617 }
 618
 619 static void
 620 cpu_powerx_setup(int cpuid, uint16_t vers)
 621 {
 622
 623 #ifdef __powerpc64__
 624         if ((mfmsr() & PSL_HV) == 0)
 625                 return;
 626
 627         /* Configure power-saving */
 628         switch (vers) {
 629         case IBMPOWER8:
 630         case IBMPOWER8E:
 631                 mtspr(SPR_LPCR, mfspr(SPR_LPCR) | LPCR_PECE_WAKESET);
 632                 isync();
 633                 break;
 634         default:
 635                 return;
 636         }
 637
 638         cpu_idle_hook = cpu_idle_powerx;
 639 #endif
 640 }
 641
 642 static int
 643 cpu_feature_bit(SYSCTL_HANDLER_ARGS)
 644 {
 645         int result;
 646
 647         result = (cpu_features & arg2) ? 1 : 0;
 648
 649         return (sysctl_handle_int(oidp, &result, 0, req));
 650 }
 651
 652 void
 653 cpu_idle(int busy)
 654 {
 655         sbintime_t sbt = -1;
 656
 657 #ifdef INVARIANTS
 658         if ((mfmsr() & PSL_EE) != PSL_EE) {
 659                 struct thread *td = curthread;
 660                 printf("td msr %#lx\n", (u_long)td->td_md.md_saved_msr);
 661                 panic("ints disabled in idleproc!");
 662         }
 663 #endif
 664
 665         CTR2(KTR_SPARE2, "cpu_idle(%d) at %d",
 666             busy, curcpu);
 667
 668         if (cpu_idle_hook != NULL) {
 669                 if (!busy) {
 670                         critical_enter();
 671                         sbt = cpu_idleclock();
 672                 }
 673                 cpu_idle_hook(sbt);
 674                 if (!busy) {
 675                         cpu_activeclock();
 676                         critical_exit();
 677                 }
 678         }
 679
 680         CTR2(KTR_SPARE2, "cpu_idle(%d) at %d done",
 681             busy, curcpu);
 682 }
 683
 684 static void
 685 cpu_idle_60x(sbintime_t sbt)
 686 {
 687         register_t msr;
 688         uint16_t vers;
 689
 690         if (!powerpc_pow_enabled)
 691                 return;
 692
 693         msr = mfmsr();
 694         vers = mfpvr() >> 16;
 695
 696 #ifdef AIM
 697         switch (vers) {
 698         case IBM970:
 699         case IBM970FX:
 700         case IBM970MP:
 701         case MPC7447A:
 702         case MPC7448:
 703         case MPC7450:
 704         case MPC7455:
 705         case MPC7457:
 706                 __asm __volatile("\
 707                             dssall; sync; mtmsr %0; isync"
 708                             :: "r"(msr | PSL_POW));
 709                 break;
 710         default:
 711                 powerpc_sync();
 712                 mtmsr(msr | PSL_POW);
 713                 isync();
 714                 break;
 715         }
 716 #endif
 717 }
 718
 719 static void
 720 cpu_idle_booke(sbintime_t sbt)
 721 {
 722         register_t msr;
 723         uint16_t vers;
 724
 725         msr = mfmsr();
 726         vers = mfpvr() >> 16;
 727
 728 #ifdef BOOKE
 729         switch (vers) {
 730         case FSL_E500mc:
 731         case FSL_E5500:
 732         case FSL_E6500:
 733                 /*
 734                  * Base binutils doesn't know what the 'wait' instruction is, so
 735                  * use the opcode encoding here.
 736                  */
 737                 __asm __volatile(".long 0x7c00007c");
 738                 break;
 739         default:
 740                 powerpc_sync();
 741                 mtmsr(msr | PSL_WE);
 742                 isync();
 743                 break;
 744         }
 745 #endif
 746 }
 747
 748 #ifdef __powerpc64__
 749 static void
 750 cpu_idle_powerx(sbintime_t sbt)
 751 {
 752
 753         /* Sleeping when running on one cpu gives no advantages - avoid it */
 754         if (smp_started == 0)
 755                 return;
 756
 757         spinlock_enter();
 758         if (sched_runnable()) {
 759                 spinlock_exit();
 760                 return;
 761         }
 762
 763         if (can_wakeup == 0)
 764                 can_wakeup = 1;
 765         mb();
 766
 767         enter_idle_powerx();
 768         spinlock_exit();
 769 }
 770 #endif